DESIGN AND ANALYSIS OF 1-BIT FULL

ADDER BASED ON CMOS AND DOMINO

LOGIC TECHNIQUES
P. Ramesh Department of CH. Santhoshini R. Anonya
ECE Department of ECE, Department of ECE,
MLR Institute of MLR Institute of Technology, MLR Institute of
Technology, Hyderabad Hyderabad Technology, Hyderabad
India–500043 India–500043 India–500043
ramesh.peddaveni@mlrinstitutions chsanthoshini2003@gmail.com ranguanonya@gmail.co
.ac.in
m

B. Sandeep
Department of ECE, B. Chandu
MLR institute of Technology, Department of
Hyderabad ECE,
India–500043 MLR institute of
bantusandeep123@gmail.com Technology,
Hyderabad
India–500043

chandunayak777@gmail.com

Abstract—For decades, CMOS technology has been used So, a technology is required to overcome these limitations.
in the semiconductor industry to produce circuits, but the Hence, we use domino logic for designing a 1-bit full adder
number of transistors raises, so does the device area and and comparing the parameters in both the technologies.
delay. In this project, one-bit full adder circuit with CMOS In the rapidly expanding VLSI industry, transistor density
logic and domino logic was developed in the Cadence virtuoso
is consistently on the rise. As the transistor count increases, it
EDA software using 90nm technology and by providing
different supply voltages their parameters are measured from
inevitably leads to amplified device area, latency, and power
the waveforms. This project, focuses on the creation of consumption. Over the past few decades, the semiconductor
space-saving and fast-moving devices. This project compares industry has predominantly relied on CMOS technology for
the size, latency,and power consumption of CMOS and chip design. However, due to the escalating transistor count,
domino logic based on full adder circuits. A comparative both device area and latency are growing [2,3]. Consequently,
analysis revealed that a one-bit full adder circuit employing there is a pressing need to transition to a technology that offers
Domino logic occupies a smaller footprint and demands lower reduced area and diminished latency. This has led to the
power consumption in comparison to a one-bit full adder adoption of Domino logic for the design of one-bit full adders,
circuit based on CMOS logic. with a subsequent comparison of performance parameters,
Keywords—power, speed, Cadence, CMOS, Domino, size. including area, latency, and power consumption, between the
two Technologies. The exploration of one-bit full adder design
I.INTRODUCTION and analysis through the utilization of CMOS and Domino
logic techniques is a fundamental aspect within the domain of
The process of very large-scale integration involves the
digital circuit design. This investigation delves deeply into the
integration of thousands of transistors into a single chip,
intricate realm of integrated circuit design, with the objective
resulting in the creation of an integrated circuit. VLSI is
of scrutinizing the performance, efficiency, and power
mainly used to design electronic components like
consumption associated with these two prevalent logic
microprocessor and memory chips, which required millions of
methodologies. Given the one-bit full adder's pivotal role in
transistors. From the past few decades CMOS
arithmetic and data processing circuits, optimizing its design
technology is being used for designing the chips in for contemporary applications becomes imperative.
semiconductor industries. As we can see the transistor density
The primary goal of this inquiry is to illuminate the
is increasing day by day thus making the circuit consume more
advantages and disadvantages of incorporating CMOS and
power, area and delay.
Domino logic techniques in one-bit full adder design. The
study immerses itself in the constantly evolving landscape of
the semiconductor industry, where the pursuit of compact
device footprints, minimized latency, and energy-efficient Virtuoso 6.1.7 software, 180nm technology for analyzing the
solutions is paramount. Through a comprehensive comparative full adder circuit. Domino logic has demonstrated superior
analysis of design and performance metrics for one-bit full accuracy and efficiency with fewer transistors and minimal
delay in comparison to CMOS design logic. .There are almost
adders implemented with both CMOS and Domino logic, our
no glitches in Domino logic transient analysis. Further there is
objective is to provide valuable insights that can shape future a decrease in chip area by 28.5% and delay by 47.37% in
innovations in digital circuit design. This research significantly Domino logic as compared to CMOS logic. Further, as shown
contributes to the ongoing quest for enhanced efficiency and in the power graph of CMOS logic and Domino logic it was
more robust computing solutions, thereby advancing the observe that instantaneous power is more in CMOS based logic
state-of-the-art in VLSI and integrated circuit technology. as compare to the Domino logic so there are more chances of
device failure in CMOS logic as compare to the Domino logic.

II.LITERATURE SURVEY
Researchers have sought to optimize and refine these
designs for diverse applications, contributing to advancements IV.PROPOSED SYSTEM
in digital circuit design. This literature survey underscores the
importance of making informed choices based on specific
project requirements and offers a pathway for future FULL ADDER:
investigations into hybrid approaches and
tailored optimizations. The full adder serves as a fundamental cornerstone in both
digital electronics and computer architecture. Its primary role
In their study, Ravi Tiwari and Khemraj Deshmukh, a PG revolves around the addition of three binary inputs: A, B, and
student and an assistant professor, respectively, from the
a carry-in bit known as C_in, yielding two key outputs in the
Department of VLSI at Shri Shankaracharya Technical Campus
(FET) in Bhilai, Chattisgarh, India, made a significant form of the sum (S) and a carry-out (C_out). The values of
observation. They found that in a prior instance, a 10-transistor these outputs are determined through a truth table that
full adder circuit had been designed, consuming a substantial accounts for various input combinations.
60 watts of power. In their current work, they introduced an
11-transistor full adder circuit which demonstrated a notable Notably, the sum output embodies the least significant bit
reduction in power consumption, down to 40 watts, as of the overall addition result, while the carry-out assumes the
compared to the earlier 10-transistor full adder design. crucial task of carrying over any excess to the subsequent
stage in multi-bit addition processes. Employing logic gates
N. Lokabharath Reddy, Mohinder Bassi, and Shekhar such as XOR, AND, and OR gates, full adders are essential
Verma conducted a comparative study of four different full components in facilitating arithmetic operations, forming the
adder designs using 90nm technology in Cadence Virtuoso.
foundational building blocks for the creation of adders,
Among these, the Domino 22T full adder outperformed others
with superior delay and PDP values at a 33 MHz frequency in subtractors, and arithmetic logic units (ALUs) within digital
CMOS 90nm technology. Variation in transistor sizes had an systems. The combined arrangement of multiple full adders
impact on average power, effectively addressing threshold loss grants the capability to construct larger adders, instrumental in
concerns. Additionally, the SERF 10T full adder exhibited multi-bit binary addition, thereby enabling critical calculations
lower power consumption compared to conventional designs. in computer systems and diverse digital devices.
It's important to note that both delay and power consumption
are contingent on the operating frequency. Based on their
findings, the Domino 22T full adder is the recommended
choice for arithmetic operations due to its favorable delay
characteristics.

Nandani Choudhary, Mayank Sinha, Raghav Agarwal,

Harsh Tiwari, and Dheeraj Singh, hailing from ABES
Engineering College in Ghaziabad, India, noted that the choice
between Static Logic and Dynamic CMOS Logic hinges on the
specific application at hand. Static logic, as seen in NAND and
NOR gates, offers advantages such as simplicity,
cost-effectiveness, and comparable performance. However, for
more intricate tasks like microcontroller design, dynamic logic
proves to be the superior choice. Their study underscores the
significance of selecting the appropriate logic and voltage
variations for achieving the development of VLSI chips that
are both high-performance and low-power. Fig1: full adder logic diagram

In this paper designing of full adder circuit using the CMOS

logic and Domino logic has been done. We used Cadence
 Fig 2: Truth table of full adder Fig 3: Circuit diagram of CMOS Inverter.
CMOS LOGIC: DOMINO LOGIC:
A 90nm CMOS technology node is a critical and In the realm of digital circuit design, a 20-transistor (20T)
well-established semiconductor manufacturing process in the full adder implemented using domino logic is a noteworthy
world of integrated circuits. In this context, a 28-transistor approach that combines speed and power efficiency. Domino
(28T) full adder design becomes a crucial component for logic is a dynamic logic family that excels in
arithmetic operations in digital circuits. The full adder is a high-performance applications, often characterized by its
fundamental building block in digital logic, capable of adding non-static nature and compact design. The 20T full adder
three binary inputs, typically two operands and a carry-in, to leverages this methodology to efficiently add three binary
produce a sum and carry-out. The use of 28 transistors in its inputs, typically two operands and a carry-in, providing a sum
implementation indicates a complex and robust approach to and carry-out as outputs. With a reduced transistor count
achieving this functionality, offering advantages in terms of compared to some traditional implementations, it can offer a
speed and power efficiency. This technology node and balance between performance and silicon area utilization. This
transistor count are essential considerations in modern design is particularly valuable in applications where
microelectronics, where efficiency and performance are of optimizing speed and minimizing power consumption are
paramount importance. paramount, making it a relevant choice in modern
This full adder harmoniously combines three binary inputs semiconductor technology.
- A, B, and carry-in (C-in) - yielding two significant outputs:
the sum (S) and carry-out (C-out). Through the meticulous
orchestration of CMOS transistors, this design offers a potent
solution for digital arithmetic operations. Its compact form and
energy-efficient implementation ensure minimal power
consumption, all while delivering high-performance
computational capabilities. This 28-transistor CMOS full
adder is a cornerstone of modern integrated circuits,
empowering the development of intricate arithmetic logic units
and processors, making it an indispensable element within the
realm of digital computing systems.

Fig 4: Domino logic block diagram.

SCHEMATIC DIAGRAMS:
 The project's results tell us that when you're deciding
between CMOS and Domino logic for a 1-bit full adder,
you've got to juggle space, speed, and power use. If you don 't
have strict limits on space, CMOS lets you tweak the speed,
but it takes up more room. On the other hand, if speed is your
jam and you want to save power, Domino logic is the way to
go. So, you 've got to think about your project's needs and
choose the logic that fits. And there's room for more research
to mix and match these approaches for specific jobs.

Fig 5: Schematic of Full Adder using CMOS Logic

Fig 9: Transient Response of CMOS Logic Design

Fig 6: Test Bench of Full Adder using CMOS Logic

Fig 7: Schematic of Full Adder using Domino Logic

Fig 8: Test Bench of Full Adder using Domino Logic

IV. RESULTS AND DISCUSSION

 Fig 12: Power Analysis of Full Adder using Domino Logic

Analysis:

Fig 10: Power Analysis of CMOS Logic Design

Comparison of Results:
Parameters Full Adder Full Adder
using CMOS using Domino
Logic Logic
Technology 90nm 90nm
Number of 28 20
Transistors
Power 311.31 161.04
Consumption
Cost Moderate Cost-Effective
Size Moderate Smaller

Fig 11: Transient Response of Domino Logic Design Complexity High Low
Speed Low compared to High
Domino Logic

V.CONCLUSION:
In the comparative analysis, we observed that the CMOS
full adder is more stable and less power-hungry, while the
domino logic full adder offers superior speed but at the cost of
higher dynamic power consumption. The choice between these
techniques depends on the specific requirements of the
application, with CMOS being a safe bet for reliability and
power efficiency, and domino logic being a preferred choice
for applications where speed is of paramount importance, even
if it comes at the expense of higher power consumption. The
final decision should be based on a careful evaluation of the
trade-offs and the specific needs of the system being designed.

VI. REFERENECS:
[1] Gaetano Palumbo, Melita Pennisi, Massimo Alioto
proposed a simple approach to reduce delay changes in
Domino logic Gates, IEEE transaction on Circuits and
System, Vol. 59, pp. 10-14, October 2012.

[2] Thorp, K. Himabindu and K. Hariharan, "Design of

area and power efficient Full Adder in 90nm," 2017
International Conference on Networks & Advances in
Computational Technologies (Net ACT),
Thiruvanthapuram, pp. 336-340, 2017.

[3] Thakur, R., Dadoria, A. K., & Gupta, T. K performed

Comparative analysis of various Domino logic circuits
for better performance, International Conference on
Advances in Electronics, Computers and
Communications (ICAECC), pp. 1-6, 2019.
[4] K. Bernstein, J. Ellis-Monaghan, E. Nowak
implemented High-Speed Design Styles Leverage IBM
Technology Prowess, IBM Micro News, vol. 4, no. 3,
1998.

[5] F. Frustaci M. Lanuzza P. Zicari S. Perri and P.

Corsonello proposed Low-power split-path data-driven
dynamic logic, IET Circuits Devices Syst., Vol. 3, Iss. 6,
pp. 303-312, 2009

[6] V. Kursun, and E. G. Friedman, "Low swing dual

threshold voltage domino logic," in Proc. ACM/SIGDA
Great Lakes Symp. VLSI, pp. 47- 52, 2018.

[7] Zhiyu Liu, Volkan Kursun published PMOS-Only

Sleep Switch Dual-Threshold Voltage Domino Logic in
Sub-65-nm CMOS Technologies, IEEE Trans. Very
Large-Scale Integration (VLSI) Systems, vol. 15, no. 12,
DEC. 2007

[8] Zhiyu Liu, Volkan Kursun stated the Leakage Power

Characteristics of Dynamic Circuits in Nanometer CMOS
Technologies, IEEE Trans. Circuits and Systems-II, vol.
53, no. 8, 2006.

[9], S. M., Abdalla, Y. S., Dessouki, A. A. El-Badawy, E.

S. A., “A novel low-power and high-speed dynamic
CMOS logic circuit technique” IEEE confrenceIn Radio
Science Conference, National pp. 1-8, 2009.

[10] P. Mazumder and L. Ding, "On Circuit Techniques

to Improve Noise Immunity of CMOS Dynamic Logic,”
IEEE Transactions on Circuits and Systems, 2004