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Cao Unit-3 QB

The document contains questions about various topics related to pipelining and instruction processing in computer architecture including data hazards, data path and control lines, hardwired control units, instruction hazards, micro-programmed control, multiple bus organization, pipelining, single bus organization, and superscalar. It includes questions about defining, explaining, drawing diagrams, and writing control sequences for various components of pipelined instruction processing.

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0% found this document useful (0 votes)
74 views2 pages

Cao Unit-3 QB

The document contains questions about various topics related to pipelining and instruction processing in computer architecture including data hazards, data path and control lines, hardwired control units, instruction hazards, micro-programmed control, multiple bus organization, pipelining, single bus organization, and superscalar. It includes questions about defining, explaining, drawing diagrams, and writing control sequences for various components of pipelined instruction processing.

Uploaded by

AFRID. SK
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Mappins

Questions in Unit-3 Pattern Marks


COs
Topic: DATA HAZARD
|
84828 How data hazard can be prevented in pipelining?. Draw Understand CO3 2
the diagram for Operand Forwarding.
92370 What is the classification of data hazards? Understand C03 2
|97953 What is data hazard? Explain the methods for dealing with the Understand CO3 8
data hazards.
Topic: DATA PATH AND CONTROL LINE
92413 Whatis data path and control path? Understand C03 2

98149 Describe the data and control path techniques in pipelining. Understand CO3 8

Topic: HARDWIRED CONTROL UNIT


92299 What is a hardwired control unit? Understand CO3 2

92319 What is the difference between hardwired and Understand CO3 2


microprogrammed control unit?
98172 Sketch the neat diagram for hardwired control and explain the Understand CO3 8
working principle.
Topic: INSTRUCTION HAZARD
84904 Define Instruction hazards. Understand CO3 2

98151 | What is instruction hazard? Explain in detail how to handle the Understand CO3 8
instruction hazards in pipelining with relevant examples

Topic: MICRO-PROGRAMMED CONTROL


84982 What is a micro-program sequencer? Remember CO3 2

https://edu.kalasalingam.ac.in/question_bank_report/1579 4/8
98322 Explain in detail aboutmicro programmed control. Understand C03 8

Topic: MULTIPLE BUS ORGANIZATION


84941 Forthe multiple bus organization, write the complete control Apply CO3 2
sequence for the instruction: Add R4,R5,R6
Topic: PIPELINING
|84763 Define parallel processing. Remember CO3 2

84961 Define pipelining. Remember CO3

92320 Drawthe hardware organization of four stage pipeline. Understand CO3 2

92328 What are the steps required for a pipelined processor to Understand CO3 2
process the instruction?
97914 Discuss the basic concepts of pipelining. Understand CO3 8

Topic: SINGLE BUS ORGANIZATION


84959 For the single bus organization, write the complete control Apply C03 2
sequence for the instruction: Move (R1), R1

92339 Listthe drawbacks ofmicro programmed control Apply CO3 2

98154 Explain in detail about Single bus organization with Understand CO3 8
suitable diagram
98157 How the register transfer operation being performed in Understand CO3 8
single bus organization and explain with neat diagram.
98166 Describe the execution of complete instruction with suitable Apply CO3 8
example.
98179 Write the sequence of control steps required for the single Apply CO3 8
|
bus organization in each of the following
instructions:
a) Add the immediate number NUM to register R1.
|
b) Add the contents of memory-location NUM to register
R1.
Assume that each instruction consists of two words. The
first word specifies the operation and the addressing mode,
and the second word contains the number NUM
Topic: SUPER SCALAR
92296 What is the essential characteristic ofthe superscalar Understand CO3 2
approach to processor design?

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