library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SuperContador is
Port ( clk : in STD_LOGIC;
clksal: out STD_LOGIC;
reset : in STD_LOGIC;
speed : in STD_LOGIC;
sal : out STD_LOGIC_VECTOR (6 downto 0);
unidad: inout STD_LOGIC_VECTOR (3 downto 0);
decena: inout STD_LOGIC_VECTOR (3 downto 0);
centena: inout STD_LOGIC_VECTOR (3 downto 0);
millar: inout STD_LOGIC_VECTOR (3 downto 0);
an0 : out STD_LOGIC;
an1 : out STD_LOGIC;
an2 : out STD_LOGIC;
an3 : out STD_LOGIC);
end SuperContador;
architecture Behavioral of SuperContador is
signal clk_div : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal sel : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal s : STD_LOGIC_VECTOR(14 downto 0);
signal s14_val : STD_LOGIC; -- Variable para almacenar s(14)
begin
-- Divisor de frecuencia
process(clk)
begin
if rising_edge(clk) then
clk_div <= clk_div + 1;
end if;
end process;
-- Señal de salida del divisor de frecuencia
clksal <= clk_div(23);
-- Contador de 0 a 9999
process(clksal, reset)
begin
if reset = '1' then
unidad <= "0000";
decena <= "0000";
centena <= "0000";
millar <= "0000";
elsif rising_edge(clksal) then
-- Almacenar el valor de s(14) en la variable s14_val
s14_val <= s(14);
if speed = '0' then
-- Velocidad normal: Incrementa en cada ciclo de clksal
if unidad = "1001" then
unidad <= "0000";
if decena = "1001" then
decena <= "0000";
if centena = "1001" then
centena <= "0000";
if millar = "1001" then
millar <= "0000";
else
millar <= millar + 1;
end if;
else
centena <= centena + 1;
end if;
else
decena <= decena + 1;
end if;
else
unidad <= unidad + 1;
end if;
else
-- Velocidad rápida: Incrementa cada dos ciclos de clksal
if s14_val = '1' then
if unidad = "1001" then
unidad <= "0000";
if decena = "1001" then
decena <= "0000";
if centena = "1001" then
centena <= "0000";
if millar = "1001" then
millar <= "0000";
else
millar <= millar + 1;
end if;
else
centena <= centena + 1;
end if;
else
decena <= decena + 1;
end if;
else
unidad <= unidad + 1;
end if;
end if;
end if;
end if;
end process;
-- Multiplexor
process(unidad, decena, centena, millar, sel)
begin
case sel is
when "00" =>
sal <= unidad;
when "01" =>
sal <= decena;
when "10" =>
sal <= centena;
when "11" =>
sal <= millar;
end case;
end process;
-- Decodificador
process(sal)
begin
case sal is
when "0000" =>
sal <= "0000001";
when "0001" =>
sal <= "1001111";
when "0010" =>
sal <= "0010010";
when "0011" =>
sal <= "0000110";
when "0100" =>
sal <= "1001100";
when "0101" =>
sal <= "0100100";
when "0110" =>
sal <= "0100000";
when "0111" =>
sal <= "0001111";
when "1000" =>
sal <= "0000000";
when "1001" =>
sal <= "0000100";
when others =>
sal <= "1111111";
end case;
end process;
-- Divisor de frecuencia para el contador de 0 a 3
process(clksal)
begin
if rising_edge(clksal) then
s <= s + 1;
end if;
end process;
-- Contador de 0 a 3
process(s(14))
begin
if rising_edge(s(14)) then
sel <= sel + 1;
end if;
end process;
-- Decodificador de activación de ánodo
process(sel)
begin
case sel is
when "00" =>
an0 <= '1';
an1 <= '0';
an2 <= '0';
an3 <= '0';
when "01" =>
an0 <= '0';
an1 <= '1';
an2 <= '0';
an3 <= '0';
when "10" =>
an0 <= '0';
an1 <= '0';
an2 <= '1';
an3 <= '0';
when "11" =>
an0 <= '0';
an1 <= '0';
an2 <= '0';
an3 <= '1';
when others =>
an0 <= '0';
an1 <= '0';
an2 <= '0';
an3 <= '0';
end case;
end process;
end Behavioral;
