, . .

, commodore MPS
~ aernlconduct:or group 6532
[K!J~@~
MEMORY,
I/O, TIMER
ARRAY

6532 (MEMORY, 110, TIMER ARRAY)

THE 8532 CONCEPT-
The 6532 Is designed to operate In conjunction with the MCS650X Microprocessor Family. It is
comprised of a 128 x 8 static RAM, two software controlled 8 bit bl-dlrectional data ports allowing
direct Interfacing between the microprocessor unit and peripheral devices, a software programmable
Interval timer with Interrupt capable of timing In various Intervals from 1 to 262,144 clock periods, and
a programmable edge detect circuit.

FEATURES OF THE 8532

• 8 bit bl-dlrectlonal Data Bus for direct • High Impedance Three-State Data Pins
communication with the microprocessor • 1 MHz, 2MHz and 3MHz operation
• Programmable edge-sensitive Interrupt
• 128 x 8 static RAM
• Two 8 bit bl-dlrectlonal data ports for
Interface to peripherals
• Two programmable 110 Peripheral Data
Direction Registers
• Programmable Interval Timer
• Programmable Interval Timer Interrupt
• TTL & CMOS compatible. peripheral lines
• Peripheral pins with Direct Transistor
Drive Capability

8532 PIN DESIGNATION

ORDERING INFORMATION
MXS6532_~ vss .0.6
.0.5 02
.0.4 CSI
"3 CS2
"2 liS
AI R/W
AD REs
PAD OBO
p.o., DB,
FREQUENCY RANGE
PA2 DBz
NO SUFFIX = 1 MHz
PA3 OB3
A = 2 MHz
PA4 DB4
PA5 085
L...-_ _ _ _ _ _ PACKAGE DESIGNATOR PA6 086
PA7 OB7
C=CERAMIC
P= PLASTIC P87 I"RQ
P86 PBO
P85 P81
PB4 PBZ
VOO PB3

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6532
BLOCK DIAGRAM

DO
01 DATA
DIRECTION
02 DATA CONTROL
03 BUS REGISTER
04 A
BUFFER
D!5
06 OUTPUT
07 REGISTER A

CSI
CS2 CHIP
02 SELECT
PA7
R/W
PERIPHERAL PA6
RES
PA!5
DATA
PA4
BUFFER
PA3
A
Rs PA2
PAl
PAO

IRQ

PB7
PB6
PERIPHERAL
PB5
DATA
PB4
BUFFER
PB3
B
PB2
AO
ADDRESS PBI
AI
DECODERS PBO
A2
A3
A4
A!5
A6 OUTPUT
REGISTER B

DATA
DIRECTION
CONTROL
REGISTER
B

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6532
MAXIMUM RATINGS
RATING SYMBOL VOLTAGE UNIT
Supply Voltage vee -.3 to +7.0 V
InputlOutput Voltage VIN -.3 to + 7.0 V
Operatlng'Temperature Range TOp Oto 70 ·C
Storage Temperature Range TSTG -55 to + 150 ·C

All Inputs contain protection Circuitry to prevent damage due to high static charges. Care should be
exercised to prevent unnecessary application of voltage outside the specified range.

I
ELECTRICAL CHARACTERISTICS (VCC - 5.OV ± 5%, VSS = OV, TA = o.70 C)0

CHARACTERISTIC SYMBOL MIN, TYP, MAX, UNIT

Input High Voltage VIH VSS+2,4 1,3 vee v

---
Input Low Voltage VIL VSS-·3 1.1 VSS + ,8 V
- ----- e----- - - - - -

Input Leakage Current; VIN =

Vss + 5v liN - 1,0 2,5 ~
M-M,~, AIN, m,
02, CS1,CS2
- f---------- --
Input Leakage CUlTent lor High Impedance State IrSI - ±1,0 ±10,0 ~
(Three State); VIN =,4v to 2,4V; 00{)7
----
Input High CUlTent; VIN = 2.4v IIH -100, -300, - ,.A
PM-PA7, Pa0.P87
------ ---
Input Low CUlTent; VIN = .4v IlL - -1,0 -1,6 mA
PM-PA'I, PfIO.P87

Output High Voltage

vee ,. MIN, ILOAD ~ • 100,.A(PM-PA7, P8().PB7, [)()'D7) VOH VSS+2.4 3.5 VCC V

----
Output Low Voltage

vee • MIN, ILOAD!£ 1.8MA VOL Vss ,2 VSS+.4 V

Output High Current (Sourclng~

VOH ~ 2.4v (PA()'PA7, P8().PB7, [)()'D7) IOH
. -100 -1000
-
,.A
--

f-'
O-utput Low Current (SInking); VOL.s. ,4v (PM-PA7) (P8().PB7) IOL 1.8 3,0 -- mA

f---. -
Clock Input Capacitance Cclk - 18 30 pI
---
r--'
Input lCapacltance CIN - 7 10 pI
.•.• _--
f----

_.
Output Capacitance CollT - 7 10 pI

Power Dltt:Slpation Po - 500 1000 mW

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8532
WRITE TIMING CHARACTERISTICS

DATA BUS

,.... - - - - - - - - - - - Vce- 30 %
I~+-~---------- 2.4V
PERIPHERAL

DATA ---------------lr----" "-+.:,:8V:........_ _ _ _ _ _ _ _ _ _ O.4V

READ TIMING CHARACTERISTICS

CLOCK INPUT
--------

ADDRESS

PERIPHERAL
DATA

DATA BUS _ _ _ _ _ _ _ _"""\.

____________ ~~Tle _ _- - -

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6532
WRITE TIMING CHARACTERISTICS

1MHz 2MHz 3MHz

CHARACTERISTIC SYMBOL MIN MAX MIN MAX MIN MAX UNIT
Clock Period TCYC 1 20 .5 10 0.33 10 fJS
Rise & Fall Times TR, TF - 25 - 25 - 25 nS
Clock Pulse Width TC .470 10 .235 5 0.160 5 fJS
R/W valid before positive transition of
clock TWCW 180 - 90 - 60 - nS

I
Address valid before positive transition
of clock TACW 1130 - 90 - 60 - nS
Data Bus valid before negative transition
of clock TDCW aoo - 150 - 100 - nS
Data Bus Hold Time THW 10 - 10 - 10 - nS
Peripheral data valid after negative
transition of clock TCPW - 1 - .500 - .333 fS
Peripheral data valid after negative
transition of clock driving CMOS
(Level=VCC-30%) TCMOS - 2 - 1 - .666 }JS

READ TIM ING CHARACTERISTICS

1MHz 2MHz 3MHz

CHARACTERISTIC SYMBOL MIN MAX MIN MAX MIN MAX UNIT

R/W valid before positive transition of
clock TWGR 180 - 90 - 60 - nS
Address valid before positive transition
of clock TACR 180 - 90 - 60 - nS
Peripheral data valid before positive
transition of clock TPCR 300 - 150 - 100 - nS
Data Bus valid after positive transition
of clock TCDR - 400 - 200 - 135 nS
Data Bus Hold Time THR 10 - 10 - 10 - nS
IRQ valid before positive transition of
clock TIC 200 - 100 - 75 - nS

Loading = 30 pf + 1 TTL load

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6532
INTERNAL ORGANIZATION
A block diagram of the Internal architecture Is shown In Figure 1. The 6532 Is divided Into four basic sec-
tions, RAM, 1/0, TIMER, and Interrupt Control. The RAM Interfaces directly with the microprocessor through
the system data bus and address lines. The 110 section consists of two 8-blt halves. Each half contains a
Data Direction Register (DDR) and an I/O Register.

RAM-128 Byte. (1024Blt8)

The 128 x 8 ReadlWrlte memory acts as a conventional static RAM. Data can be written Into the RAM from
=
the microprocessor by selecting the chip (CS1 = 1, ~ 0) and by setting AS to a logic 0 (0.4v). Address
lines AO through AS are then used to select the desired byte of storage.

Intemal Peripheral Registers

The Peripheral A I/O port consists of eight lines which can be Individually programmed to act as either an
Input or an output. A logic zero In a bit of the Data Direction Register (DORA) causes the corresponding line
of the PA port to act as an Input. A logic one causes the corresponding PA line to act as an output. The
voltage on any line programmed to be an output Is determined by the corresponding bit in the Output
Register (ORA).

Data Is read directly from the PA pins during any read operation. For any output pin, the data transferred Into the
processor will be the same as that contained In the Output Register if the voltage on the pin Is allowed to go to 2.4v
for a logic one. Note that for Input lines, the processor can write Into the corresponding bit of the Output Register.
This will not affect the polarity on the pin until the corr'9sponding bit of DORA is set to a logiC one to allow the
peripheral pin to act as an output.

In addition to acting as a peripheralI/O line, the PA7line can be used as an edge-detecting input. In this mode,
an active transition will set the internal interrupt flag (bit 6 of the Interrupt Flag register). Setting the interrupt flag
will cause fRO output to go low If the PA71nterrupt has been enabled. The PA7line should be set up as an input for
this mode.

Control of the PA7 edge detecting mode is accomplished by writing to one of four addresses. In this operation,
AO controls the polarity of the active transition and A1 acts to enable or disable interrupting of the processor. The
data which is placed on the Data Bus during this operation is discarded and has no effect on the control of PA7.

Setting of the PA7 interrupt flag will occur on an active transition even if the pin is being used as a normal input
or as a peripheral control output. The flag will also be set by an active transition If interrupting from PA7 is dis-
abled. The reset signal (RES) will disable the PA7 interrupt and will set the active transition to negative (high to
low). During the system initialization routine, it is possible to set the interrupt flag by a negative transition. It may
also be set by changing the polarity of the active Interrupt. It is therefore recommended that the interrupt flag be
cleared before enabling Interrupting from PA7.

Clearing of the PA7 Interrupt Flag occurs when the microprocessor reads the Interrupt Flag Register.

The operation of the Peripheral B Input/Output port is exactly the same as the normal I/O operation of the
Peripheral A port. The eight lines can each be programmed to act as either an input or as an output by placing a 0
or a 1 into the Data Direction register (DDRB). In the output mode, the voltage on a peripheral pin is controlled by
the Output Register (ORB).

The primary difference between the PA and the PB ports is in the operation of the output buffers which drive
these pins. The buffers are push-pull devices which are capable or sourcing 3 ma at 1.5v. This allows these pins to
directly drive transistor switches. To assure that the microprocessor will read proper data on a "Read PB" opera-
tion, sufficient logiC Is provided in the chip to allow the microprocessor to read the Output Register Instead of
reading the peripheral pin as on the PA port.

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 MPS

6532
INTERFACE SIGNAL DESCRIPTION
R...t(RES)
During system Initialization a logic "0" on the RES Input will cause a zeroing of all four 110 registers. This
In turn will cause all 1/0 buses to act as Inputs thus protecting external components from possible damage
and erroneous data while the system Is being configured under software control. The Data Bus Buffers are
put Into an OFF-5TATE during Reset. Interrupt capability Is disabled with the RES signal. The RES signal
must be held low for at least one clock period when reset Is required.

Input Clock
The Input clock is a system Phase Two clock which can be either a low level clock (Vil < 0.4, Vil > 2.4) or high
level clock (Vil < 0.2, VIH =
Vcc ~ :~)

ReadIWrlt. (RIW)
The RIW signal Is supplied by the microprocessor array and Is used to control the transfer of data to and
from the microprocessor array and the 6532. A high on the RIW pin allows the processor to read (with proper
addressing) the data supplied by the 6532. A low on the ANI pin allows a write (with proper addressing) to
the 6532.

Int.rru~t Request (iIm) .

The fRO pin is an Interrupt pin from the Interrupt control logic. The pin will be normally high with a low in-
dicating an Interrupt from the 6532. An external pull-up device Is required. The fRO pin may be activated by a
transition on PA7 or timeout of the interval timer.

Data Bus (OO-Dn

The 6532 has eight bi-directional data pins (00-07). These pins connect to the system's data lines and
allow transfer of data to and from the microprocessor array. The output buffers remain In the off state ex-
cept when a Read operation occurs and are capable of driving one standard TTL load and 130 pf.

Peripheral Data Ports

The 6532 has 16 pins available for peripheral I/O operations. Each pin is individually software programmable to act
as either an input or an output. The 16 pins are divided into 2 a-bit ports, PAo-PA7 and PBO-PB7. PA7 also has other
uses which are discussed in later sections. The pins are set as inputs by writing a "0" into the corresponding bit of the
data direction register. A "1" into the data direction register will cause the corresponding pin to be an output. When in
the input mode, the peripheral output buffers are in the" 1" state and pull-up device acts as less than one TTL load to the
peripheral data lines. On a Read operation, the microprocessor unit reads the peripheral pin. When the peripheral
device gets information from the 6532 it receives data stored in the data register. The microprocessor will read correct
information if the peripheral lines are greater than 2.0 volts for a "1" and less than o.a volts for a "0" as the peripheral pins
are all TTL compatible. Pins PBO-PB7 are also capable of sourcing 3 ma at 1.5v, thus making them capable of Darlington
drive. ..

Address Lines (Ao-A6) .

There are 7 address pins. In addition to these 7, there is a RAM SELECT pin. These pins, Ao-A6 and RAM SELECT,
are always used as addreSSing pins. There are two additional pins which are used as CHIP SELECTS. They are pins
CS1 and CS2.

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6532
Interval nnw
The Timer section of the 6532 contains three basic parts: preliminary divide down register, programmable 8-blt
register and Interrupt logic.

Figure 2. BASIC ELEMENTS OF INTERVAL TIMER

RIW PA7 A3 D7 De D6 Dol D3 D2 D1 DO RIW A1

• I' I. r r I

INTERRUPT PROGRAMMABLE - DIVIDE

- CONTROL REGISTER DOWN t2

I ~ . Ir

07 De os EM 03 02 01 DO

The Interval time can be programmed to count up to 255 time intervals. Each time interval can be either 1T, 8T,
64T or 1024T Increments, where T is the system clock period. When a full count is reached, an interrupt flag is set
to a logic "1". After the Interrupt flag Is set the internal clock begins counting down to a maximum of - 255T. Thus,
after the Interrupt flag Is set, a Read of the timer wi" tell how long since the flag was set up to a maximum of 255T.

The 8 bit system Data Bus is used to transfer data to and from the Interval Timer. If a count of 52 time intervals
were to be counted, the pattern 0 0 1 1 0 1 0 0 would be put on the Data Bus and written into the Interval Time
register.

At the same time that data Is being written to the Interval Timer, the counting intervals of 1, 8, 64, 1024T are
decoded from address lines AO and A 1. During a Read or Write operation address line A3 controls the interrupt
capability; I.e., A, = 1 enables IRO, A, = 0 disables IRO. When the timer is read prior to the interrupt flag being set,
the number of time Intervals remaining will be read, i.e., 51,50,49, etc.

When the timer has counted thru 00000000 on the next count time an interrupt will occur and the counter will
read 1 1 1 1 1 1 1 1. After Interrupt, the timer register decrements at a divide by "1" rate of the system clock. If after
Interrupt, the timer Is read and a value of 1 1 1 0 0 1 0 0 is read, the time since interrupt Is 27T. The value read is In
two's complement, but remember that interrupt occurred on count number. Therefore, we must subtract 1.

Value read = 1 1100 10 0

Complement = 0 0 0 1 1 0 1 1

ADD 1 = 0 0 0 1 1 1 0 0 = 28 Equals two's complement of register

SUB 1 =00011011 =27

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6532
Thus, to arrive at the total elapsed time, merely do a two's complement add to the original time written Into the
timer. Again, assume time written as 00 1 1 0 1 00 ( = 52). With a divide by 8, total time to Interrupt Is (52 x 8) + 1 =
417T. Total elapsed time would be 416T + 28T =
444T, assuming the value read after Interrupt was 11 1 001 0 O.

After the Interrupt, whenever the timer Is written or read the Interrupt Is reset. However, the reading of the timer
at the same time the Interrupt occurs will not reset the Interrupt flag. When the Interrupt flags are read (DB7 for the
timer, DB6 for edge detect) data bus lines DO-D5 go to O.

Figure 3. TIMER INTERRUPT TIMING

12 IN

I
~",T ~~_______________________________________________________________

1. Data written Into interval timers Is 0 0 1 1 0 1 0 0 = 52,0

2. Data In Interval timer Is 0 0 0 1 1 0 0 1 = 25,0
52.213.1 = 52·26-1 = 25
8
3. Data In Interval timer Is 0 0 0 0 0 0 0 0 = 010
52.4~5.1 =52·51·1 =0
4. Interrupt has occurred at 02 pulse #416
Data In Interval timer = 1 1 1 1 1 1 1 1
5. Data in Interval timer is 1 0 1 0 1 1 0 0
two's complement Is 0 1 0 1 0 1 0 0 = 8410
=
84 + (52x8) 50010

When reading the timer after an interrupt, A3 should be low so as to disable the IRQ pin. This is done so as to
avoid future Interrupts until after another Write operation.

Interrupt Flag Register

The Interrupt Flag Register consists of two bits: the timer interrupt flag and the PA7 interrupt flag. When a read
operation Is performed on the Interrupt Flag Register, the bits are transferred to the processor on the data bus, as
the diagram below, Indicates.

Figura 4. INTERRUPT FLAG REGISTER

7 6
I, 5 4 I I2
3 o I
j
·0·
PA7 FLAG
TIMER FLAG
The PA7 flag Is cleared when the Interrupt Flag Register is read. The timer flag is cleared when the timer register
is either written or read.

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 MPS
6532
ADDRESSING
Addesslng of the 6532 Is accomplished by the 7 addressing pins, the AS pin and the two chip select pins CS1
and CS'2. To address the R~ CS1 must be high with CS2 and AS low. To address the 110 and Interval timer CS1
and AS must be high with ~~ low. As can be seen to access the chip CS1 Is high and ~ is low. To distinguish
between RAM or 110 Timer the AS pin Is used. When this pin Is low the RAM Is addressed, when high the 110 Inter-
val timer section Is addressed. To distinguish between timer and 110 address line A2 is utilized. When A2 is high the
Interval timer Is accessed. When A2 Is low the 110 section Is addressed. Table 1 Illustrates the chip addressing.

Edge Sen.. Interrupt

In addition to Its use as a peripheral 110 line, the PA7 pin can function as an edge sensitive Input. In this mode,
an active transition on PA7 will set the Internal Interrupt flag (bit 6 of the Interrupt Flag Register). When this occurs,
and providing ttle PA7 Interrupt Is enabled, the lAO output will go low.

Control of the PA7 edge detecting logic Is accomplished by performing a write operation for one of four ad-
dresses. The data lines for this operation are "don't care" and the addresses to be used are found in Figure 4.

The setting of the Internal Interrupt flag by an active transition on PA71s always enabled, no matter whether PA7
Is set up as an Input or an output.

The RES signal disables the PA71nterrupt and sets the active transition to the negative edge-detect state. During
the reset operation, the Interrupt flag may be set by a negative transition. It may, therefore, be necessary to clear
the flag before its normal use as an edge detecting Input is enabled. This can be achieved by reading the Interrupt
Flag Register, as defined by Figure 4 immediately after reset.

110 Register-Timer Addreselng

Table 1 Illustrates the address decoding for the internal elements and timer programming. Address line A2
distinguishes 110 registers from the timer. When A2 Is low and Fffi is high, the 110 registers are addressed. Once the
110 registers are addressed, address lines A 1 and AO decode the desired register.

When the timer Is selected A 1 and AO decode the "divide-by" matrix. This decoding is defined in Table 1. In addi-
tion, Address A3 Is used to enable the Interrupt flag to fRO.

Table 1: ADDRESSING DECODE

OPERATION ~ ANI M A3 A2 Al

WrIte RAM 0 0
Read RAM 0 1
Write DORA 0 0 0
Read DORA 1 0 0
WrlteDDRB 0 0 1
Read DDRB 1 0 1 1
Wrlte Output Reg A 0 0 0 o
Read Output Reg A 1 0 0 o
Wrlte Output Reg B 0 0 o
Read Output Reg B 1 0 o
Write TImer
+IT 0 (s) 0 o
+BT 0 (s) 0 1
+64T 0 (s) o
+1024T 0 (s)
Read TImer (s)
Read Interrupt Flag(s) 1
Wrlte Edge Detect Control (b) (e)

NOTES:- = Don't care, '"1'" =High ItMtI (;o2.4V),'"0'" = Low I_I (.. 0.4V)
(.) A3 = 0 to disable Interrupt from timer to IRQ
A3 = 1 to enable interrupt from timer to iRQ
(b) Al =0 to disable Interrupt from PA7 to iR<:i
Al = 1 to en.ble Interrupt from PA7 to iR<:i
=
(e) AO 0 for negative edge-detect
AO = 1 for positive edge-detect

COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to
improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.

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