@ ) ug SECTION-B Discuss the required hardware, hardware algo ee rithm for ithm for the : 10 Design an arithmetic cireuit with one selection vatiable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with the input cay C, Draw the logic diagram for the first two stages Booth Multiplication Iterate your algori Product (+13 )*(-15). 10 5¢,=0 C= t 0 D=A+B D=A+1 1 D=A-I D=A+B41. A computer has 16 registers, an ALU with 32 operations, and a shifter with eight operations, all connected to a common bus system. (a) Formulate a Control word for a micro-operation. (b) Specify the number of bits in each field of the Control word and give a general encoding scheme. (c) Show the bits of the Control word that specify the micro- operation R4 < RS + R6. SECTION-C (a) Write the program to evaluate the expression 5519/600/777/1053 2 X= A*[B + C*™(D + E)] /F* (G+ H) using the Zero-Address instruction and One-Address instruction. 10 explain various addressing modes with suitable i eres: 10 - (a) What are the basic differences between a branch instruction, a call subroutine instruction and program interrupt ? Explain. 10 (b) Prove that a k-stage linear pipeline can be atmost k times faster than that of a non-pipelined serial processor. 10 secTion-pD (SF 1. A two-way set associative cache memory uses blocks of four words, The cache can accommodate a total of 2048 words from the main memory. The main memory size is 128 K432, 20 (@) Formulate all pertinent informations required to construct the cache memory. (©) What is the size of the cache memory ? ADMA controller transfers 16-bit words to memory using cycle stealing, The words are assembled from a device that transmits characters at the rate of 2400 characters per second. ‘The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. How much will the CPU be slowed down because of DMA transfer? Explain also.9. SECTION-E (Compulsory Question) State whether the followings are TRUE or FALSE. Give the proper justification also for each. (10x2=20) (a) ) © @ © © The speed imbalance between Memory access and CPU operations is reduced by memory interleaving. The idea of virtual memory is based on the —— of locality of reference. The XOR operator is distributive over AND operator. In INX H instruction bus remains idle for one cycle. Interrupt RST 5.5 is both level and edge sensitive. A micro-programmed control unit is faster than a Hard - wired control unit. (g) a) Parallel printer does not use RS-232C interface. An instruction pipeline operates on a stream of © instructions by overlapping the phases of instruction cycle.6 (a) ) Microprogrammed control unit is not suitable for RISC architecture. Justify the validity or otherwise of this statement. (10) Define instruction level parallelism. Write the important approaches available to exploit instruction level parallelism. (10) SECTION D 7. Define virtual memory. Explain how virtual address is translated into physical address using a suitable schematic diagram. (20) 8. (a) Illustrate the concept of bus interface in I/O data transfer. (10) (b) Explain the use of DMA controller in a computer system with a neat diagram. (10) SECTION-E (Compulsory Question) 9. (a) Define encoder. (b) Differentiate between virtual memory and cache memory. (©) Construct a T Flip-flop with a D-Flip-flop and an exclusive OR gate. (d) Define Pipeline. (©) What is the need of an interface between I/O device and CPU. (5x4=20) 5707/300/777/1187 3a i. Total No. of Questions — 9) [Total Pages : 3 (2122) 5733 B.Tech. (IT) Fresh New Syllabus (rd Semester) Examination (wef. Nov. 2021) COMPUTER ORGANIZATION (IT) Paper-IT-3001 (Common with New Syllabus 2019-24) Time : Three Hours) [Maximum Marks : 100 The candidates shall limit their answers precisely within the answer-book (40 pages) issued to them and no supplementary/ continuation sheet will be issued, Note : Attempt five questions in all, selecting one question from Section A, B, C and D. Section E is compulsory, All questions carry equal marks. SECTION-A 1. Draw the block diagram and explain the working of Von Neumann Architecture. 2. What is the difference between Hardwired and Micro- programmed control unit? Explain the timing and control of hardwired control unit. 5733/200/777/1195 s i$ IP.T.0.eee ae Fexmanent Adaress___—— erase < «questions oe soa cl to NOS 2, (@ Implement the following boolean function With 203) 8 x multiplexer i F(A, B,C, D) = 2 (0,3, 5, 6, 8, 9, 14, 15) (10) (b) Design a combinational circuit with four inputs ang four outputs that generates 2's complement of the input Hos ee binary number. (10) ao tes § SECTION-B arre cone a 3. Explain flow chart of Booth's multiplication algorithm in onset ion st detail. Also compute 7x (-8) using Booth's Algorithm, (20) conti = Niet oie 4. (a) Explain floating point arithmetic operations in as eae! detail. (10) Se (©) With respect to control unit of a CPU architecture, explain the following terms : ; @ Microprogram. ag (i) Sequence counter, (iii) Microinstruction. (10) SECTION-C Define addressing modes. Explain any five with the help of suitable example, (10) Explain stack based architecture of a CPU with the help of a diagram, (10) () 5707/300/777/1187> e ‘ a; of Questions - 9] [Total Pages : 4 5519 B.Tech. IlIrd Semester Examination COMPUTER ORGANISATION (CSE/IT) Ce Paper : ITD)-3001 e Time : Three Hours] [Maximum Marks : 100 The candidates. shall limit their answers precisely within the answer-book (40 pages) issued to them and no supplementary/ continuation sheet will be issued. Note : Attempt five questions in all. Select one question each from Section A, B, C and D. Q. No. 9 of Section E is compulsory. SECTION-A 1. Simplify the followii Boolean function in sum-of-products— 6 2 What do you un, the SECTION-8 3 @ Draw and ex slain the wi Subeactor circuit, orking of (@®) Explain with example the ee ple the Boy 4 Explain the work lain the working of Micropro rammed conte a SECTION-c 5 (a) Whatis is addressing modes? Explain dressing modes v ovine ts suitable example between RISC and Clee om; pUters, @ Daw and explain the working of General Bite erst 'and by cache memory? Exphia ‘mappin; example, nB CONCEP Used in cache m, ache memory with Mean Wi ee 7th the help of — initialization of DMA contol k dic iagram, explain DMA transi ig) “a a SECTION-E (Compulsory Question) ‘Answer the following ¢ (a). Difeenae between CPU a4 10P. (Why registers are faster than ‘memory? (tn 6 bits instruction format if opcode is of bits how many different operations ican be specified for OmPUIEE saat memory can contain 4096 Wore how many tors we require in adress part of instruction? (What is the difference berween write-through and -yrite-back policy of cache? (©) What is data stream and instruction stream? (How s the performance of computer SYED) measured? (@ Write down the ead and write ‘micro-operations. (4) What are the functions of control ust? (What ae the different phases of an insruco® cycle? @) _instrction is of repister reference 17PE then what is the use of address bits in instruction code? a‘Total No. of Questions ~ 9} Total é (2031) [Total Pages : 3 5707 B.Tech. (IT) New Syllabus [Ird Semester Examination COMPUTER ORGANIZATION Paper — IT-3001 Time : Three Hours] [Maximum Marks : 100 The candidates shall limit their answers precisely within the answer-book (40 pages) issued to them and no supplementary/ continuation sheet will be issued. Note : Attempt one question each from Section A, B, C and D. Section E is compulsory. SECTION-A 1. (a) Differentiate between : (@ SIMD and MIMD. (i) Latch and Flip-Flop. (10) (b) Draw and explain instruction cycle and control functions associated with each phase. Show the execute phase for any one reference memory instruction. fanTg6ib 8 to ator (10) 5707/300/777/1187 g verter.