Shift Register
Qu 1. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 =
1. On the sixth clock pulse, the sequence is ________.
A
Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
.
B.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
C
Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
.
D
Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1
.
Answer: Option C
Qu 2.What is a shift register that will accept a parallel input, or a bidirectional serial load
and internal shift features, called?
A
tristate
.
B.end around
C
universal
.
D
conversion
.
Answer: Option C
Qu 3.On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 =
0. On the fourth clock pulse, the sequence is ________.
A
Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
.
B.Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
C Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
.
D
Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0
.
Answer: Option A
Qu4.A bidirectional 4-bit shift register is storing the nibble 1101. Its input is
HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three
clock pulses, the shift register is storing ________.
A
1101 B.0111
.
C
0001 D.1110
.
Answer: Option B
Qu 5.A bidirectional 4-bit shift register is storing the nibble 1101. Its input is
HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three
clock pulses, the shift register is storing ________.
A
1101 B.0111
.
C
0001 D.1110
.
Answer: Option B
Qu.6 How can parallel data be taken out of a shift register simultaneously?
A
Use the Q output of the first FF.
.
B.Use the Q output of the last FF.
C
Tie all of the Q outputs together.
.
D
Use the Q output of each FF.
.
Answer: Option D
Qu .7What is meant by parallel load of a shift register?
A
All FFs are preset with data.
.
B.Each FF is loaded with data, one at a time.
Answer: Option A
Qu 8.What does the output enable do on the 74395A chip?
A
It determines when data can be loaded.
.
B.It forces all outputs to go HIGH.
C
It forces all outputs to go LOW.
.
D
It activates the three-state buffer.
.
Answer: Option D
Qu 9.To operate correctly, starting a ring shift counter requires:
A
clearing all the flip-flops
.
B.presetting one flip-flop and clearing all others
C
clearing one flip-flop and presetting all others
.
D
presetting all the flip-flops
.
Answer: Option B
Qu 10.In a 6-bit Johnson counter sequence there are a total of how many states, or bit
patterns?
A
2 B.6
.
C
12 D.24
.
Answer: Option C
Qu 11.A modulus-12 ring counter requires a minimum of ________.
A
10 flip-flops
.
B.12 flip-flops
C
6 flip-flops
.
D
2 flip-flops
.
Answer: Option B
Qu 12.Stepper motors have become popular in digital automation systems because
________.
A
of their low cost
.
B.they are driven by sequential digital signals
C
they can be used to provide repetitive mechanical movement
.
D they are driven by sequential digital signals and can be used to provide repetitive
. mechanical movement
Answer: Option D
Qu13.The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel
output shift register with an initial state 01110. After three clock pulses, the register
contains ________.
A
01110 B.00001
.
C
00101 D.00110
.
Answer: Option C
Qu14.Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store
the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first.)
A
1100 B.0011
.
C
0000 D.1111
.
Answer: Option C
Qu15.A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble
0111 is waiting to enter. After four clock pulses, the register contains ________.
A
0000 B.1111
.
C
0111 D.1000
.
Answer: Option C
Qu 16.A sequence of equally spaced timing pulses may be easily generated by which type of
counter circuit?
A ring shift
.
B.clock
C
Johnson
.
Answer: Option A
Qu 17.An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to
achieve a time delay (td) of ________.
A
16 s
.
B. 8 s
C
4 s
.
D
2 s
.
Answer: Option C
Qu 18.The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit
parallel out shift register that is initially clear. What are the Q outputs after four clock
pulses?
A
10011100 B.11000000
.
C
00001100 D.11110000
.
Answer: Option B
Qu 19.If an 8-bit ring counter has an initial state 10111110, what is the state after the
fourth clock pulse?
A
11101011 B.00010111
.
C 11110000 D.00000000
.
Answer: Option D
Qu 20.How would a latch circuit be used in a microprocessor system?
A
as transportation for Intel employees
.
B.for a group of data that is the same
C
as a set of common connections for transfer of data
.
Answer: Option C
Qu 21.A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by
________ position(s) for each clock pulse.
A
right, one
.
B.right, two
C
left, one
.
D
left, three
.
Answer: Option A
Qu 22.How many clock pulses will be required to completely load serially a 5-bit shift
register?
A
2 B.3
.
C
4 D.5
.
Answer: Option D
How is a strobe signal used when serially loading a shift register?
A
to turn the register on and off
.
B.to control the number of clocks
C
to determine which output Qs are used
.
D
to determine the FFs that will be used
.
Answer: Option B
Qu 23.What are the three output conditions of a three-state buffer?
A
HIGH, LOW, float
.
B.1, 0, float
C
both of the above
.
D
neither of the above
.
Answer: Option C
Qu 24.The primary purpose of a three-state buffer is usually:
A
to provide isolation between the input device and the data bus
.
to provide the sink or source current required by any device connected to its output
B.
without loading down the output device
C
temporary data storage
.
D
to control data flow
.
Answer: Option A
Qu 25.What is the difference between a ring shift counter and a Johnson shift counter?
A
There is no difference.
.
B.A ring is faster.
C
The feedback is reversed.
.
D
The Johnson is faster.
.
Answer: Option C
Qu 26.What is a recirculating register?
A
serial out connected to serial in
.
B.all Q outputs connected together
C
a register that can be used over again
.
Answer: Option A
Qu 27When is it important to use a three-state buffer?
A
when two or more outputs are connected to the same input
.
B.when all outputs are normally HIGH
C
when all outputs are normally LOW
.
D
when two or more outputs are connected to two or more inputs
.
Answer: Option A
qu28. How would a latch circuit be used in a microprocessor system?
A
as transportation for Intel employees
.
B.for a group of data that is the same
C
as a set of common connections for transfer of data
.
Answer: Option C
Qu A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by
29. ________ position(s) for each clock pulse.
A
right, one
.
B.right, two
C
left, one
.
D left, three
.
Answer: Option C
Qu30. How many clock pulses will be required to completely load serially a 5-bit shift
register?
A.2 B.3
D
C.4 5
.
Answer: Option D
Qu 31. A bidirectional 4-bit shift register is storing the nibble 1110. Its input
is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After
two clock pulses, the shift register is storing ________.
A.1110 B.0111
D
C.1000 1001
.
Answer: Option D
32. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three
clock pulses, the data outputs are ________.
A
1110 B.0001
.
C
1100 D.1000
.
Answer: Option B
33. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state 11110000. After two clock pulses, the register
contains ________.
A.10111000 B.10110111
D
C.11110000 11111100
.
Answer: Option D
34. By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a
________, ________, and ________-out register.
A
parallel-in, serial, parallel
.
B.serial-in, parallel, serial
C
series-parallel-in, series, parallel
.
D
bidirectional in, parallel, series
.
Answer: Option A
35. What type of register would have a complete binary number shifted in one bit at a time
and have all the stored bits shifted out one at a time?
A
parallel-in, parallel-out
.
B.parallel-in, serial-out
C
serial-in, parallel-out
.
D
serial-in, serial-out
.
Answer & Explanation
Answer: Option C
36. When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the
clock frequency is ________.
A.40 kHz
B.50 kHz
C.400 kHz
D.500 kHz
Answer: Option C
37. Ring shift and Johnson counters are:
A.synchronous counters
B.aynchronous counters
C.true binary counters
D.synchronous and true binary counters
Answer: Option A
38. What is the difference between a shift-right register and a shift-left register?
A.There is no difference.
B.the direction of the shift
Answer: Option B
39. What is a transceiver circuit?
A.a buffer that transfers data from input to output
B.a buffer that transfers data from output to input
C.a buffer that can operate in both directions
Answer: Option C
40. A 74HC195 4-bit parallel access shift register can be used for ________.
A.serial in/serial out operation
B.serial in/parallel out operation
C.parallel in/serial out operation
D.all of the above
Answer: Option D
41. Which type of device may be used to interface a parallel data format with external
equipment's serial format?
A.key matrix
B.UART
C.memory chip
D.series in, parallel out
Answer: Option B
42. What is the function of a buffer circuit?
A.to provide an output that is inverted from that on the input
B.to provide an output that is equal to its input
C.to clean up the input
D.to clean up the output
Answer: Option B
43. What is the preset condition for a ring shift counter?
A.all FFs set to 1
B.all FFs cleared to 0
C.a single 0, the rest 1
D.a single 1, the rest 0
Answer: Option D
44. Which is not characteristic of a shift register?
A.Serial in/parallel in
B.Serial in/parallel out
C.Parallel in/serial out
D.Parallel in/parallel out
Answer: Option A
45. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a
________.
A.divide-by-4 clock pulse
B.sequence generator
C.strobe line
D.multiplexer
Answer: Option C
46. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in
________.
A.12 s
B. 120 s
C.12 ms
D.120 ms
Answer: Option B
47. Another way to connect devices to a shared data bus is to use a ________.
A.circulating gate
B.transceiver
C.bidirectional encoder
D.strobed latch
Answer: Option B
48. To serially shift a nibble (four bits) of data into a shift register, there must be
________.
A.one clock pulse
B.four clock pulses
C.eight clock pulses
D.one clock pulse for each 1 in the data
Answer: Option B
49. Computers operate on data internally in a ________ format.
A.tristate B.universal
C.parallel D.serial
Answer: Option C
50. In a 4-bit Johnson counter sequence there are a total of how many states, or bit
patterns?
A.1 B.2
C.4 D.8
Answer: Option D
Sequential circuit design
Qu 1 In which sequential circuit output depends on present state and inputs.
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer b
Qu 2 In which sequential circuit output depends on only present state.
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer a
Qu 3 how many sequential model are available?
a. Moore model
b. Mealy model
c. both
d. Neither a nor b
Answer c
Qu 4 In which sequential circuit output depends on present state and inputs.
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Qu 5 stata table is a representation of describing the operation of a which circuit.
a. Synchronous circuit
b. Asynchronous circuit
c. In both cases
d. Neither a nor b
Answer a
Qu 6 which sequential circuit has required more delay to generate output ?.
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer b
Qu 7 which sequential circuit has required more no of states to generate output ?
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer a
Qu 8 .In a state diagram the circuit is represented by a --------
a. graph
b. chart
c. block
d. table
Answer a
Qu 9 Which type of state diagram it is?
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer a
Qu 10 Which type of state diagram it is?
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer b
Qu 11 Which type of circuit it is?
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer b
Qu 12 Which type of circuit it is?
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer a
Qu 13 In which sequential circuit output can be unstable.
a. . Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer b
Qu 14 In which sequential circuit required more hardware to generate output .
e. Moore model
f. Mealy model
g. In both cases
h. Neither a nor b
Answer a
Qu 15 which sequential circuit is easy to design .
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer a
Qu 16 when sequence generator move into the unused state and not come back into used
state so this condition known as
a. Race condition
b. Toggle condition
c. Race around condition
d. Lockout condition
Answer d
Qu 17 Those state which are not available in sequence known as
a. Unwanted state
b. Unavailable state
c. Unused state
d. Used state
Answer c
Qu 18 Those state which are available in sequence known as
a. wanted state
b. available state
c. Unused state
d. Used state
Answer d
Qu 19 in which method sequence come back into used state.
a. Without bushing
b. With bushing
c. both
d. neither a nor b
Answer b
Qu 20 Which type of circuit it is?
a. Moore model
b. Mealy model
c. In both cases
d. Neither a nor b
Answer b
Algorithmic State Machines
Qu 1 ASM is a-----------.
a. chart
b. graph
c. table
d. circuit
Answer a
Qu 2 ASM contain how many basic contain.
a. 1
b. 2
c. 3
d. none
Answer c
Qu 3 Which type of boxes are available in ASM.
a. state
b. decision
c. conditional
d. all of them
Answer d
Qu 4 Which type of boxe it is in ASM.
a. state
b. decision
c. conditional
d. all of them
Answer a
Qu 5 Which type of boxe it is in ASM.
a. state
b. decision
c. conditional
d. all of them
Answer a
Qu 6 Which type of boxe it is in ASM.
a. state
b. decision
c. conditional
d. all of them
Answer c
Qu 7 this ASM represent which circuit diagram.
a. mod 4 counter
b. 2 bit up counter
c. 2 bit down counter
d. Mod 6 counter
Answer a
Qu 8 Which type of method it is .
First level
(Multiplexers)
Second level
(Register)
MUX
1 MUX Output FF
1 Third level
(Decoder)
Select
MUX
Inputs Output
Select
MUX FF
2 MUX Output 2
Holds the present
binary state
Fig. Block schematic for a 3-level scheme for multiplexer design
a. Multiplexer controller method
b. Flip flop controller method
c. Decoder controller method
d. None of above
Answer a
Qu 9 which chart depends on clock?
a. ASM chart
b. Flow chart
c. Both
d. None of above
Answer a
Qu10 this ASM represent which circuit diagram.
00
01
0 1
M
10
0 1
M
e. mod 4 counter
f. 2 bit up counter 11
M
g. 2 bit up/down counter
h. Mod 6 counter
Answer b
