Performance Optimization of ZnO based Thin Film

Transistor for Future Generation Display Technology

Abhishek Kumar Singh, Vivek Vijay Kharche, P. Chakrabarti,
Student Member, IEEE, Student Member, IEEE, Senior Member, IEEE,
Dept. of Electronics Engineering, Dept. of Electronics Engineering, Dept. of Electronics Engineering,
Indian Institute of Technology Indian Institute of Technology Indian Institute of Technology
(Banaras Hindu University), (Banaras Hindu University), (Banaras Hindu University),
Varanasi – 221005, India Varanasi – 221005, India Varanasi – 221005, India
aksingh.rs.ece16@iitbhu.ac.in kvvijay.ece16@iitbhu.ac.in pchakrabarti.ece@iitbhu.ac.in

Abstract— Zinc oxide based thin-film transistors (TFT) built like high on-off ratio, less leakage current and low power
with an Al2O3 insulator layer have been analyzed on Silvaco consumption. However, cost of this material is a major cause
ATLASTM 2D simulator in order to optimize their performance of concern for commercial deployment of IGZO based TFTs
for application in display systems. We have optimized the in backplane display technologies. From this view point ZnO
geometry of the structure by varying the oxide thickness and based TFTs need to be explored properly to resolve the cost
semiconductor channel for achieving high performance switching
issue. Even though researchers have reported ZnO based TFTs
application in display technology. The study revealed that the
device can be successfully optimized to achieve a very high value many years ago, a high performance TFT involving low
of on-off ratio of ~2.78x108 to provide a better driving capability fabrication cost is yet to be developed for possible use in
and yet maintaining a low sub-threshold voltage of 0.55 V/decade backplane display technology. Table I lists the performance
ensuring high speed of operation. The high performance ZnO ratings of various TFTs reported till date using different
based device proposed to be built on Al2O3 insulator will make it materials. It is clearly seen that still researchers are struggling
cost-effective for large display systems. hard to achieve an on off ratio exceeding 108 with a lower
value of sub-threshold swing (~0.5 V/dec). Therefore, it is
Keywords—Optimization, Zinc oxide (ZnO), Thin Film important to optimize the device geometry and various
Transistor (TFT), Display, OLED Driver
parameters of ZnO based TFTs to meet the requirements. In
I. INTRODUCTION this paper we have made an attempt to simulate and optimize
the performance of ZnO based TFTs for possible use in
Thin film transistors have become the backbone of thin film backplane technology.
electronics. Among various applications of oxide TFTs, the
most promising one is their deployment as the pixel switching II. DEVICE STRUCTURE AND SIMULATION
elements on flat panel displays or LED displays. ZnO is a low
cost material which is available in high abundance. It has been
extensively used for making a variety of electronic and
optoelectronic components such as thin film transistors
(TFTs), UV photodetectors, sensors and LED etc. [1]-[3].
ZnO TFTs are more attractive for applications in display
technology as compared to their organic counterparts in view
of in view of higher mobility and lower cost. An extensive
study of the current state-of-the-art of thin-film transistors
reveals that the researchers are striving for achieving even
higher value of carrier mobility so that the electrical properties
of the devices improve. In fact many researchers have
demonstrated reasonable field effect mobility 1-10 cm2/V-sec
for ZnO based TFTs [4]. TFTs having electron mobility more
than 50 cm2/V-sec has been demonstrated by the researchers
[5]. Materials used for making TFT display backplanes
include low-temperature polycrystalline silicon (LTPS),
amorphous silicon (a-Si) and indium gallium zinc oxide
(IGZO). Among these materials IGZO has been most widely Fig. 1. Device structure of ZnO based bottom gate
used in backplane technology [6] due to several advantages Thin Film Transistor

978-1-5386-4318-1/17/$31.00 ©2017 IEEE

 TABLE I. COMPARISON OF VARIOUS TFT PARAMETERS

Sub-threshold Field effect

Off current Threshold Thickness(Oxide/S.
Sr.No. On-Off Ratio swing mobility (cm2 W/L ratio Reference Deposition Technology
(A) voltage(V) C)(nm/nm)
(V/decade) /V-Sec)
I. 2.5×10-7 ~102 1.3 --- 11 50/200 4/1 [7] Sol gel
II. 10-10 ~105 ~15 --- 0.8 - 2.3 150/100 20/1 [8] RF Sputtering
III. 3×10-8 3×106 1.7 --- --- 170/150 3.3 [9] RF Sputtering
IV. 1.3×10-9 2×105 21 1.24 19-21 220/100 --- [10] RF Magnetron Sputtering
Atomic Layer
V. 10-7 -10-9 107 2.6 0.5 12.2 200/20 10 [11]
Deposition
-12 7
VI. 10 2.7×10 --- --- 5.2 50/40 &100/40 50/20 [12] RF Sputtering
Atomic Layer
VII. ~10-11 107 10-20 --- 0.3-2.5 220/100 10/1 [13]
Deposition

From previous research reports it is understood that a bottom

gate TFT structure is superior to a top gate structure in terms TABLE II. MATERIAL PARAMETERS OF ZNO FOR 2D DEVICE
SIMULATION [4][5]
of performance and electrical characteristics [14]. The
structure under consideration has a bottom gate configuration
Material constant for ZnO Values
as shown in Fig.1. In this work, the Bottom gate structure has
Band gap EG (300K) 3.37 eV
been simulated using ATLASTM tool from Silvaco
Effective mass of electron 0.19mo
International, Singapore. Various parameters pertaining to
Effective mass of hole 1.21mo
polycrystalline ZnO have been taken from [4]-[5] and are
Dielectric constant 8.5
listed in Table II. In the simulation we have taken two
Mobility 60 cm2/V s
different dielectric material e.g., SiO2 with a low dielectric
Electron affinity 4.3 eV
constant of 3.9 and other Al2O3 with a high dielectric constant Effective density of state in the
of 9.1. The thickness of gate insulator Al2O3 and SiO2 is 2.9483×1024/m3
conduction band (NC)
varied as 50 nm, 100 nm, 150 nm for optimizing the best Effective density of state in the valence
1.1364×1025/m3
possible dimension of structure used for TFT. band (NV )
The objective of the simulation was focused on SRH life time for electrons 4.1955×10−6 s
achieving desired performance of TFT for display technology. SRH life time for holes 6.5781×10−6 s
Aluminum is a low cost material available in abundance in Trap density 1023 m3
nature and hence aluminum is used for gate, source and drain
contacts. For 2D simulation SRH recombination, drift
diffusion, impact ionization, and mobility models are used.
Fermi Dirac Distribution is mainly used to determine the III. RESULT AND DISCUSSION
carrier concentration. All calculations are performed at room The on-off ratio, subthreshold swing and mobility are the
temperature (300 K). The drain current in saturation region prime parameters for determining the performance of TFT.
(VDS > VGS -VT) is given as [15] High on-off ratio and mobility are desirable for better driving
capability. Low sub-threshold swing provides low power
consumption and high-speed operation [16].
= ( − ) (1) Fig. 2 and 4 shows transfer (ID Ѹ VG) and output characteristics
(ID Ѹ VD) of simulated bottom-gate ZnO TFT respectively.
Where is mobility of electrons in ZnO, is oxide Channel length (L) and width (W) of the ZnO TFT were 10 μm
capacitance per unit area, W is width of channel, L is length is and 60 μm respectively.
channel. Field effect mobility is the important parameter for .
TFTs. The following equation is used for calculation of field-
effect mobility

= (2)

where is field effect mobility, is the transconductance.

 performance of TFT. It has been observed that the drain
current in case of Al2O3 oxide based TFT is more than that in
case of SiO2 oxide based TFT. On current in case of Al2O3
oxide based TFT is greater than that in the case of a SiO2
oxide based TFT. This is because drain current is directly
proportional to the dielectric constant of oxide and inversely
proportional to the thickness of oxide. For the thickness of 50
nm of Al2O3, the drain current (ID) obtained is 4.3×10-12 A at
gate voltage (VG ) = -3.2 V and VD = 12 V (off state). Also ID =
1.2 mA at gate voltage VG =1.4 V and VD = 12 V (on state). An
on-off current ratio is 2.7×108 can thus be achieved for this
structure. For SiO2 oxide layer, ID = 1.5 × 10-10 A at VG = -4.6
V and VD = 12 V (off state) was obtained and ID = 0.58 mA at
VG = 2.2 V and VD = 12 V (on state) was obtained to provide
an on-off current ratio of 3.9 × 106. In table III, off and on (i.e.
(a)
VG-off and VG-on) voltages are considered different for different
oxide thickness as well as ZnO thickness. The same analysis
was done by changing the thickness of oxide for Al2O3 and
SiO2 to 80 nm (Fig. 2) and 100 nm (Fig. 3) respectively. The
transfer characteristics (ID-VG) have been plotted on
logarithmic scale for the optimized structure. Important
parameters obtained from the model are listed in Table III.

(b)

Fig. 3. log (ID) vs. VG at 100 nm thickness of ZnO and Oxide (Al2O3)
thickness of 50 nm.

The simulation results show that for the optimized structure

the on-off current ratio is 2.7× 108. For the optimized structure
the field effect mobility has been obtained as 6.05 cm2/Vs. We
have also calculated on-off current ratio, sub threshold swing
(c) for different thickness of oxide layer and ZnO layer
considering both Al2O3 and SiO2 as oxide layer. The variations
Fig. 2 Transfer characteristics (IDS − VG) of (a) 50nm (b) 80nm (c) 100nm
oxide thickness
in drain current with respect to oxide and semiconductor
thickness have been plotted in Fig. 4(a)-(c). A close look at
Transfer characteristics Fig. 2 (a)-(c) show the variation of these variations reveals that by using Al2O3 instead of SiO2
drain current versus gate voltage at fixed oxide thickness of 80 one can achieve a better driving capability. For Al2O3 Oxide
nm with SiO2 and Al2O3 and varying the thickness of thickness of 50 nm and ZnO layer thickness = 100 nm, the
semiconductor layer of 100 nm, 150 nm, 200 nm respectively. drain current saturates at VD = 4 V onwards (VG = 4 V) but for
These variations have been studied for optimizing the SiO2, it saturates at around 5 V of VD (VG = 4 V).
 TABLE III. DEVICE PARAMETERS OF TFT WITH DIFFERENT
THICKNESS

SiO2 Al2O3
tox ZnO S.S Ioff S.S Ioff
Ion/ Ioff Ion/ Ioff
(nm) (nm) (mV/dec) (10-10 A) (mV/dec) (10-12 A)
100 586 3.9×106 1.50 554 2.7×108 4.37
150 595 1.7×106 3.45 563 7.8×106 149
50
200 603 9.7×105 4.85 571 3.7×106 301

100 602 1.4×106 2.82 572 1.9×107 42.9

150 612 8.6×105 4.74 581 3.3×106 240
80
200 621 6.8×105 5.98 589 2×106 387

100 609 1.1×106 3.38 580 7.6×106 90.6 (c)

150 621 6.4×105 5.30 590 2.3×106 285
150
200 629 5.5×105 6.18 699 1.5×106 426 Fig. 4. Output (IDS − VD) characteristic of the ZnO TFT oxide for thickness
values of (a) 50 nm (b) 80 nm (c) 100 nm

IV. CONCLUSION
Simulation of a bottom gate ZnO based TFT with Al2O3/SiO2
as oxide layer have been reported. The simulation has been
carried out using Silvaco ATLASTM 2D TCAD tool. The
simulation results of ZnO based TFT suggests that use of
oxide layer of Al2O3 instead of SiO2 of 50 nm thickness with
ZnO thickness of 100 nm provides high on-off current ratio of
2.7 ×108, sub threshold swing of 0.55 V/dec, μFE of 6.05
cm2/Vs. With decrease in ZnO layer thickness for constant
oxide thickness, sub threshold swing and on-off current ratio
can be improved further. The fabrication of the structure on the
basis of the above design guidelines is currently underway. The
ZnO based TFT with high on-off ratio is expected to turn out as
a low-cost alternative for more expensive devices used for
backplane display technology.
(a)

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