VHDL
Douglas L. Perry
Third Edition
McGraw-Hill
New York • San Francisco • Washington, D.C. • Auckland
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CONTENTS
Preface xv
Chapter 1 Introduction to VHDL
VHSIC Program 2
VHDL as a Standard 2
Learning VHDL 3
VHDL Terms 3
Traditional Design Methods 4
Traditional Schematics 6
Symbols Versus Entities 7
Schematics Versus Architectures 7
Component Instantiation 8
Behavioral Descriptions 9
Concurrent Signal Assignment 10
Event Scheduling 11
Statement Concurrency 11
Sequential Behavior 12
Process Statements 12
Process Declarative Region 13
Process Statement Part 13
Process Execution 13
Sequential Statements 14
Architecture Selection 14
Configuration Statements 15
Power of Configurations 15
Chapter 2 Behavioral M o d e l i n g 17
Introduction to Behavioral Modeling 18
Transport Versus Inertial Delay 22
Inertial Delay 22
Transport Delay 23
Inertial Delay Model 24
Transport Delay Model 25
Simulation Deltas 25
D ri vers 29
Driver Creation 29
Bad Multiple Driver Model 30
Contents
Generics 31
Block Statements 33
Guarded Blocks 37
Chapter 3 Sequential Processing 41
Process Statement 42
Sensitivity List 42
Process Example 42
Signal Assignment Versus variable Assignment 44
Incorrect Mux Example 45
Correct Mux Example 47
Sequential Statements 48
IF Statements 49
CASE Statements 50
LOOP Statements 52
NEXT Statement 55
EXIT Statement 56
ASSERT Statement 58
Assertion BNF 59
WAIT Statements 61
WAIT O N Signal 64
WAIT UNTIL Expression 64
WAIT FOR time_expression 64
Multiple WAIT Conditions 65
WAIT Time-Out 66
Sensitivity List Versus WAIT Statement 68
Concurrent Assignment Problem 69
Passive Processes 72
Chapter 4 D a t a Types 75
Object Types 76
Signal 76
Variables 78
Constants 79
Data Types 80
Scalar Types 81
Composite Types 88
Incomplete Types 100
File Types 104
File Type Caveats 107
Subtypes 107
Contents IX
Chapter 5 Subprograms and Packages 111
Subprograms 112
Function 112
Conversion Functions 115
Resolution Functions 121
Procedures 135
Packages 137
Package Declaration 138
Deferred Constants 138
Subprogram Declaration 139
Package Body 140
Chapter 6 Predefined Attributes 145
Value Kind Attributes 146
Value Type Attributes 146
Value Array Attributes 149
Value Block Attributes 151
Function Kind Attributes 153
Function Type Attributes 153
Function Array Attributes 156
Function Signal Attributes 158
Attributes EVENT a n d LAST_VALUE 159
Attribute LAST_EVENT 160
Attribute ACTIVE and LAST_ACTIVE 162
Signal Kind Attributes 162
Attribute DELAYED 163
Attribute STABLE 166
Attribute QUIET 168
Attribute TRANSACTION 170
Type Kind Attributes 171
Range Kind Attributes 172
Chapter 7 Configurations 175
Default Configurations 176
Component Configurations 178
Lower-Level Configurations 181
Entity-Architecture Pair Configuration 182
Port Maps 183
Mapping Library Entities 185
Generics in Configurations 189
Contents
Generic Value Specification in Architecture 192
Generic Specifications in Configurations 195
Board-Socket-Chip Analogy 200
Block Configurations 204
Architecture Configurations 206
Chapter 8 Advanced Topics 211
Overloading 212
Subprogram Overloading 212
Overloading Operators 217
Aliases 221
Qualified Expressions 222
User-Defined Attributes 224
Generate Statements 226
Irregulär Generate Statement 228
TextIO 231
Chapter 9 Synthesis 237
Register Transfer Level Description 238
Constraints 243
Timing Constraints 244
Clock Constraints 244
Attributes 245
Load 246
Drive 246
Arrival Time 246
Technology Libraries 247
Synthesis 249
Translation 249
Boolean Optimization 250
Flattening 251
Factoring 252
Mapping to Gates 253
Chapter 10 VHDL Synthesis 257
Simple Gate — Concurrent Assignment 258
IF Control Flow Statements 259
Case Control Flow Statements 262
Simple Sequential Statements 263
Asynchronous Reset 266
Contents XI
Asynchronous Preset and Clear 267
More Complex Sequentia!
Statements 269
Four-Bit Shifter 270
State Machine Example 273
Chapter 11 High Level Design Flow 281
RTL Simulation 283
VHDL Synthesis 285
Functional Gate Level Verification 291
Place and Route 292
Post Layout Urning Simulation 294
Static Urning 295
Chapter 12 Top-Level System Design 297
CPU Design 298
Top-Level System Operation 298
Instructions 299
Sample Instruction Representation 300
CPU Top-Level Design 301
Block Copy Operation 307
Chapter 13 CPU: Synthesis Description 311
ALU 314
Comp 317
Control 319
Reg 329
Regarray 330
Shift 332
Trireg 334
Chapter 14 CPU: RTL Simulation 337
Testbenches 338
Kinds of Testbenches 339
Stimulus Only 341
Füll Testbench 345
Simulator Specific 348
Hybrid Testbenches 350
Fast Testbench 353
CPU Simulation 357
Contents
Chapter 15 CPU Design: Synthesis Results 365
Control 368
Alu 370
Comp 372
Reg 374
Regarray 376
Shirt 378
Tri reg 380
Chapter 16 Place and Route 385
Place and Route Process 386
Placing and Routing the Device 389
Setting up a project 389
Reading in the Netlist and Performing Place and
Route 392
Analyzing the Results 392
Chapter 1 7 CPU: VITAL Simulation 395
VITAL Library 397
VITAL Simulation Process Overview 398
VITAL Implementation 398
Simple VITAL Model 399
VITAL Architecture 402
Wire Delay Section 402
Flip-Flop Example 404
SDF File 408
VITAL Simulation 410
Back-Annotated Simulation 413
Appendix A Standard Logic Package 415
Appendix B VHDL Reference Tables 437
Appendix C Reading VHDL BNF 447
Appendix D VHDL93 Updates 451
Alias 451
Attribute Changes 452
Bit String Literal 454
DELAY_LENGTH Subtype 454
Direct Instantiation 454
Extended Identifiers 455
File Operations 456
Foreign Interface 457
Generate Statement Changes 458
Globally Static Assignment 458
Groups 459
Incremental Binding 460
Postponed Process 461
Pure and Impure Functions 462
Pulse Reject 462
Report Statement 463
Shared Variables 463
Shift Operators 465
SLL—shift left logical 465
SRL—shift right logical 465
SLA—shift left arithmetic 465
SRA—shift right arithmetic 465
R O L — r o t a t e left 466
ROR — rotate right 466
Syntax Consistency 466
Unaffected 468
XNOR Operator 468
