HF920

900V, Fixed-Frequency, Offline Regulator

w/ Ultra-Low Standby Power Consumption
The Future of Analog IC Technology

DESCRIPTION FEATURES
The HF920 is a flyback regulator with a  Monolithic 900V/15Ω MOSFET and High-
monolithic, 900V MOSFET. The HF920 provides Voltage Current Source
excellent power regulation in AC/DC  Fixed Switching Frequency, Programmable
applications that require high reliability, such as up to 150kHz
smart meters, large appliances, industrial  Current-Mode Control Scheme
controls, and products powered by poor AC grids.  Frequency Jittering
The HF920 requires a minimal number of  Low Standby Power Consumption via Active
external components. Burst Mode
The HF920 uses peak-current-mode control to  <30mW No-Load Consumption
provide excellent transient response and easy  Frequency Doubling Operation Mode
loop compensation. When the output power falls  Internal Leading-Edge Blanking (LEB)
below a given level, the regulator enters burst  Built-In Soft-Start (SS) Function
mode. The IC consumption is also specially  Internal Slope Compensation
optimized. As a result, the HF920 achieves very  External Input PRO Pin Protection with
low power consumption during standby Hysteresis and Auto-Restart Recovery
conditions.  Over-Temperature Protection (OTP)
MPS’s proprietary, 900V, monolithic process  VCC Under-Voltage Lockout (UVLO) with
enables an over-temperature protection (OTP) Hysteresis
that is on the same silicon as the 900V power  Over-Voltage Protection (OVP) on VCC
MOSFET, offering the most precise thermal  Time-Based Overload Protection (OLP)
protection. The HF920 also offers a full suite of  Short-Circuit Protection (SCP)
protection features such as VCC under-voltage  Available in SOIC8-7A and SOIC14-11
lockout (UVLO), overload protection (OLP), Packages
over-voltage protection (OVP), and short-circuit
protection (SCP). APPLICATIONS
The HF920 is designed to minimize  E-Meters
electromagnetic interference for power line  Industrial Controls
communications (PLC) in home and building  Large Appliances
automation applications. The operating All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance. “MPS”
frequency is programmed externally with a single and “The Future of Analog IC Technology” are registered trademarks of Monolithic
resistor, so the power supply’s radiated energy Power Systems, Inc.

can be designed to block interference to the PLC.

Table 1: Maximum Output Power
In addition to the programmable frequency, the
HF920 employs frequency jittering that reduces PMAX (W)
Package
the noise level and EMI filter cost greatly. 85Vac~420Vac 230Vac±15%
SOIC8-7A 6.5 9.5
Frequency-doubling mode operation can be SOIC14-11 7 10
enabled through a simple external set-up. With NOTES:
this special operation mode, the switching  The maximum output power is limited by junction temperature.
 Test is done under TA = 50°C. The test board is placed into a
frequency is doubled when the converter runs box about 20cm*15cm*10cm.
into an over-power condition. In this way, the  To reduce VDS, the turns ratio is set to 5.
converter is able to handle up to a 50% decrease  Single output, VOUT = 12.5V.
of the transformer inductance caused by external  GND of the SOIC8-7A package is connected to a 3cm2 copper
area with exposed copper strips. GND of the SOIC14-11
magnetizing interference. package is connected to a 2.5cm2 copper area.
 Working condition under minimum input voltage is set to BCM.

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 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR

TYPICAL APPLICATION

85- +
+
420Vac

VCC D

PRO

FB S

FSET GND

HF920

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ORDERING INFORMATION
Part Number Package Top Marking
HF920GSE* SOIC8-7A See Below
HF920GS** SOIC14-11 See Below
* For Tape & Reel, add suffix –Z (e.g.: HF920GSE–Z)
** For Tape & Reel, add suffix –Z (e.g.: HF920GS–Z)

TOP MARKING (HF920GSE)

HF920: Part number

LLLLLLLL: Lot number
MPS: MPS prefix
Y: Year code
WW: Week code

TOP MARKING (HF920GS)

MPS: MPS prefix

YY: Year code
WW: Week code
HF920: Part number
LLLLLLLLL: Lot number

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PACKAGE REFERENCE
TOP VIEW TOP VIEW

SOIC8-7A SOIC14-11

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC

D .................................................... -0.3V to 900V SOIC8-7A ............................... 96 ..... 45 ..... °C/W
VCC ................................................. -0.3V to 30V SOIC14-11 ............................. 70 ..... 35 ..... °C/W
All other pins .................................. -0.3V to 6.5V NOTES:
Continuous power dissipation (TA = +25°C) (2) 1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
SOIC8-7A .................................................... 1.3W maximum junction temperature TJ (MAX), the junction-to-
SOIC14-11 ................................................ 1.78W ambient thermal resistance θJA, and the ambient temperature
Junction temperature ................................ 150°C TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
Lead temperature...................................... 260°C (MAX)-TA)/θJA. Exceeding the maximum allowable power
Storage temperature .................-60°C to +150°C dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
ESD capability human body model ........... 2.0kV shutdown circuitry protects the device from permanent
ESD capability charged device model ....... 2.0kV damage.
3) The device is not guaranteed to function outside of its operating
Recommended Operation Conditions (3) conditions.
4) Measured on JESD51-7, 4-layer PCB.
VCC to GND...................................... 10V to 24V
Operating junction temp. (TJ) ....-40°C to +125°C

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 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR

ELECTRICAL CHARACTERISTICS
VCC = 12V, TJ = -40°C to 125°C, min and max values are guaranteed by characterization, typical
values are tested under 25°C, unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Unit
Start-Up Current Source and Internal MOSFET (D Pin)
Supply current from drain ICharge VCC = VCCH - 0.1V, VD = 400V 1 2 3 mA
Leakage current from drain ILeak VD = 400V, VGS = 0V, TJ = 25°C 1 μA
VD = 400V, VGS = 0V 10
Breakdown voltage V(BR)DSS 900 V
VCC = 10V, TJ = 25°C 15 18 Ω
On-state resistance RDS(ON)
ID = 100mA TJ = 125°C 25 29 Ω
Supply Voltage Management (VCC Pin)
VCC upper level at which
VCCH 12 13 14 V
the IC switch turns on
VCC lower level at which
VCCL 8.4 9 9.6 V
the IC switch turns off
VCC hysteresis VCC_HYS 3 4 5 V
VCC OVP level VOVP 24.4 25.5 26.5 V
VCC OVP delay time tOVP 70 μs
VCC recharge level after
VCCR 4.8 5.5 6.2 V
protections
Quiescent current during
IPro VCC = VCCL 300 μA
protections
Quiescent current IQ VCC = VCCH - 0.1V 200 300 μA
VCC =13V, fS = 100kHz 510 610 μA
Operation current ICC
VCC = 13V, FB = 0V 300 400 μA
Feedback Management (FB Pin)
Internal pull-up resistor RFB Normal operating 39 kΩ
Internal pull-up voltage VUP 4.1 4.4 4.7 V
FB to current-set-point
Kdiv 3.4 3.7
division ratio
Internal soft-start time tSS 6.7 ms
FB decreasing level at
which the regulator enters VBURL 0.4 0.5 0.6 V
burst mode
FB increasing level at
which the regulator leaves VBURH 0.6 0.7 0.8 V
burst mode
Overload set point VOLP 3.3 3.65 4 V
Overload counter 8192
Threshold for frequency to
VFR CFSET = 1nF 2.85 3 3.15 V
recover
Frequency doubling entry/
CFSET = 1nF 31
recovery counter
Frequency Setting (FSET Pin)
FSET reference voltage VFSET 1.18 1.25 1.32 V
Frequency spectrum
jittering range, in RJittering ±3.5 %
percentage of Fs
RFSET = 200kΩ 43 49 55
Typical operating
fS RFSET = 200kΩ, CFSET = 1nF, kHz
frequency 87 99 111
VFB = 3.5V
Maximum switching duty Dmax 79 83 87 %

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ELECTRICAL CHARACTERISTICS (continued)

VCC = 12V, TJ = -40°C to 125°C, min and max values are guaranteed by characterization, typical
values are tested under 25°C, unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Unit
Current Sensing Management (S Pin)
Leading-edge blanking for
tLEB1 385 ns
current sensor
Leading-edge blanking for
tLEB2 350 ns
SCP
Maximum current set point VCSL 0.91 0.97 1.02 V
Short-circuit protection set
VSCP 1.43 1.5 1.57 V
point
Slope compensation ramp SRamp RFSET = 200kΩ 21 mV/μs
Protection Management (PRO Pin)
Protection voltage VPRO 2.92 3.1 3.32 V
Protection hysteresis VPRO-Hys 0.2 V
Thermal Shutdown
Thermal shutdown
150 °C
threshold (5)
Thermal shutdown recovery
30 °C
hysteresis (5)
NOTE:
5) This parameter is guaranteed by design.

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 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR

PIN FUNCTIONS
Pin #
Name Description
SOIC8-7A SOIC14-11
IC power supply. Connect an electrolytic capacitor and a small ceramic
1 3 VCC
decoupling capacitor to VCC.
Switching frequency setting. Connect a resistor from FSET to GND to set
the switching frequency, which can be up to 150kHz. FSET is also used for
2 4 FSET
enabling frequency-doubling operation mode by placing a typical 1nF
capacitor in parallel with the frequency-setting resistor.
External protection. When pulled up, PRO shuts down the IC with a
3 5 PRO
hysteresis.
Feedback. The output voltage is regulated according to the feedback signal
4 6 FB
on FB. OLP detection and burst mode control are also performed on FB.
5 1, 2, 7, 8 GND IC ground.
Source of the internal MOSFET. S is the input for the primary current-sense
6 9 S
signal.
- 13 NC No connection.
Drain of the internal MOSFET. D is the input for the start-up high voltage
8 14 D
current source.

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 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR

TYPICAL CHARACTERISTICS
Icharge @ VD = 400V vs. Temperature V(BR)DSS @ ILeak = 100µA vs.
Temperature
2.5 1160

1140
2
1120
ICHARGE (mA)

V(BR)DSS (V)
1.5 1100

1080
1
1060
0.5 1040

0 1020
-50 0 50 100 -40 10 60 110
Temperature (°C) Temperature (Ԩ)

RDS(ON) vs. Temperature VCSL vs. Temperature

30 1

25 0.99

20 0.98
RDS(ON) (Ω)

VCSL (V)

15 0.97

10 0.96

5 0.95

0 0.94
-50 0 50 100 -50 0 50 100
Temperature (°C) Temperature (°C)

Kdiv vs. Temperature VOLP vs. Temperature

3.5 3.7

3.45 3.65
KDIV (V)

VOLP (V)

3.4 3.6

3.35 3.55

3.3 3.5
-50 0 50 100 -50 0 50 100
Temperature (°C) Temperature (°C)

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TYPICAL CHARACTERISTICS (continued)

fS vs. Temperature tLEB1 vs. Temperature

100 500
490
90 double fs 480
470
80

tLEB1 (ns)
460
fS (kHz)

70 450
440
60 430
420
50
410
40 400
-50 0 50 100 -50 0 50 100
Temperature (°C) Temperature (°C)

tLEB2 vs. Temperature VPRO vs. Temperature

400 3.2
390
380 3.18
370
tLEB2 (ns)

360 3.16
VPRO (V)

350
340 3.14
330
320 3.12
310
300 3.1
-50 0 50 100 -50 0 50 100
Temperature (°C) Temperature (°C)

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TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested with the evaluation board in the Design Example section.
VIN = 230V, VOUT1 = 13.5V, IOUT1 = 300mA, VOUT2 = 8V, IOUT2 = 50mA, VOUT3 = 8V, IOUT3 = 50mA, TA =
25°C, unless otherwise noted.
Efficiency No-Load Consumption (6)
85 30
80 25
75
20
Efficienyc (%)

PIN (mW)
70
15
65
10
60
5
55 115VAC input
230VAC input 0
50
0 0.25 0.5 0.75 1 85 115 145 175 205 235 265
Load
VIN (VAC)
Power On Power Off

CH1: VD CH1: VD
200V/div. 200V/div.
CH2: VCC CH2: VCC
20V/div. 20V/div.
CH3: FB CH3: FB
5V/div. 5V/div.

CH4: VOUT1 CH4: VOUT1

10V/div. 10V/div.
40ms/div. 40ms/div.
Normal Operation Short-Circuit Entry

CH1: VD CH1: VD
200V/div. 200V/div.

CH2: VCC CH2: VCC

20V/div. 20V/div.
CH3: FB CH3: FB
5V/div. 5V/div.
CH4: VOUT1 CH4: VOUT1
10V/div. 10V/div.

10µs/div. 400ms/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested with the evaluation board in the Design Example section.
VIN = 230V, VOUT1 = 13.5V, IOUT1 = 300mA, VOUT2 = 8V, IOUT2 = 50mA, VOUT3 = 8V, IOUT3 = 50mA, TA =
25°C, unless otherwise noted.
Short-Circuit Recovery Short-Circuit Power On

CH1: VD CH1: VD
200V/div. 200V/div.

CH2: VCC CH2: VCC

20V/div. 20V/div.
CH3: FB CH3: FB
5V/div. 5V/div.
CH4: VOUT1 CH4: VOUT1
10V/div. 10V/div.

400ms/div. 400ms/div.

OLP Entry OLP Recovery

CH1: VD CH1: VD
200V/div. 200V/div.

CH2: VCC CH2: VCC

20V/div. 20V/div.
CH3: FB CH3: FB
5V/div. 5V/div.
CH4: VOUT1 CH4: VOUT1
10V/div. 10V/div.

1s/div. 1s/div.

OLP Power On OVP Entry

CH1: VD CH1: VD
200V/div. 200V/div.

CH2: VCC CH2: VCC

20V/div. 20V/div.
CH3: FB CH3: FB
5V/div. 5V/div.
CH4: VOUT1 CH4: VOUT1
10V/div. 10V/div.

1s/div. 1s/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested with the evaluation board in the Design Example section.
VIN = 230V, VOUT1 = 13.5V, IOUT1 = 300mA, VOUT2 = 8V, IOUT2 = 50mA, VOUT3 = 8V, IOUT3 = 50mA, TA =
25°C, unless otherwise noted.
OVP Recovery OVP Power On

CH1: VD CH1: VD
200V/div. 200V/div.

CH2: VCC CH2: VCC

20V/div. 20V/div.
CH3: FB CH3: FB
5V/div. 5V/div.
CH4: VOUT1 CH4: VOUT1
10V/div. 10V/div.

1s/div. 1s/div.
NOTE:
6) The no load consumption is tested with OUT2 and OUT3 open.

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 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR

BLOCK DIAGRAM

Power
Management

OVP

Frequency Driving Signal

Control Management

OTP
Fault Signal
OLP Management

Burst Mode
Control

SCP

Peak Current Current

Conversion Comparator

Figure 1: Internal Functional Block Diagram

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OPERATION The lower VCC under-voltage lockout (UVLO)

threshold decreases from VCCL to VCCR when a
The HF920 incorporates all of the necessary
fault condition (such as SCP, OLP, OVP, or OTP)
features required by a reliable switch-mode
occurs.
power supply. The proprietary, 900V, monolithic
integration enables a highly integrated power Soft Start (SS)
supply solution. The HF920 uses burst-mode The HF920 implements an internal soft-start
operation to minimize the stand-by power circuit to reduce stress on the primary-side
consumption at light load. Protection features MOSFET and secondary diode and to smoothly
such as auto-recovery for overload protection establish the output voltage during start-up. The
(OLP), short-circuit protection (SCP), over- internal soft-start circuit increases the threshold
voltage protection (OVP), and thermal shutdown of the peak-current comparator gradually from
for over-temperature protection (OTP) contribute the minimal level until the feedback control loop
to a safer converter design with minimal external takes over. The maximum soft-start time is tSS.
components. Within the soft-start duration, the switching
Pulse-Width Modulation (PWM) Operation frequency is also increased progressively from
20 - 100% of the programmed switching
The HF920 employs peak-current-mode control.
frequency.
On the secondary side, the output voltage is
regulated by the compensation network, and the Switching Frequency
compensation output is fed back to the primary The switching frequency can be set by a resistor
side as an input signal to FB through an optical between FSET and GND. The oscillator
coupler. The FB voltage (VFB) is used to control frequency can be calculated with Equation (1):
the peak current on the primary side winding of
1 Hz (1)
the flyback transformer based on the current fS 
R
sensing on S. The integrated 900V MOSFET 523  10 9
 123.4  10 12
 FSET
VFST
turns on at the beginning of each cycle based on
the internal oscillator and turns off based on the Where VFSET is the internal reference voltage on
peak current control. FSET.
Start-Up and VCC UVLO Frequency Jittering
Initially, the IC is driven by the internal current
The HF920 provides a frequency jittering
source drawn from the high-voltage D pin. The
function, which simplifies the input EMI filter
IC begins switching, and the internal high-
design and decreases system cost. The HF920
voltage current source turns off once the VCC
has optimized frequency jittering with a ±3.5%
voltage reaches its upper threshold (VCCH). Then,
frequency deviation range and a 256TS carrier
the IC supply is taken over by the auxiliary
cycle that improves EMI effectively by spreading
winding of the transformer. Whenever VCC falls
the energy dissipation over the frequency range.
below its lower threshold (VCCL), the regulator
stops switching, and the internal high-voltage Frequency Doubling
current source turns on again (see Figure 2). Connect a 1nF capacitor to FSET to enable the
VCC Auxiliary Winding Takes Charge frequency doubling. The switching frequency is
VCCH doubled when the converter enters an over-
VCCL power condition (FB voltage rises to VOLP). This
way, the converter is able to handle up to a 50%
decrease of the transformer inductance caused
Driver
Switching Pluses by external magnetizing interference.

Figure 2: VCC Start-Up

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Peak Current Limit Over-Voltage Protection (OVP)

The primary peak current is sensed by a sensing The HF920 shuts down via OVP when VCC rises
resistor between S and GND. When the sum of above VOVP for tOVP. In a flyback application, the
the sense resistor voltage and the slope auxiliary winding output voltage is proportional to
compensation voltage reaches the peak current the output voltage, so OVP protects the circuit
limit (VCS), the MOSFET turns off. from overstress during an output over-voltage
condition. The HF920 restarts automatically after
The peak current limit is set by VFB, as VCS = VFB
VCC drops to VCCR. The regulator resumes
/ Kdiv, for all normal operations. The maximum
normal operation once the fault disappears.
value of peak current limit is limited to VCSL
internally. This way, the output power is always Overload Protection (OLP)
limited to prevent excessive stress on the power The HF920 shuts down when OLP is triggered.
supply. The OLP fault occurs when VFB is pulled up to
Burst Operation VOLP for 8192 switching cycles. The HF920
restarts automatically when VCC drops to VCCR.
The HF920 implements burst-mode operation at
When the fault disappears, the power supply
no-load and light-load conditions. Burst-mode
resumes operation.
operation enables and disables the switching
pulse of the MOSFET alternately to reduce If frequency doubling is enabled, the HF920
switching loss. This helps minimize the stand-by doubles the switching frequency when VFB rises
power consumption and achieve high light-load to the OLP point.
efficiency.
Short-Circuit Protection (SCP)
As the load decreases, VFB decreases. The IC The HF920 shuts down when the S voltage is
stops switching when VFB drops below VBURL. As higher than VSCP, which indicates a short circuit.
the converter stops and the output voltage drops, The HF920 enters short-circuit protection (SCP),
VFB rises again due to the negative feedback which prevents any thermal or stress damage.
control loop. Once VFB goes over VBURH, the The HF920 restarts automatically when VCC
switching pulse resumes. If the load condition drops to VCCR. Once the fault disappears, the
remains the same, VFB decreases, and the entire power supply resumes operation.
process is repeated.
Thermal Shutdown (OTP)
Figure 3 shows the burst mode operation of the
When the junction temperature of the IC exceeds
HF920.
150°C, over-temperature protection (OTP) is
activated, and the main power MOSFET stops
VFB switching to protect the HF920 from thermal
0.7V damage. During the protection period, the
regulator is latched off. VCC is discharged to
0.5V
VCCR and recharged to VCCH by the internal high-
voltage current source. Once the junction
VDS temperature drop exceeds the thermal shutdown
recovery hysteresis, the HF920 resumes
operation.
PRO
PRO provides external protection. The HF920 is
shut down when the PRO voltage exceeds VPRO
and resumes operation once the fault disappears.
PRO protection can be used for input OVP or
any other protections (input UVP, OTP for key
Figure 3: Burst-Mode Operation components, etc.).

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Leading-Edge Blanking (LEB)

The HF920 implements a leading-edge blanking
(LEB) unit to prevent the MOSFET from turning
off prematurely due to its high turn-on current
spike. During the blanking time, the current
sensing signal on S is blocked.
The LEB unit contains two LEB times. The
current sensor LEB inhibits the current limitation
comparator for TLEB1, and the SCP LEB inhibits
the SCP current comparator for TLEB2. Figure 4
shows the primary current sense waveform and
the LEB.

Figure 4: Leading-Edge Blanking

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APPLICATION INFORMATION VDC(min) can then be calculated with t1 and

Equation (4). A larger input capacitor should be
Selecting the Input Capacitor
used if the estimated VDC(min) is too low.
The input bulk capacitor filters the rectified AC
input voltage and hold the bus voltage for the As a 900V offline regulator, the HF920 is ideal
converter. Figure 5 shows the typical DC bus for very high-voltage input applications, which
voltage waveform of a full-bridge rectifier. means a very high bus voltage is beyond the
rated voltage of normal high voltage electrolytic
capacitors. To meet the high bus voltage
requirement, stack capacitors as shown in
Figure 6.

Figure 5: Input Voltage Waveform

When a full-bridge rectifier is used, the input
capacitor is set at 2μF/W for the universal input
condition (85 ~ 265VAC), typically. For high-
voltage input applications (>185VAC), cut the
capacitor values in half. Very low DC input
voltages can cause thermal problems under
heavy-load conditions. It is recommended that
the minimum DC voltage is higher than 70V.
Estimate the minimum DC voltage with the Figure 6: Input Stacked Capacitor Circuit
following procedure.
The same type of capacitors should be chosen
First, estimate the input power (Pin) with for C1 and C2 to balance their voltages. Each
Equation (2): capacitor endures half of the bus voltage, but
VO  IO due to the capacitance distribution (typically ±
Pin  (2) 20% for electrolytic capacitors), their voltage

varies in mass production. In this case, R1 to R4
Where VO is the output voltage, IO is the rated should be used as the voltage balancing
output current, and η is the estimated efficiency. resistors.
Generally, η is between 0.75 and 0.85 To balance the voltage on C1 and C2, R1 to R4
depending on the input range and output should have the same value. R1 to R4 should be
application. a 1206 package size to meet the voltage rating
Then, the linear part of the DC input voltage (VDC) requirement. The R1 to R4 values should also be
can be expressed with Equation (3): large enough for energy savings. For example,
the total value of R1 to R4 is 20MΩ, which
2  Pin (3) consumes about 18mW at a 600VDC bus voltage.
VDC (t)  VAC(peak )2  t
Cin
Voltage Stress on the Primary MOSFET
At t1, the DC bus voltage reaches its minimum Typically, the maximum voltage stress on the
value, and the AC input starts charging the input primary MOSFET is design to be less than 90%
capacitor. t1 can be calculated with Equation (4): of its breakdown voltage for reliable operation.
VDC(t1) = VAC(t1) (4)

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The maximum voltage stress occurs when the For CCM at a minimum input, the converter duty
primary MOSFET turns off and can be calculated cycle can be determined with Equation (6):
with Equation (5):
(VO  VF )  N
D (6)
VDS(max)  VBUS(max)  N(VO  VF )  Vspike (5) (VO  VF )  N  VDC(min)
Where VF is the rectifier diode’s forward voltage, Where VF is the secondary diode’s forward
VO is the output voltage, N is the primary-to- voltage, and N is the transformer turns ratio.
secondary turns ratio, and Vspike is the voltage
spike caused by the transformer’s primary The MOSFET turn-on time can be calculated
leakage inductance. with Equation (7):

According to Equation (5), voltage stress can be D (7)

TON 
reduced either by choosing a small N or Vspike. fS
However, a small N leads to larger secondary
Where fS is the operating frequency.
stress, which means there is a trade-off to make.
A small Vspike requires a strong snubber to The input average current, ripple current, peak
suppress the voltage spike. current, and valley current of the primary side are
calculated using Equation (8), Equation (9),
The input circuit should be designed to
Equation (10), and Equation (11):
guarantee a proper VBUS(max) (i.e.: using
suppression components to protect it from Pin (8)
IAV 
surge). VDC(min)

Primary-Side Inductor Design (Lm) Iripple  K P  Ipeak (9)

Typically, the converter is designed to operate in
continuous conduction mode (CCM) under a low IAV (10)
Ipeak 
input voltage for universal input applications. KP
(1  )D
With a built-in slope compensation function, the 2
HF920 supports stable CCM control when the Ivalley  (1  K P )  Ipeak (11)
duty cycle exceeds 50%. Set the ratio (KP) of the
primary inductor ripple current amplitude vs. the Estimate Lm using Equation (12):
peak current value to 0 < KP ≤ 1, where a
VDC(min)  TON (12)
smaller KP means a deeper CCM, and KP = 1 Lm 
Iripple
stands for boundary conduction mode (BCM)
and discontinuous conduction mode (DCM). Current-Sense Resistor
Figure 7 shows the relevant waveforms. A larger
primary inductance leads to a smaller KP, which Figure 8 shows the peak current control
reduces the RMS current but increases the waveform with slope compensation.
transformer size. For most HF920 applications,
an optimal KP value is between 0.8 and 1,
considering the wide input range.

Figure 8: Peak Current Control Waveform with

Slop Compensation

Figure 7: Typical Primary Current Waveform

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When the sum of the sense resistor voltage and For resistors R5 to R7, 1206 packages should be
the slope compensation voltage reaches the used to meet the voltage rating requirement. The
peak current limit (VCS), the HF920 turns off the total value should be larger than 10MΩ for
internal MOSFET. VCS equals the maximum energy-saving purposes.
current-set point (VCSL) under full load.
Switching noise may couple to these large
Considering the margin, use 0.95 x VCSL for
resistors and disturb the PRO protection. It is
designs. The voltage on the sense resistor can
recommended to connect a bypass ceramic
be calculated using Equation (13):
capacitor to PRO. Place this capacitor as close
Vsense  0.95  VCSL  SRamp  TON (13) to the IC as possible.

Where SRAMP is the slope compensation ramp in Thermal Performance Optimization

proportion to fS. Typically, SRAMP = 21mV/μs The HF920 is dedicated to high input voltage
when RFSET = 200kΩ. applications. However, the high input voltage
can cause a greater switching loss on the
The value of the sense resistor is calculated MOSFET, which can lead to poor thermal
using Equation (14): performance. Measures should be taken to
Vsense reduce the switching loss when designing these
R sense  (14)
Ipeak applications.
First, try to use a lower switching frequency if
The current-sense resistor should be chosen possible. Then use a small transformer turns
with an appropriate power rating. Its power loss ratio to minimize the reflected voltage on the
can be calculated with Equation (15): primary winding. Thus, VDS is reduced. Finally,
 Ipeak  Ivalley 2 1 2
reduce the turn-on loss, since the turn-on loss
   Ipeak  Ivalley    D  Rsense
Psense   (15) composes a large part of the switching loss.
 2  12 

Turn-on loss is the product of the turn-on current
Input Over-Voltage Protection on PRO spike and VDS. Reducing the turn-on loss can be
A typical input OVP circuitry of the HF920 is achieved by reducing VDS or the turn-on current
shown in Figure 9. The input OVP point can be spike.
calculated with Equation (16): Reducing VDS by using a small turns ratio is
R5  R6  R7  R8 discussed above. Another way of reducing VDS
VINOVP  VPRO  (16) when the MOSFET turns on is to set the HF920
R8
to work under deep DCM. In deep DCM, the VDS
oscillation is fully damped, so there is no chance
of turning on at the high peak value.
The turn-on current spike is caused by a
parasitic capacitor and output diode reverse
recovery.
DCM operation helps prevent the output diode’s
reverse recovery. The transformer structure
should be designed to achieve minimum
parasitic capacitance of each winding and
between the primary and secondary windings.

Figure 9: Input Over-Voltage Protection Set-Up

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PCB Layout Guidelines

Efficient PCB layout is critical for achieving
reliable operation, good EMI performance, and
good thermal performance. For best results,
refer to Figure 10 and follow the guidelines below.
1. Minimize the power stage switching stage
loop area. This includes the input loop (C8–
C6-T1–U2–R21/R22–C8), the auxiliary
winding loop (T1–D6–R16–C11–T1), the
output loop (T1–D6–C9–T1, T1–D1–C1–T1,
and T1–D2–C3–T1), and the RCD loop (T1– Bottom
D5–R5/R7/C4–T1). Figure 10: Recommended Layout
2. Ensure that the power loop ground does not Design Example
pass through the control circuit ground. If a Table 2 is a design example using the
heat sink is used, connect it to the primary application guidelines for the given
GND plane to improve EMI and thermal specifications.
dissipation.
Table 2: Design Example
3. Place the control circuit capacitors (for FB, VIN 85 to 420VAC
PRO, and VCC) close to the IC to decouple VOUT1 13.5V
the switching noise. IOUT1 0.3A
4. Enlarge the GND pad near the IC for good VOUT2 8V
thermal dissipation. IOUT2 0.05A
VOUT3 8V
5. Keep the EMI filter far away from the IOUT3 0.05A
switching point. fS 50kHz
6. Ensure enough clearance distance to meet The detailed application schematic is shown in
the insulation requirement. Figure 11. The typical performance and circuit
waveforms are shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
evaluation board datasheets.

Top

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TYPICAL APPLICATION CIRCUIT

EE16 Lm=2.5mH
N1:N2:N3:N4:N5:N6=22:170:26:16:16:26

NC D1
N1 VOUT3
FR1 10 C2
L

ES1D/200V/1A C1 R1 8V/50mA
L 1 N5 47uF/25V 1uF/25V 6.8k/1%
10/1W 9 D2 GND3
R2
D3 D4
R3 5.1M/1206 N2 VOUT2
NC 1N4007 1N4007 8 C5
CX1 C4 C3
ES1D/200V/1A R4 8V/50mA
0.22uF/275V C6 R5 R7 1nF/630V/1206 N4 47uF/25V 1uF/25V 6.8k/1%
LX1 22uF/400V R6 NC 200k/1206 2 7 GND2
5.1M/1206 R9
85VAC to 420VAC C7
R8
NC 3
51/1206 330pF/200V/0805
D5 VOUT1
24mH C8 R10 N3 5 D6
CX2 S1ML/1kV/1A
22uF/400V 5.1M/1206 4 MBRS3200/200V/3A C9 C10 13.5V/0.35A
0.22uF/275V N6 470uF/35V 0.1uF/50V

L
R11 D7 D8 6 GND1(L)
NC
1N4007 1N4007 R12 D9
5.1M/1206 BAV21W/200V/0.2A CY1
N PRO
R16 R13
5.1/1206 1nF/250V 2k/1%
R20
93.1k/1% R14
U1
C11 97.6k/1%
C12
U2
22uF/50V
1 8 0.1uF/50V
VCC D R17
2 10k/1%
FSET
EL817B
3 6
PRO PRO S
C16
1nF/16V R15 C15 4 5 C14 C13
FB GND R19
200K 1nF/16V R22 R21 2.2nF/16V
HF920GSE 5.1/1%/1206 3.3/1%/1206
300k/1%
22nF/50V
U3
TLV431AFTA/1.24V

R18
9.76k/1%

Figure 11: Typical Application Schematic

1T

NC N5
1T

N4
1T
N6
1T
A
N5 N3
B 1T

N2
1T
N6 N1
1T

a) Connection Diagram b) Winding Diagram

Figure 12: Transformer Structure

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Table 3: Winding Order

Terminal
Tape (T) Winding Wire Size (Ф) Turns (T)
Start → End
1 N1 1 → NC 0.15mm*2 22

1 N2 2→1 0.15mm*1 170

1 N3 4→3 0.1mm*1 26

1 N6 5→6 0.3mm TIW *1 26

1 N4 10 → 9 0.16mm TIW *1 16

1 N5 A→B 0.16mm TIW *1 16

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FLOW CHART

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EVOLUTION OF THE SIGNALS IN PRESENCE OF FAULTS

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PACKAGE INFORMATION
SOIC8-7A

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PACKAGE INFORMATION (continued)

SOIC14-11

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume
any legal responsibility for any said applications.

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