U.S.N.

B.M.S. College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

December 2019 / January 2020 Semester End Main Examinations

Programme: B.E. Semester: III

Branch: Computer Science And Engineering Duration: 3 hrs.
Course Code: 19CS3PCCOA Max Marks: 100
Course: Computer Organization and Architecture Date: 24.12.2019

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may suitably assumed.

UNIT - I
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank

1 a) Convert the Following pairs of decimal numbers to 5-bit 2’s 10

complement numbers, then perform addition and subtraction on each
pair. Indicate whether or not overflow occurs for each case.(i) 7 and 13
(ii) 12 and 9.

b) Write an Assembly Language Program to add n numbers using Indirect 05

addressing mode.
pages. Revealing of identification, appeal to evaluator will be treated as malpractice.

c) Describe any 5 Assembler Directives with example. 05

UNIT - II
2 a) Explain the Technique used to resolve the conflict which arises when two or 10
more entities contend for the use of single resource in a computer system.

b) Distinguish between 05
i. ISR & subroutine
ii. Polling and interrupt.

c) Consider the case of a single interrupt request from one device. The device keeps 05
interrupt request signal activated until it is informed that the processor has
accepted its request. This activated signal, if not deactivated, may lead to
successive interruptions causing the system to enter infinite loop.
Determine what measures the processor can take to avoid successive
interruptions causing the system to enter infinite loop.

UNIT - III
3 a) Explain Virtual Memory Address Translation using Paging 10

b) Design a memory of size 16x8 using 4x8 memory chips. Show your design with 10
neat diagram.
 OR
4 a) Explain the organization of 1K x 1 memory chip 10

b) A cache is organized in the direct-mapped manner with the following 05

parameters:
 Main memory size of 64K words.
 Blocks of 16 words each.
 Cache consisting of 2K words.
i. How many bits are there in a main memory address?
ii. How many bits are there in each of the TAG, BLOCK and WORD fields?
05
c) Illustrate with neat diagram Set – Associative mapping technique.

UNIT - IV
5 a) Explain the design of 4-bit carry look ahead adder. 10

b) Multiply (+22)(Multiplicand) x Multiplier(-6) using Booth’s 05

Algorithm Method

c) Multiply 110101 (Multiplicand) x 011011 (Multiplier) using Bit-Pair 05

Recoding Method

OR
6 a) Explain the IEEE Floating Point Formats. Represent (0.0625)10 in 10
IEEE Floating point Formats.

b) Multiply 14 x 12 using sequential circuit binary multiplier along with the 10

hardware configuration diagram.

UNIT - V
7 a) Using a Single Bus Architecure,Write & Explain the sequence of control steps 10
required for ADD THE (IMMEDIATE) NUMBER NUM TO REGISTER R1

b) Explain with block diagram the basic organization of a Hardwired Control Unit 10

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