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The document describes the instruction fetch and execute cycle of a microprocessor (MP) connected to RAM via a 16-line bus. It provides an assembly language code snippet with 5 instructions and initial memory contents. When each instruction is fetched and executed: 1) The program counter (PC), accumulator (AC), and instruction register (IR) are updated with the new values. 2) The appropriate bus signals - such as address, data, read - are activated to fetch operands from memory locations and write results. 3) The AC is operated on according to the instruction and the memory is updated after instruction 5.

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162 views3 pages

Q1 Solution

The document describes the instruction fetch and execute cycle of a microprocessor (MP) connected to RAM via a 16-line bus. It provides an assembly language code snippet with 5 instructions and initial memory contents. When each instruction is fetched and executed: 1) The program counter (PC), accumulator (AC), and instruction register (IR) are updated with the new values. 2) The appropriate bus signals - such as address, data, read - are activated to fetch operands from memory locations and write results. 3) The AC is operated on according to the instruction and the memory is updated after instruction 5.

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api-3801329
Copyright
© Attribution Non-Commercial (BY-NC)
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Section: Roll #

Computer Organization and Architecture TE-C


Wednesday, February 21, 2007
QUIZ # 1: Instruction Fetch and Execute Cycle & Bus
Max Marks = 25; Max Time: 25 minutes
BUS = 16
Please write your answers in the space provided. MP lines RAM

Statement
Above diagram shows a microprocessor (MP) and its connection to the RAM via Bus of 16 lines. The
following table A shows a piece of assembly language code for the MP microprocessor and table B shows
data values at some memory locations (all numbers are Hex):

TABLE A - INSTRCUTIONS
No. Memory Address Instruction Machine Code Comments
1 F1FD LOAD B12D 10 B12D Move the contents of address
location B12D into AC
2 F1FE SUB B12E 11 B12E AC  AC - Contents of
address location B12E
3 F1FF ADD B12F 01 B12F AC  AC + Contents of
address location B12F
4 F200 SUB B130 11 B130 AC  AC - Contents of
address location B130
5 F201 STORE B12D 00 B12D Store value of AC at location
B12D

TABLE B – DATA
ADDRESS CONTENTS
B12D 05
B12E 02
B12F 07
B130 04

Initially Program Counter (PC) = F1FD, Accumulator (AC) = 0 and


Instruction Register (IR) = ?. For Questions 1-4 please give one line description otherwise you will get
0
1. What is the word size for MP? (1 Point) 6*4 = 24 (code in IR)

2. What will be the size of IR register in bits? (1 Point) 24

3. What is the size of AC in bits? (1 Point) 24 = word = data size

4. Does the bus has enough lines for address and data, please explain in one line? (2 Point)
Yes. May be more than one fetches needed
Section: Roll #
5. As each instruction of table A is fetched and executed by the processor MP, please show the values
of PC, AC, IR registers, memory location values and name the bus signals that are used: (25 Points)

Instruction 1: PC = F1FE AC = 5 IR = 10 B12D


ADDRESS CONTENTS
B12D 05
B12E 02
B12F 07 Bus signals: Bus Request, Bus Request acknowledge, Bus grant,
B130 04 Address, data, read

Instruction 2: PC = F1FF AC = 3 IR = 11 B12E


ADDRESS CONTENTS
B12D 05
B12E 02 Bus signals: Bus signals: Bus Request, Bus Request acknowledge,
B12F 07 Bus grant, Address, data, read
B130 04

Instruction 3: PC = F200 AC =10 IR = 01 B12F


ADDRESS CONTENTS
B12D 05
Bus signals: Bus signals: Bus Request, Bus Request acknowledge,
B12E 02
Bus grant, Address, data, read
B12F 07
B130 04

Instruction 4: PC =F201 AC = 6 IR = 11 B130


ADDRESS CONTENTS
Bus signals: Bus signals: Bus Request, Bus Request acknowledge,
B12D 05
Bus grant, Address, data, read
B12E 02
B12F 07
B130 04

Instruction 5: PC = F202 AC = 6 IR = 00 B12D


Section: Roll #
ADDRESS CONTENTS
B12D 06
B12E 02 Bus signals: Bus signals: Bus Request, Bus Request acknowledge,
B12F 07 Bus grant, Address, data, read, write
B130 04

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