Combinational Circuits
Two Classes of Logic Circuits
Combinational Circuit
o Each outputs depends entirely on the immediate input.
Sequential Circuit
o Each output depends on both present inputs and state.
Analysis Procedure
Steps
1. Label the Inputs and Outputs
2. Obtain the functions of intermediate points and the outputs.
3. Draw the truth table.
4. Deduce the functionality of the circuit.
Design Methods
Different Combinational Circuit Design Methods
Gate-Level Design Method (With Logic Gates)
Block-Level Design Method (With Functional Blocks)
Gate-Level Design: Half Adder
Design Procedure
o State Problem
o Determine and label the inputs and outputs of circuit.
o Draw the truth table.
o Obtain simplified Boolean functions.
o Draw the Logic Diagram
Gate-Level Design: Full Adder
Half adder adds up only two bits
To add two binary numbers, we need to add 3 bits (including the carry)
Gate-Level (SSI) Design: Code Converters
Takes an input code, translates to its equivalent output code.
Example, BCD to Excess-3 Code Converter
Block-Level Design
More complex circuits can also be built using block-level method
In general, block-level design method (as opposed to gate-level design) relies on algorithms
or formulae of the circuit, which are obtained by decomposing the main problem to sub-
problems recursively (until small enough to be directly solved by blocks of circuits)
First example shows how to create a 4-bit parallel adder using block-level design
Using 4-bit parallel adders as building blocks, we can create
o BCD-to-Excess-3 Code Converter
o 16-bit Parallel Adder
4 Bit Parallel Adder
Adds two 4-bit numbers together and a carry-in to produce a 5 bit result
Use an alternative design.
o Addition formula for each pair of bits (with carry in)
BCD to Excess 3 Converter using Block Level Design
Excess-3 Code can be converted from BCD code using truth tables.
Gate-Level Design can be used since only 4 inputs.
Use problem-specific formula.
o Excess-3 Code = BCD Code + 0011
16 Bit Parallel Adder
Larger parallel adders can be built from smaller ones.
A 16-bit parallel adder can be constructed from four 4-bit parallel adders.
Magnitude Comparator
A device that compares 2 unsigned values A and B, to check if A > B, A =B, or A<B
Circuit Delays
Given a logic gate with delay t. If inputs are stable at times t1,t2,…., then the earliest time in
which the output will be stable is : max (t1,t2,…) + t
To calculate the delays of all outputs of a combinational circuit, repeat above rule for all
gates.