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Linearity-Voltage Divider

1) The document discusses voltage divider circuits and how loading error affects their linearity. Loading error is defined as the percentage difference between the output voltage with no load (VoNL) and with a load (VoL). 2) Graphs and tables of experimental data show that while the individual divider circuits themselves are linear, the addition of a load causes the relationship between output voltage and resistance to become nonlinear. 3) Loading error increases as the load resistance decreases and depends on the specific resistance values used in the divider network.

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0% found this document useful (0 votes)
75 views13 pages

Linearity-Voltage Divider

1) The document discusses voltage divider circuits and how loading error affects their linearity. Loading error is defined as the percentage difference between the output voltage with no load (VoNL) and with a load (VoL). 2) Graphs and tables of experimental data show that while the individual divider circuits themselves are linear, the addition of a load causes the relationship between output voltage and resistance to become nonlinear. 3) Loading error increases as the load resistance decreases and depends on the specific resistance values used in the divider network.

Uploaded by

mahmab70
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE463

Voltage Divider Circuits


Linearity

Dr. Marwan MARGHEM


Voltage Divider Circuits (Loading Error)
• Example
Voltage Divider Circuits (Loading Error)

• Solution
a. VoNL: Output voltage with no load.

b. VoL: Output voltage with load.


Voltage Divider Circuits (Loading Error)

Note:
The effect of loading error is not linear
Voltage Divider Circuits

𝑉𝑜𝑁𝐿 −𝑉𝑜𝐿
• %𝑒 = × 100
𝑉𝑜𝑁𝐿

• VoNL: Output voltage with no load.


• VoL: Output voltage with load.
Voltage Divider Circuits (Loading Error)
R2 kΩ VoL[V] VoNL [V] %e
Vs=10V, R1=5 kΩ, and RL=100 kΩ
1 1.65 1.67 0.83

2 2.82 2.86 1.41


Loading Error
3 3.68 3.75 1.84
4.00
4 4.35 4.44 2.17 3.00

%e
2.00
5 4.88 5.00 2.44
1.00
6 5.31 5.45 2.65 0.00
0 2 4 6 8 10 12
7 5.67 5.83 2.83
R2
8 5.97 6.15 2.99

9 6.23 6.43 3.11

10 6.45 6.67 3.23


Voltage Divider Circuits (Linearity)
R1 kΩ R2 kΩ VoNL [V]

5 1 1.67

5 2 2.86
1
5 3 3.75
8.00
5 4 4.44
6.00
5 5 5.00
Vo
4.00

5 6 5.45 2.00
0.00
5 7 5.83
0 5 10 15
5 8 6.15 R

5 9 6.43

5 10 6.67
Voltage Divider Circuits (Linearity)
R1 R2 VoNL
All Resistors in kΩ, and all Voltages in Volts
1 5 8.33
2 5 7.14 2
3 5 6.25
10.00
4 5 5.56 8.00
5 5 5.00 6.00
Vo

4.00
6 5 4.55 2.00
0.00
7 5 4.17
0 5 10 15
8 5 3.85 R
9 5 3.57
10 5 3.33
Voltage Divider Circuits (Linearity)
R1 R2 VoNL
All Resistors in kΩ, and all Voltages in Volts
100 1 0.10

100 2 0.20 3
100 3 0.29
1.00
100 4 0.38 0.80

100 5 0.48 0.60


Vo

0.40
100 6 0.57 0.20
0.00
100 7 0.65
0 5 10 15
100 8 0.74 R
100 9 0.83

100 10 0.91 Linear Relation


Voltage Divider Circuits (Linearity)
R1 R2 VoNL
All Resistors in kΩ, and all Voltages in Volts
1 100 9.90

2 100 9.80
4
3 100 9.71
10.00
4 100 9.62
9.80
5 100 9.52 Vo 9.60
9.40
6 100 9.43 9.20
7 100 9.35 9.00
0 5 10 15
8 100 9.26
R
9 100 9.17

10 100 9.09 Linear Relation


Voltage Divider Circuits (Linearity)
R1 R2 VoNL
All Resistors in kΩ, and all Voltages in Volts
0.1 1 9.09

0.1 2 9.52 5
0.1 3 9.68
10.00
0.1 4 9.76 9.80
Vo 9.60
0.1 5 9.80 9.40
9.20
0.1 6 9.84
9.00
0.1 7 9.86 0 5 10 15
R
0.1 8 9.88

0.1 9 9.89

0.1 10 9.90
Voltage Divider Circuits (Linearity)
R1 R2 VoNL All Resistors in kΩ, and all Voltages in Volts
1 0.1 0.91

2 0.1 0.48 6
3 0.1 0.32
1.00
4 0.1 0.24 0.80
Vo 0.60
5 0.1 0.20 0.40
0.20
6 0.1 0.16 0.00
0 5 10 15
7 0.1 0.14
R
8 0.1 0.12

9 0.1 0.11

10 0.1 0.10
Voltage Divider Circuits (Linearity)
All Resistors in kΩ, and all Voltages in Volts
R1 R2 VoNL
5 4.5 4.74
7
5 4.6 4.79
5 4.7 4.85 5.40
5.20
5 4.8 4.90

Vo
5.00
5 4.9 4.95
4.80
5 5 5.00 4.60
5 5.1 5.05 4 4.5 5 5.5 6
R
5 5.2 5.10
5 5.3 5.15
5 5.4 5.19
Linear Relation
5 5.5 5.24

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