JAYPEE UNIVERSITY OF ENGINEERING & TECHNOLOGY, GUNA
DEPARTMENT OF Computer science & engineering
A PRACTICAL WORK BOOK
of
COMPUTER ORGANIZATION & Architecture LAB
(18B17CI414)
SUBMITTED
TO
Dr. Rahul pachori
Name of student: ENRL NO.
Class: BATCH:
BRANCH: SESSION:
Name:Toshika Raikwar Er No.:211B329
INDEX
Date of
S.No. Aim of the experiment signature remarks
submission
1
Experiment no. # 01
AIM: Design of basic digital circuits using logic gates.
Exercise #1: Design two inputs and five outputs All-in-One logic gate circuit shown in Fig.1
using Logisimsimulator with (i) data width 1 (ii) data width 4.
Name:Toshika Raikwar Er No.:211B329
Boolean Expressions Logic Diagram
C = not A
D = A.B
E = A+B
F = ~(A.B)
G = A⊕B
Truth Table
Exercise#2: Design two inputs and one output All-in-One logic gate diagram shown in Fig.2
using Logisimsimulator with (i) data width 1 (ii) data width 8.
Boolean Expressions Logic Diagram
~b c d + b ~c ~d + a ~c d + a c ~d
Truth Table
Exercise#3: Design a three-input majority detector combinational digital circuit using
Logisim simulator which shows output equal to 1 if the input variables have more 1's than 0's,
the output is 0 otherwise.
Boolean Expressions Logic Diagram
Name:Toshika Raikwar Er No.:211B329
bc+ac+ab
Karnaugh (K) Map
Exercise#4: Design a combinational circuit with three inputs and three outputs. When the
input is 0, 1, 2, or 3, the output is one greater than the input and when the input is 4, 5, 6, or 7,
the output is one less than the input. Display the input and output digits using Hex digit
display with splitter.
Boolean Expressions Logic Diagram
X=AC+BC+AB
Y=~A~BC+A~B~C+~AB~C+ABC
Z=~C
Karnaugh (K) Map
Fig6:Increase for 0,1,2,3 Decrease for 4,5,6,7
Experiment no. # 02
AIM: Design of binary adders and subtractors.
Exercise #1: Design half adder and half subtractor shown in Fig. 1 and Fig. 2 using logisim
simulator
Name:Toshika Raikwar Er No.:211B329
Boolean Expressions Logic Diagram
Sum:~a b + a ~b
Carry:ab
Difference:~a b + a ~b
Borrow:a~ b
Karnaugh (K) Map
Exercise#2: Design full adder using (i) basic gates only (ii) by adding half adder as sub
circuit using logisim.
Boolean Expressions Logic Diagram
~a ~b c + ~a b ~c + a ~b ~c +a b c
Karnaugh (K) Map
Exercise#3: Design 4-bit binary adder using one half adder and 3-full adders as shown in
Fig. 5. Use half adder and full adders as sub circuits in the design. Display both the input
digits; output digit and end carry digit using Hex digit display with splitter available in
logisim simulator.
Boolean Expressions Logic Diagram
x=b+a;y=a;z=~c ~d f g h + ~c ~d e
+ ~c d ~e ~f + ~c d ~e ~g + ~c d
~e ~h + c ~d ~e ~f + c ~d ~e ~g +
c ~d ~e ~h + c d f g h + c d e;u=~e
~f g h + ~e f ~g + ~e f ~h + e ~f
~g + e ~f ~h + e f g h;v=~g h + g
~h
Truth Table
Name:Toshika Raikwar Er No.:211B329
Name:Toshika Raikwar Er No.:211B329
