--*****************************************************************--
-- Creates a 32 individual 64-bit registers
--******************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL; -- for type conversions
--Entity declaration
entity Register_File is
port ( clk : in std_logic;
RegWrite : in std_logic ;
Rd_Addr_Reg1 : in std_logic_vector(4 downto 0);
Rd_Addr_Reg2 : in std_logic_vector(4 downto 0);
Wt_Reg : in std_logic_vector (4 downto 0);
Wt_Data : in std_logic_vector (63 downto 0);
Rd_Data1 : out std_logic_vector (63 downto 0) ;
Rd_Data2 : out std_logic_vector (63 downto 0)
);
end entity Register_File;
--Architecture Declaration
architecture behavoral1 of Register_File is
-- Declare a subtype nominate "Reg" , size 64 bits
subtype Reg is std_logic_vector (63 downto 0);
--Declare a type "RegisterFile" as array of 32 of "Reg"
type RegisterFile is array(0 to 31) of Reg;
-- The same work as declare an array of size 32, and of width 64.
-- It can be replaced by :
-- type RegisterFile is array(0 to 31) of std_logic_vector(63 downto 0);
--declare the signal to work with
signal RegFile : RegisterFile ;
begin
process (clk) --The clock is the onlything on the sensitivity list
begin
--Only works on the rising edge of the clock
if (clk ='1' and clk'event ) then
--If the write enable is high, then write. Otherwise, read
if(RegWrite = '1') then
--Select the correct register and store the input there
RegFile(to_integer(unsigned(Wt_Reg))) <= Wt_Data;
else
--Read the data from each selected Register
Rd_Data1 <= RegFile(to_integer(unsigned(Rd_Addr_Reg1)));
Rd_Data2 <= RegFile(to_integer(unsigned(Rd_Addr_Reg2)));
end if ;
end if;
end process;
--Make Sure that last Register is at 0
RegFile(31) <= (others => '0');
end architecture behavoral1;
architecture behavoral2 of Register_File is
-- declare an array of size 32, and of width 64.
--It can be replaced by :
type RegisterFile is array(0 to 31) of std_logic_vector(63 downto 0);
--declare the signal to work with
signal RegFile : RegisterFile ;
signal ZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Addr_31 : std_logic_vector(4 downto 0) := (others => '1');
begin
--read at any time
Rd_Data1 <= RegFile(to_integer(unsigned(Rd_Addr_Reg1)));
Rd_Data2 <= RegFile(to_integer(unsigned(Rd_Addr_Reg2)));
--The clock is the onlything on the sensitivity list
process (clk)
variable startup : boolean := True;
begin
-- for initialization of RAM during start of simulation
if (startup = True) then
RegFile(31) <= (others => '0');
RegFile(0) <= std_logic_vector(to_unsigned(38,64));
RegFile(1) <= std_logic_vector(to_unsigned(16,64));
RegFile(2) <= std_logic_vector(to_unsigned(12,64));
RegFile(3) <= std_logic_vector(to_unsigned(3,64));
RegFile(4) <= std_logic_vector(to_unsigned(4,64));
RegFile(5) <= std_logic_vector(to_unsigned(5,64));
RegFile(6) <= std_logic_vector(to_unsigned(5,64));
RegFile(7) <= std_logic_vector(to_unsigned(1,64));
startup := False;
--write on the positive edge of the clock
elsif (clk ='1' and clk'event ) then
--If the write enable is high, then write. Otherwise, read
if(RegWrite = '1') then
if (Wt_Reg /= Addr_31) then
--Select the correct register and store the input there
RegFile(to_integer(unsigned(Wt_Reg))) <= Wt_Data;
else
RegFile(to_integer(unsigned(Wt_Reg))) <= ZERO;
end if;
end if ;
end if;
end process;
--Make Sure that last Register is at 0
RegFile(31) <= (others => '0');
end architecture behavoral2;
--Configuration
configuration Config_Register_File of Register_File is
for behavoral2
end for;
end configuration Config_Register_File;
