COMBINATIONAL CIRCUITS ™ Numbey systems, Boolean algebra, Logic garces FMAM, Sor and pos act as raw materials for building 2 digital system. S.A clreutt outpute a digit in the form ot 4 bitte” O te vepresented by 0000,4 is represented by co0|y- 4 by 1001. A combinational circuit is to be derigned which takes these 4 bits af input and output as 4, Fo the digit ¢s 25,and © otherwise. a-f only AND/OR and Not gates moy be used, what it the minymum dumber of gates required ? tay 4 uss WR (da Output= 4) Input zs = 0, otherwise Input 79. dont care <2 Output) = Sm(5,6,4,2,9) +4 (10) My L213 INAS) cp AB eo OL u lo fa A+ BDTBC x » * x HS 7 co * No-o-f goter = 3 OCAIINEU WILT Lallloca&In the above question, find the Minimum number o ef gates only it a Input gates are to be uted? lau SD 3 Le) 2 Cd 4 Output, F- A+BO+Be A = A+e(c+d) + B vNo-vot 2 Input qates Ls ¢ required =3 . 2D 8: Twe products are cold rom a vending machine, wehich has two puch buttens Pp, and P,, When o button ts pressed ithe price of the correcponding product ts displayed Inia + - segment display. df no buttens are pressed, ‘o’ ic displayed , signitying Rs ot tf only Py vs precced, ‘2. (e displayed 1 Signifying ©Rs.Q', If only Py is pressed, ‘5° is pressed, signitying “Rs+S'. Tf both Pr and Pa are pressed, ‘E? Is displayed, Siqnitying ‘Erm? The names of the seqmrents in the 4 - seqment display, and the glow ef the display for %o', 627, ‘S!, Se’ and are chown below. A ° 2 s 2 ee ee “| jf Jot ft. fle Consider D c Puch butten pretred|act pressed \n equivalent +e Logic Llo respectively OCAINEU WILT Lal locaRNA Segment glowing Inot glowing In the display ts equivalent +o Logic tlo respectively Itia seqment ® +t» 4 are considered as -unetions of ‘the following |e correct: Proand Ps , then whith o Cr ae BG Q=PitP2, d=ecte Co Ge PtPe, ea bre Po g= Pi tha, go bre Let us construct @ truth table for @ +o q- Pr Py a b © d « + q 9 ° ° ‘ ‘ \ t \ ( ° ° t 2 { \ ° ' ‘ ° \ 4 ° 5 \ ° | ' . \ ' i ( € ' o 0° \ ‘ ‘ , ast b= Po = Ha Pre = % c= PF det © = Smet) 3) = WMA) = fo+P, fe se mlo, 213) = TMU) = Pot Pa @= Sm (12,2) = WM lo) = PrtPa Consider, e+e = Fett hy sw d= e+e and q= PitPa varied wit ValliacaBut b+e = P+ th thy ties, b+e #@e (by What are the minimum number of NOT gates and Q-Input oR gates required to design the logic of the driver for this 4-Seqment dicplay? A-2 NOT and 4 oR B 2 NOT and 4 oR cl Not and B OR D2 Not and 3. og | A=| kde 4+ Ne gatts required | ! | 1 Q-NOT gates and 3-0R qotts are required. skAdvantaget of Digital System! —> Pigital systems are \ Compact 6. Cost effective a. Accuracy 3. Precision 4. Stovage S: Faster OCAIINEU WILT LalllocaCombinational creuits WD Pretent On pretent input only. ao Requiyet ho memory awd No +eed back Ea* Halt adder, F-Ay Mur, Decoder ete ARITHMETIC > Consider addition ot ° ° ° 44 4 eu —_— ° \ SE HALF ADDER? => Addt two bits and A B S Cy o ° ° ° ° \ \ ° \ ° r ° \ \ ° \ ee ada ty =AB output depende Sequential elreults W Pretent output depende On precent Input &previot output: UD Memory present dip Feedback is present FA? Fliptlops, Registers and counters Cte CLR CULTS two binary digits \ \ => +! + 4 — — 10 106 rx carry sum outputs cayry and cum bit! A 8 OCAIINEU WILT Lallloca* Halt adder using NANDINOR! | i | CD veing NAND:- — S=A@B nBHCy Min number of NAND gates required = 5 Gb Using Nor: > Contider,, A@B= ABtAB = (A+B) (A+B) OR- AND = NoR-NOR | Cy = AB Rte = AB—AB= Carry 3 Min no-ot NOR gates = 5 ( a 324 6 > In a general addition, we 2 ¢ 2ae need to add a-digit< at 4 oo 6 4 8 a time which are two - OCanMneu will Valllovcainputs and one carry -tyrom previvue addition. car roo tt mw e to toy ee Lo ° ' % Hence we gor -full adder, which performs 3-ble addition. HR FULL ADDER! - A B Cen SF Cy (Cour) ° ° ° ° ° ° ° \ \ ° ° \ ° ' ny oS = Srolt, 24,4) ° ‘ \ ° ' = A@BO@c 1 ° ° ' ° Cy = Sm( 31516.) { ° \ ° \ = A@B)C+aR ‘ \ ° ° ' ! \ \ i \ > Consider k-map tor simp lifeation of Cout , BC t 0 s oo ot it Cy = ABTBCTAC (" . 2 Rect Age tABC+ABC | ( @ = (A@a)c + AB OCAIINEU WILT LalllocaA@B |___+4 A@DRO CHA © )> (A@e) © OD — cy= AEH +AS tov) (Ren bp) = Cy=ABtec+Ac — *4 a* rep of cys Requires Lees number ot gates and rept Hat Less propagation delay, ' tpd = ata | Q. Ln the clrewt of Higure A,8,¢ are the inputs | and Pi\G are the +wo outputs. The circuit tsa a B ce 8 p OCAIINEU WILT LalllocaCAV halt adder where P is -the sum and & {is carry (By halt adder where P js carry and @ js sum US Full adder where Pp jig sum and @ js Carry @) ull adder where ¢ is carry and & is sum 8 = AB+BC +AC = Carry of Full adder P = A @@@c = Sum of full adder [—_ cy # Tenplementaton of FA using tHA's: ADBOa =$ A’ —la s HA WA (a@eye 6 6 Cy Gy= Aas | FA = 2 HA + LOR gate (n@ere a Implement FA using a ip NANDINOR gates Pipl ly Bea AB HA08)c =%y OCaeU WILT UallouaMin norot gots required = 9 —™ Sum, $= A@®e@®e and carry, Cy = AB+RO+AC are both self dual Functions: Hence NAND &NOR trnplementation is same. Q-A full adder can be made out of (0) Tus halt adders Ch) Two halt adders ond a Not gate Gi twe halt adders and an oR gate (A) Two halt adders and an AND gate VPA - 2 HA 4 1 OR qate &- Which one of +the following will qive the sum of full adder a4 output! CH) Three Input majority carry VI Three bit parity checker (ce) Three bit comp arater (A) Three bit counter Sum of full adder = A@e@c | = odd parity detector | Three input Majority carry Carry of full adder @.tThe halt adder circuit In the given figure bas Ip i—)— inputs ABe Tl A B OCAIINEU WILT LalllovcaThe Leqte level of P and 4 outputs will be (oP =o and ao L6) P=0 and a=! Ke) P=t and Q@=0 (4) pet and & Consider substractions in decimal and binary syste Decimal: 1 OY Bor row 3 GB C10) a “2 ZA. Decimal “10! 4 04 Difference Binary:- TD Borrow o 1 Oo Uv=2) - —. =1 of — _— 7 A A ce ditterence RNOTE*- X-oR (£ aleo called quarter adder- FHALF CUBTRAC TOR! A 8 Dp Be ° ° o D= AGB+AB= AGB ° ' ' ' BL = AB \ oO ' eo OCaINIeEU WILT Uallloca™ Hol adder and halt cubtvactor ditty juct by a tingle inverter A — o e— 8. ¥ uy —> Minimum number of gate required 0 tm plement holt subtvactor are 5 (2a \\p NANDI NOR gates) Q@. Consider the +fellowing statements ! A halt—adder Il. @s a halt subtractyr alco 2. Has two outputs (y= %-y and sy=%@y fer tro Inputs x and y- 3B. Has two outputs Cy= 444 and Sy= 2OY for two inputs kK and y: 4. 2e a combinational circuit Which of the statements given above tslare corrrect?! @) 1,2 and 4 (ey 1,2 and 4 GF YH only (ad) 2 and 3 Cer a,4 Halt adder: Sum= 1@y Carry = 44 It te a combinational circuit OCAIINIEU WILT LalllovaBorrow qiven=4 Ditference=+ Borrow taken =1 SROFULL SUBTRACT OR! — Takes three InputS! A,B > Serrow qiven eo nett (Lower) @tn and outputs : pitterence, Bour (Borre to be taken trom higher) A B Be 5 8. 0 o D ° ° ° ° ‘ ' \ ° \ ° 1 \ ° 1 1 ° \ ' ° ° ' ” \ ° ' ° 5 ‘ ' ° ° ° Ditterence, D=Sm(1,2,4,9) = A@aOc Bervow, 6s = Sml1 2139) = Rar l(aovde OCAINEU WILT LalllovcaOCAIINEU WILT LalllocaBec A@sOC | a | x Rwac)= ABC*BS) = ABC+ABC te 8@c L : . Raceawet+ase | aA S | Be = Emlt 2139) Lt if Q full subtvactor Full subtvacter using halt pybtracter!- Bo= Aa +(ageye FS = atts+4 oR NOTE! Number of two Input NAND| NOR gates required te tm plement Full sulstvactor + 979° —> Consider 4—Lit binary addition, OCAIINEU WILT LalllocaKY bit Parallel | Ripple carry adder: aa BS Cs Aa Ba G Ay ® Gg he 8 Gee a ie E 1 © Cy 3 le 5 I ! Be N—bit parallel Ripple carry adder? \ ~~ Towel delay = nTp, = Ant, 5 depends on interna civeurt of FA Tea = Propagation delay of each full adder Tea = 214 where, Tq = hate delay = Tetal delay, Te, = Un-OTe + mat( te, Te) Te — Prop delay of carry tn FA in FA Ty = Prop delay of cum in should wait = Tn on bit parallel adder, every ctaqe tor +he carry tyvom previous stage hence Tp = Un-i) Te + Max C Tei Te) OCAIINEU WILT LalllocaEx :- To =3one | Tem 20ne “pat Bons are ees +=0 \ 40 4 bs ¢ Ca Ag 8 1 Ay Gq he Bo \ %™ Boos Co=0 i" La | PAS FAD Fohy EAL s: Si Ss oy a Gons a Yont ‘ Dont So ¥ 4 Fons v 4 ton =n il 2 Tetal delay, tT = Ione lor) The (4-1) (20) + max (30,20) = 60430 = WOME He N-bit parallel adder > It is a N-bit Full adder lor) CN-0 eA + UA Chor us -B) Since 4% ©Ae ater N-bIE parallel= (N= (a HAD + UA adder =lan-\) HA > We can Implement e-bit paralle| adder by cascading two 4 bit parallel addere > Since carry fs propagated Uke a ripple from one adder +v other, It It also called ac Rpple carry adder: OCAIINEU WILT LalllocaSince carry input in the present state 1s clepending on carry output from the previous state delay increases With Increatce th number of bits. We tan overcome this ditadvantaqe by uring L2ok ahead carry’ (oy)'Cayry took ahead adder? BZ the vipple carry adder Shown I+ In each FA sum requires Yonek carry requires 2ONs hy 6 Ay B “ Ao Bo ge “| \ & ‘1 2 1 By bo=O PAs PAs cy ts Se \ Se Determine -+the Ci) Total delay QD Addition rate W Ttme delay, Ty = (n-) Tet matlTe,Te) = (4-1) (20) + mar (42,20) = 6o440 =loons = 1 *S GD Addition rate = Novot additions per second ExT A addition takes OS See Q additions can be done In 4 see Here 4 addition takes (o78ee, tn 4 see, Lm, = ot Additionticec fom Addition rate = lot add (sec OCAINEU WILT Callloca&- A \6-bit ripple carr adder is realised using l6 i dental full adders(PA) af shown in -the Fiqure:the carry prop” -agation delay oft each FA jg [ans and the cum propagation delay of each FA ts 159%: The worst case 5 i delay (in ns) of this [e-bit adder will be j Ao Be al Aw Bq Mis Bis ls Cy i FA FA, |_--- FAW, So s ¢ Tes 15ne and Te = lane Total delay, Tr = (n-OTe 4 maa Te Tey Number of bite, n= IC = (6-1) (127) 4 mat (15 112) | | = Woy 15 = 19S NS 6. A hald adder is imple mented with xoR and AND gatet-A full adder is Implem ented with two halt adderc and one OR gate: The propagation delay of an KOR gate 1s twice that of an AwploR gate: The propagation delay et on ANdIOR gate Is wamicreseconds. A Y-bit ripple- carry binary adder Is implemented by using feur ful) adders: the total propagation time of this U-bit Ginarg adder is microseconds is cad VepRS G) SL cop aype Carla ope OCAIINIeEU WILT LalllocaDecign vt full adder HA hope Clearly, To of FA = WB HE T. of FA = HOPS Total delay, Tp = (4-1) Cure) a mad (4 8)4-9) = alte) = 1aape aA fu adder con be Implemented with hal adders and DR gates: A 4-bit paralle) full adder without an tntttal 4 e 4 carry requiret (ae halt-addert, 4~0R gates Cb) 3) bit parity checker ce) + halt adders, 4 OF gates we z halt adders, > OR qatts yu obit parallel ull adder: 3 FA 4 WA HOA = FHA + 3 OR v te aA atta RHA No eR qater qores 41OR +4 oe +4 OF OCAIINEU WILT Lallloca@& The ctreult shown tn the fiqure hac 4 bores cach ith described by PiQiR gnputs and outputs 2 wit Y= P@RQeR RO+PR+ OP —_— Output The cireult acts ar a la) 4-bit adder gqiving P+O SHu-bit subtract qiving P-8 W) Y—bit cubtracter giving 8-P {d) None Y= P@R@R = Sum of FA = DI of Fs Z= RQ+PR+RP = ABH ACHBC =A-B = Borrow of FS = P-8 Tt je 4 bit subtracter giving e-8 ae UNIVERSAL APPER] SUBTRACTOR!- | Adder: A+B | Cubtracttr :A-B = At 2's comp of ‘a! = A+i's tomp of ‘B44 OCAINEU WILT Lal loca™ Concider, sit > ot 8. All subtracter A- B= Ayes) FA B@o= & Ba ~ oath. FAd B@4=8 So oS ctr l=05 Az Ara Ay Ao => ave G) Ba Bp & B& ctrl=4 then, 4A tn positt on Aa Ap Ay Ao => A4B44 . Ato's comp Bh wh Be of & = A-B the blanks .Tn the two $i4 full adder! unit chown In Figs: when the switch ic th - aor attng ~ ~~ _ arithmetic. Bo Bu Ay As es eS Ain Ben 2 ble Full adder cum OCAIINEU WILT Cdl locaPosition 4: Cin = 0 Position Pocition a siqnitles subtraction using 9's comp arith metic Qs Consider the ALY Shown below TH the operands are in ave complement reprecentation which of +the following operations can be pertermed by cultably setting the control Lineo kK and © only ct and — denote additien) and subtraction ‘vecpectively) ? car A+B, and A-B but not A+) We) AtB, and At, but not A-B& (e) A+B, but not A-B, Or Aty Lat ate, A-B and A+) tT =t and Co=lj} A-B+y = A-B (2's comp) k=0 and Co= 0} AtBI Add =o and C='} Add ga OCAIINEU WILT Lallloca“Figure 2 chowe a U-bit ripple carry adder realited Bing +ull adders and figure 2 shows the circult of a Full -adder (FA). The propagation delay of the KOR,;AND and oR gate in Hqure DZ are aone,tSns and fons, Fespectively: Assume all the Inputs to the Y-bit adder are Initially retet to b. At +t-0,the inputs +o the u-bLit adder are changed ts FeRyko= 1100, Ya2%%o~ 0100 and %w=loThe cutpuk of the yipple carr dey willl be stable at tlin ns) = PP 4 ad Y, Ka YX YX do Zn +t 2 5 = =4 Sol. 1 0; 0 le 2. ' ', 0 6 1 ° tSoo ° f ‘ j | vt 0 Oo, 9 = | ee Tade pendent —e | neglect Independent of cHirct two addittonePom ely euit given, Sp- KX @y@z Ena) = Cx@y)z4¥y Let ut tind worst care delay for sumicavry of Full adder | Scaliieu Witt Galloca~ Tetal delay tor qiven addition = SOns o 31 \ ° ° t Se G0 & Consider 1 ' © ° A= lons Mons toto \ o=p-""* neglect delay 1° adder realised Q-Figure 4 Shows a 4-bit ripple carry using Full addevs and fiqure T shows the cireult of a full gader Cea) The propagation deloy of the KOR; AND | + sn and tons. AiUne and oR qatts Yn Raure T are Wne, Iso ia LAE all inpues te 4 bit adder are Initially reset to? + =o, Inpute are appited be termine worst case deloy, =o, Fiqures ore mentioned In above question, 20n @) I8Ons tb) 1eS ns cey uons Cay l2ons (ey fasns OCAIINEU WILT LalllocaOCAIINEU WILT LalllocaPE BCD ADDER! An adder which’ can add two BCD numbers and Qqivee recult aleo In Ben using binary adder. BoD range :- © to 4 Range o+ A+R: OF bo G+tq Oo +o 18 T+ vesuit 0-94 ~s no change Ce, BCD retult= Binary retult Tif result >‘a', Eas 10l0 ~ Binary = | e000 : BeD | cy oa a leolo- Binary — Concider, 1 0000 vy Doe > 10 V0 ty tool. colle * Oh tm TT ——- — Hence, 6D recult -Binary result=6 Cres) if recult > oo or Bcd result = Binary result + 6 => To ged ia valid sep result from addition of two need to Bcd numbers using a binary adder, we perform -following , W at re:ult -q — No need +o change retult < eo? toa da UD af resale 74 V-e-) Sum?>9 tov) cy=t’? ,ad + Binary vetult: ocanneu Witt CalttstaBinary result BCD refute | | i | Cy Sa Sp Sy Se Cy Sa & 8 ° ° ° ° o ° ° oD ° ° ° oo \ ° © oo 4 same | as : . i ” binary | ° \ ° ° 1 ° \ oO oO \ Result 4 ts tos ee oe sum7q | ° Yoo \y o4 © © o 4 Low o wad ° 1 fi ‘ \ vb to 4 1 = ol “4 ' ° ° ° ce 1to \ ° ° ° \ o ttt \ ° ° 1 ° 1 9 0 o ‘ toy rt ea? tb’ to 1@ > 1 © © 1 oe @y 11.90 gt to 1 1 8 oo e,? — when we add ‘te, cy fs always 4 In the BO result: => Let us find the cipression for tinal carry of the result: sum 79 2 Zio, 12,13, fii aoe lilac Cie ea (415), OCAIINEU WILT LalllocaCie SEN oo e' om to Ae Sum7d t $2624 S25) °} Coy? cya t ty |G r Py ll ‘ r x Cout = S3Sa483Sir%y a rfo [| Pa Sah 485%) Ay Av At ho B, Bp 8 Bo <— Bcd inpute bit Parallel Adder oes . ell I Y-wit Parallel Adder Sg Sy S So BCD result Fat BCD Adder OCAIINEU WILT LalllocaUO Recult <4! Resulte <9 9) Cy result 77+ Az Ar Al Ay 63 BA Bo 4 bit paraliel adder— Cy Sa $2 $4 Se 4 bit parallel adder $3 $2 $, Ss Ay ALAl As By 82% a. LU 4 bit parallel adderfr—_— Co =o 6 4 Sg Seo Sr } poo $3 $7 S\'se 4 bit parallel adder $3 Sp SUS | —_——— BCD retult OCAIINEU WILT Lallloca — eco pls ComeSE CARRY Look AHEAD ADDER !- — Consider, « in 9 ' Gon 8 Cn 6 | A ° ° A of A i 4 8 ° © 8 1 1 B , ' oo ° o 4 ta _ _ ti—t Qe Oi Cout Cout < Cout = Ce, NO cavry Cout = Cin OCH c te Propagate carry rGencrat 4 4 ABIAB=A@QH AB Cout = PeCin 4 Gi Cea pe Gir PCE = ALBL 4 (AL @BIICL = ACBL (CALA BO CO CAttEr minimisation by 5 Here, k-map) Generate carry, Ge = AC Pi = ACO Cov) AL+Be +e Propagate carry, HKU-Bit carry look ahead adder! GES ALEC 5 PE= AT OBL Ses AT@eBLOeE = NOC Chay = GOR PEE Cy = Got Pole Cae GPL = G+ Py C40 + Pole) Girt Py Go + PrP ole OCAIINEU WILT Lal llocaSa= G4 Pats = Ga Paty t Pah Go 4 Pa PiPole CH= Ga tea ce = G2 + Pae a 382 + Pa Po Gy + Ps P2 Pi Ge + Pa PoP) Polo circu y byt carey Qenerater $3 tq SS 2+q Total delay for sum, ts= 4t4 cary, te=3tq _> The above delay if same irrespective of number of bits. consider a y-bit (N-bit) carry Look ahead adder.In > carr enerator civcuit, 4q OCAIINEU WILT LalllocaNo-vo-+ AND qates= 14+ a4 344 = Ip v alle s Up ~IAR 42 4-0 4N 2 NIN 4D | a MO'Sf OR gates=4oNn ’ | 1 ' ' | Rip to S Vp gates &- A carry Look ahead odder fs frequently used for addition pecause jt Lets faster (by Ts more accurate CO Veer Fewer gates Cd) Cocts Lece Carvy look ahead adder hac relatively less propagation delay hence lt te facter- &. Ascertion A. Look ahead carry adders are fast tn operation Reason Rs Paralle) cavry generation Improves the speed ot addition, Loot ahead carry adder vs Ffatttr v-e) Afcertion ts true and the reason behind Us the parallel carry generation. ‘KR is true and 'R per-tectty explains it 6. rn a carry took ahead adder, the carry qenerate function a and Ne carr propagate function Py for Cnpuke AuBe are given by oe GL PRC ce ts the Inpue see Pt OC and Ceyy= Giri where ie carry: Consider the +two-Levet Loqte Implementation of the look-ahead carry generator. Accume that fo and a OCAIINEU WILT Lalllocaar © available tor the carry generator circuit and th tit AND and OR qgattee can have any no-vef inputs. THE humber of AND gates and OR gates needed +o implem ent the Look ahead Carry generator for a u-bit adder with §3,6,, Se and Cy at its output are recpectively A+ G13 BM Ot C1 G4 pb. 19,5 Given gates can have any number of Inputs and Ne=4 Number of AND gates = Wnad - AUS ~ 6 Number of OR qater =N=4 @.A ubit carry-Look ahead adder, whith adds two u-bit numbers , ts desiqned using AND OR, Not; NAND, NOR gates only Assuming that all the inputs are available uncemplemented Form and dey Un both complemented ana of each gate ts one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR Logie AG time unite 8.6 time unite c. 0 time units p- la time units A@e = AB4A 8 - (At8) (AFB) = AB (a+8) . =n = 1. => WW atq 24 OCAIMEU WILT Cal llocaTetal delay = 6+4 = 6 time units ®-A Y-bit cavry (ook ahead adder, which adds two 4bit Mumbers, CS designed using AND, oR, NOT,NANP,NOR gaees only: Assuming that all the Inputs are available In both complement and uncomplemented form and delay of each gqatt fs one time unity what ts the everall minimum ot the addertAcume that possible propagation delay implemented using two-level carry network hat been ANP-oR Logic? A> 4 time units B. 6 time units Us time units bp. # time units Cony e CAce Bice + Ar Be = (ac @Bid ce +A be PL = ACH+BE lord AC OB minimum propagation detay Poe Act Be + qives OCAIINEU WILT Lalllocamultiplied: numbers OCAIINEU WILT LalllocaAl Ae B, Be Ye Y 1 Yo ° ° ° o ° ° ° o oe 2 f oo oO © ' ° \ ' o 110 ' ' \ 1 1 eo eo 1 > Y3) 42, VisVo can be expresced in -berme ot minterme ond can be solved to cop uting F-map- @. Consider the ctreuit In taure which hae a four SIE binary number babebibe oc input and a five bit binary output: The clreult implements number dydgdadide at by br by be u-bit Co Couk — Linary addev ay da da dy de lo Binary te Hex convertion Ww) Binary +o BCD conversion ce Binary +e QrO4 code conversion radix -l2 Conversion 4) Binary + Hy} Output of AND gotene It (nput:o to t same ., Result OCAIINEU WILT LalllocaT+ performe Binary +o vadli-12 conversion. Q-To add -+ro0 mbit numbers, the required number of holt adders ts Ca ams Cb) a™ Coamt) Cd) am mbit addition tCm-F A + tA 2 alm ta 4] MA =lam-') HA implemented &-A a-bit binary muttiplier ca” be using Wa (nputs AND only Leda input xome and 4 Inpue ANP qnase only CO) Two a impue Noks and one XNoR gate ) KOR qotes and chitt reqitters Ay Ao . Dt requires & inpa By be qui r Be Ao Be xoR's and 4 input AND AaBy Ane gates (eince it requires tL cf halt adders). OCAIINEU WILT LalllocaLoGicAL c£RCLITS \-bit comparator !- A>?B AaB A=B a ® x y z ° ° ° © \ * 7 ° \ ° ' © r ° © \ \ ° 1 i X=AB Y= Re J athe ebycult shown in the -Hqure ve AB D— 5 CMAN adder ctycule Cb) Subtractor cireuft OCAIINEU WILT LalllocaLSA cComporater clr cule CMA Parity qenerater ctycult a a AB! APB 5 AD ye ae R Aa—Ace sat is a comparator et veuit: “kK Q-bit comparator !- > Let R= AlAs and B-6,B. be two abit Xp ALB = ABE Yoo: Aveee = ALBE Vir ay=8i > ATORE () A>Bi- (ay>ei) er [Careep 2 e789) we ky be Ke WwW AeB! 5 CA, ee) of [Caria 8 & UAe < Be) ye YY +2 to = 8) and (Ao= 8c) binary number OCAIINEU WILT Lallloca3k Method -21- A B A, Ao B, By x yo @ ° o G ° ° e ° sr REN AS Are: x = Sm (4,8,4, 12, 18,14) 2 © times stat Reet Y es Smli243,6,9 "26 TY Ss m(0,5,10,15) > 4 Hees > " B ” " OCAINEU WILT Lallloca— ¥%1%,% Can be solved uring F-moP and can Ahen be implemented- HK SWAT CHING CLRCUITS: We MULTIPLE XER* = G+ fs a combinational cipycutt which contains many inputs and single output: — Basted on the selection input it con select any one o+ the many Inputs and -transters +o the output > MUX can be uted +o Implement Logic -unctions. nN selection n cel Up Up Dse of mMox Cexample): 6 A Selected Source MP2 player 5 Docking station 1 Laptop sound cat Digttal cateltte > | ba o 0 MP2 8 (Laptop ° Satellite Digital cable Tv 1 ot Cable TV OCAIINEU WILT LalllocaQO Time Division Multiplering:- ¢ felefe le e [4 | ° HQ MUR! I.—o as) y Mvx a Se UTE MUX te o y So o De Ty 2 Te 1 og, Bsetit $/E.T2 + SSeTa ocdiINeu Will UarocaAEMUX wlth delay :- B.A ate 4 digital multiplexer having a svaftching delay cof tpe fe Connected a shown in Fig: the outpue cf the multiplerer fe tield +o THe own gelect input s The Ppute which gets selected when s=o [8 tied tot and the tnput that get! celected when s-4 Ie Hed to O- The output Vo. will be LAr Oo cer S27 Pulse train et Ftrequenty Os Mir (>) Pulse train of frequency 4-0 MHz Output of MUX, Yeo SI, 484) diven, toand =e a Ys B44 $0 =8 Mot ( Met ea —o - at outpar pulse train is of frequency os Ms of MOY. OCAIINEU WILT Lallloca“JAS UL ——= ies ie OO 7 Time period of v, = T= 2HS a = OSMHT a axle & So Fer the clreurt chown tn Raure,the delays of Nog gates, multiplerer and inverters are ans,usns and las respectively. + all the impute Pia,Rs and Tare applied at the came time instant, the maaimum prepsaction delaylin ns) of the circuit Us UATE NS (bans te) Sns (dy ons t= Ine OCAIINEU WILT Lalllocaa Matimum delay = max (sc) =G6n8 It each MvXx clyeult works Ve having inte propagation delay then the as LaAstoble multvibyater LP Bletable multivibyator Lomonostakle multivibyate — Cd) none anverter 1 Laverter Buffer Daverter Dover ter OCAIINEU WILT LalllocaNoof Inverters, m= 4 Urey even It lt a Bistable multivibrater. Q. The output ¥ of a Arbit comparater ts Legie 4 whenever the a-bit Input A ls greater than “the a-bit Input B-The number vt combinations for which the logic output fe 4,04 La 4 Le) 6 le) ¢ td) lo Ba a a-bit comparator: A7B 36 AcB te A=B: 4 8. The propagation delays ef the KOR gate, AND gate and multtipleter (Mvx) tn the circuit Shown in the Aiqure are Ung, 2ns and ins retpectively P & i Se gf all the inputs P)&,R,S and T are applied simultane— -ousty and held constant, the maaimum propagatton delay ofthe circuit cs uwEns a. ans 3. tne ye ons OCAIINEU WILT LalllocaW let Tao r Y ens delay of the clreult ~ 6ne Maaimum propagation Be MUX as a universal ate: = a a WDAND gote using 2:1 MUX: Me thod -Z !- Y= AB = ° 8 Output of MUX Y= ST.+6-T) ay Y AB Substitute, S=A ;Te=t) Gob 6 ] MOR Ye A.ota-p=ae s=A Sta y To=ty a= 8 OCAIINEU WILT LalllocaMethod -a2: pa AOR gate using Method A*- Ail MUX!- Y= Ate Output of MUK! Y= $,Tot SoTy Subctitute Se =A then Yo AD tact “chen, 2 AtKR yo SE46-3) > “tA ty ‘LtA- 0 > cee) Dap edo S=A OCAINEU WILT Lallloua*” NOR gate using att mor! Method-1:- Y= ATE = AB Y= Sa. 4sq, Substitute s=4, VE Ac. 4A-9, two tl MUX tence NOR gate implementation requires Similarly NANP, €X-0R, EX-NOKR can be Jen p lemnerrted Gate Noof att MUX required ANDIOR, NOT a NAND, NoR, EX-oR, 2 EX-NoR —> Te implement any & variable -unction|qate using mvx simply copy tvuth table olp at lp o-f mux. Ex: EK-OR F=AB+AB OCAIINEU WILT LalllocaOCAIINEU WILT LalllocaQe’ + The “Boolean function realised by the Logie epreuit chown) cs 6 b= FS enloy 3) S191) = Sm (03,5, % 1 Sle | = Sen ( 24,5, IS) = Ben 2 3,8 47819115) Sutpus of MBX, F= ABC+ABD+ ABC 4AB CD Convert the above to canonical form +o qet function: 3 f= Em (2) aS 41895) fa So (243 STB AN) OCAIINEU WILT LalllocaB:For the clreult shown in the following fiqure 1te“72 are s are inputs to the 4/1 multipleter, e(mMeB) and Control bits. Find the minimised expression of output % ¢ >I 2 2 ° Polo | - al? rr re OCAIINEU WILT Lallloca. are Th the Tre circuit shown in the Hqure, So and So Select linet and ¥%q aNd Xe are Input tines: Se and Xe are Lsee. The output Y ts Ns Indeterminate Be AaB ©: R@B O- = UX@sB) + c (a @B) At selection input a, (nput of oR gate ts Floating 75° it ts treated ac 4 Cn TTL Logic. Output; Y= Bay BA= BOA idered at S, cannot be zero hence, ¥o-K3 are sonsicere dont cares: ‘ ‘ : g- jpleter cs Q:A combinational clreuit uring & Y crailtlp ‘ shown in the figure. the minimised expression for the output (2) es eo Po OCAIINEU WILT Lallloca() cl(AAB) (bc (A+e) GK) TAAB Cay C+aw = Output eaprection, 2 = ABLE MS8&:A MOX Circulyt thown In -the Agure below imple- ~ments a Logie function Fi. The correct expression For A rs output of 4°F Mux, Fo = S T.48T) Fo = YUN 4x = KU EY = KOY Output of and mox, F) = S2+ST A= SO = 5O2= KOYVYO2 ——. Y@x*@Z or X@Y)@z " OCAIINEU WILT LalllocaNOTE :- 2 A@A@e =A@S)OC ——p- ~ A@B ®, — 4 = A@8Ge + AOBOC © + A@2@c te used te BA 4X1 multipleder with two celect Lines r variablec realise a Boolean +unction € having Four Boolean 6, denote -ehe teack WIV ;2 and W at shown below:S. ond Cigniticant bit (iss) and moet significant bie cmsa) of the celectoy Lines of the Multiple% recpectively, Te; Ti Te Ze, are input lines of the multiplexer: zw!—a, zw——la, Wot € movx ° a, 2'4w A. 4 Se x Y The canonical cum of product representation oft Fie b EO yt Ww) = SMC TUS) ar PUry tw = = po Fo, 1 (tH 15) ee tr) SS (2st) 3- CEO pwd = Se COU Be HT) ‘ ' OCAIINEU WILT Lalllocaxy to ° ° 1 ° ZW & 4 u ‘9 F = Smo.) 34,14) a The Boolean eapretsion for the output t of the mult- -ipleter Shown below ce Cay PEAR & —>s - KT POa@R z * Ce) PHOLR R Gd) P4BeR P58 output of mux, += FB & = (PH T+Pones (FAHPHIE =~ (res) a+ (r@aye = C@aye + (POaR at = @@a@er Q. Consider the following multiplerer where Lo ,T, Ty) Te are four data tnput Lines selected by two address Une combinations ts the output AjAc= 00, ol, 10," respectively and of +the maultpleter. EN iS enable Input: OCAIINEU WILT LalllocaTe function # (x,y ,2) ts EF aye Ce ayte Address Lines, Ay Neo z ry \ 2 \ oo | © oo 2} mt © te | © ORE RYT AeA Hy per TEEE convention Is shown in Aqure ~) '% three Logie inputs the multiplerer volft wo Smo, tad) GS Em C315 16/%) Multtpleter shown be E(x, yz) = 2 implemented by the above elrcuit (444 (d)None of the Above =v 2 y2 Output oe. Ig =Y=0 o\ 93-7 =\ ~ “ob te x Enzo olp is VN i =x diea bled ta Figure -2(+he came ae fed with AiB and ¢ ag chown, The output of (by) S mo, 315) 4) (4) Sm(1,2,516) OCAIINEU WILT Lallloca(0 ret A of] ° 21@ * ils lolole ° A Aol Q. The Logic -funetion Umplemented by Following qt MUK Us x 7s. y 74% z x —s o —{73 (mca) x y (vse) OCAIINEU WILT LalllocaOutput of MUN -ESeTs HE SoT, +5) Seta + S88 FS osl VoRt KYY Ht XV K 4 KYO = * + x < | 1 \ ° ben ISne pq. 1 BO as tt \ \ | ' ee ee ennery 3B Oe toate % 0 eees rer one im \sne YO WOns Os 1 4 SAG Yas s Time taken=4ons OCAIINEU WILT LalllocaDecimal value OCAIINEU WILT LalllocaHow to tmplement @ function using MUX! 8: Tmplement the following functions using 4*! MOK: FA Bied= S mlonyei FAB CdS KBE ARC 4 ABCHABE = ABLE +4 ABC ABC = ABLABCH+ABC = AB AAR O+ ABC HABC con ort to 4 m4 y Tp By Jp f= Smo 15,4) Sy $e a 8 Method-a: AB ooo, to Wt Implementation table :- c 1 {O12 16 lq to ee &. Implement the Followtag functions using Y!l Mok: FLA B10) = S mlo4,6,4) # = Sloe) OCAINEU WILT LalllocaSs Ang 2 Variable function can be imple mented “SIng a 411 mux, only Some 2 variable functions can be Implemented. NBL ang 2 variable and 2 variable functions €4° be emplemented using tl MUX and a inverter. Note:- With @ ars) MUX, we can implement any n-variable and some tn40 variable functions While using @ at Mox and an inverter. all Sn? Variable and ‘(n+)’ variable -functions can be implemented BF (AIBC) = Bm lo,4,6,4) by taking Bc and Ae as Selection Lines CO Bic: Bc 1 * oo Of 1b wy ° A of/@®]! 2}32 A kK .[@ s |e @ A too AOA QD Arete OCAIINEU WILT LalllocaNote:- It a +tunetion ic given in -the Por -torm, convert Tt Into SOP orm and apply the same procedure . > To tmplement any ‘3 -varlable’ function using e: Mox S°PY truth table output at the To Input of MUK, Implement FA using of mux Mux determine the Number yequlred Lay a Me 2 Ce) 3 Cay For a full adder, Sum = Sz m(1,a,4,4) Carry = Cy = Sm (3,816,4) Since we have +o implement two different -functions, we require 29 MUKe. B-Implement + laybyc,a)= ZS lol, 4/5,414 10,18, 15) using 3. MDbK and a: muy. Dsing &:l mMux:- abe a \e00 001 o10 otf too 10! Vio ay 2 0/@/]2 |@Je :|@}@ «| dy [o * te @l@ |" Je @ | ' © to 4d da 8 g s eo ajoaya > OCAINEU WILT Lalllocac T+P Spach Tdsep =c@p = cao DON'T CARE CONDITION: A If don't cares are qiven then don't care are considered only tt they are useful for eliminating et+terna) hardware (qates) otherwise they are neqlected. €2: + laybic) = S ml2,5) + 403/446) ab c Cow 4 Lv Pre-ferrable OCAIINEU WILT LalllocaHK AMPLEMENTATZON OF Hager oppeR muy usENa Lowem ORDER muxi- Tmplement 4.1 mux using > Truth table of uit Mux i Ss Se y o e x r. ° * ¥ zt, —\ ' o de voy a oo ° Ts —> let us concider by taking Implement Sy MUX using No-of arr Mox an Mv x: + pes Se ay Se an example of S)So=lo Y= ay Muys requived =* OCAIINEU WILT LalllocaG4 oe ataty {+aey ea a ¥ Novot a: mox required te implement arit Mv are ang %—4° ay ay \ Sa se Implement ft Mvx using 4:l MU &!- No-ot Ys; MUX vequired =3 # ~& a 4st Mor a 4 aa t a ut Mow lor 4 BU MLK for last MoxX te a combinational cireuit which contains single input and multiple outputs. Based on the selection Lines, Input can be given +9 ony one of the many outputs. wy br) “lp 2" olp He nm cel lines => Since P-Mve has only one inputs tt ie not uced for Implementing logic -tunctions. ae La DMUK I s Ss oY Ye £ 1 ¥, Yo ° ° x 32 x y \ iL ° my s OCAIINEU WILT LalllocaS$ Se Ye oN I, My oo 2 o 0 6 e ' ° To 06 \ ° ° o ft © ‘ ' ° ° o © Sy Ss. "| % Implementation ef Higher order D-mvx using Lower order p-MUKi- Implement (4 DMLK ating 12 PMUXK! e510 ih — i! Sy Se 4 é yeot 4 \ Yod ne \ 1 Yg= OCAIINEU WILT Lallloca>For example, consider S$\So= lo tite ty +t is “4 Yad << Wwase tite ae te ig we Te (6 41 . ay masc 2% ig 2B + Bt = 34 lor) ac 1a w 8 g Ba244 4) — t+ 4 pmux 6 enough for First stage pe DECODER !- decoder is a combinational clreuit which contatae many inputs and many outputs. Gt jt uced for code conversion lite binary te octal, decimal ete, ak ENCODER :- A combinational circuit which tontaing many Inputs and many outputs-dt ye uted fer code qeneration (tke decimal te binard; hexa ts binary etc. OO Ocdlileu willl GalllocaPIR pEcopER! A | A 224 DECODER - then D-MUK become a LOEn >It 8,80 PAIS and decoder: tnternal structure of decoder is same ag ->since the Decoder ic aleo called as 2:4 DMUX, p-Mvx, a4 OCAIINEU WILT Lallloca14 &. tenplement halt adder and half syptractor using # P~mox? For a halt adder; = A@b= Sml,2) Cy=ABR= S m(2) For halt cubtracter, D=A@R= 3S m(1,2) Bo=AB= Sm) en =a @ Determine nowt 2:¢ decoders Lok qgatee required tv \mplement full adder! Lay tet Ger yr cep ay ® Cd) Buh Sum! Se Smnlsy2y4,9) Covryity= S on (3/516) B18 Bacoder EN=4 OCAIINEU WILT LalllocaOCAIINEU WILT Lalllocav SInq active Low (Matems) ! FAI Bic) = S nt, 213, %) = Wm (044,516) =m UnR 1319) {> aT M(0,4;516) = ° — Te turn LED on, | cutput should be ey ; a and this conta uration is eq Med “common cathode’ since all cathodes of dlodec are tied together. — Fer LED 40 ON, olp | | should be ‘0? hence | In ¢uch cate active | Zr Ow output decodere arg | ured Configuretion it Rk called“common anode”? 4+Vec OCAIINEU WILT Lallloca*Inplement 31% Decoder ucing 2:4 Decoder! , B2@ ay i € 3 i at tee, 3B at d i : : , 4 decoders 4 - in —_ 2 324 decorderc 21 112 decoder / Cor) ‘ Saverter for first { ; sta CH Using aty pecoders only! “ A Bc o omy oy YY, boo oy Voy oy oo Gy ° bY Vo 8 Ye roy Ya (oD Vsing —2s4 KR1E® BDecoders:- EN=4 OCAIINEU WILT Cdl llocaMW) Being A 6 Oo ° ° ° Oo a \ ° ° \ \ Note: Ute erase ease an Inverter and at4 decoder: c | oY. y, | oN \ Ys a oy 1 Ye oY ' Ya, 13% 2:3 Decoders (on aig pecoder& 2 24 Decoder for first stage 22 = high impedance (o-¢) OCAIINEU WILT LalllocaQs The functionally implemented by the civeuit below vs e _——= | 4 —_____——-+} s i any Decoder fo. Enable=4t (2) 2 te 4+ Multipleter Us 4 to 4% Multiplerer oF +o 4 Multi pleter @)6 to 4 Multiplerer ¢ a Rg s ary Decoder Enable=4 o 0 PF fe Ie Ve cim\lar to 4 to 4 o 1 8 yy multipleder. \ ° & Ty \ 1 os Te OCAIINEU WILT Lallloca8: The Following susitching functione are +r be implemented 4S\ng a decoder Fp = Sim (1 hit, &, 10,14) Fy = Sm (aisyay nd Fa Sm (a48)6 ,9) The minimum contHguration of the decoder should be (a) a-te-4 Line (by B-to-8 Une ou te -16) line Ud) 5 —te-32 Une = Sm(1,a,4, 47 10,14) Mas min term = '4 T+ rvequives min 4 variable Stenilarly, £22 Ss en(aisa,/N) O41 Var var ty2 Sm(ay4siea) >? since there are minimum 4 variables, a 4 ao (6 Une decoder i¢ needed: obtain many Q With which decoder (t Is postible + code conversions? (a> @ Line te 4 Line (b) 3 Une to & Line ceyNot possible with any decoder 4 tine te le Une decoder Binary + Ben, HEx, etc Can be done using Y-16 line decoder: OCAIINEU WILT LalllocaQs Which one ot the following statements ts Net Correct? An ¢ Input MUX can be used +o implement any 4 | variable function, BLA 3 Une to @ Line DEMUK can be uted te implenent | any 4 yariakle Function. i LS SY input Mux can be built using ole ¢@ inpuk | MUXs- | BFA 6 Une te 64 Line DEMUX can be built using nine 3 Line to & Line DE-MOXs, 64) MUX — e@:1 MLK S44. % 24 e 8 eo4y = S 6w4Y PEMLX — 32°% DEMUY S4 +i =9 B+\ << 8 Input M44 tA vt AIT Gg variable tunctton: Burt 3:8 PEMLX cannot be used to Implement any 4U variable -function. A.Consider the Following statements: A Urle decoder can be constructed (with enable input) by: I bstng four a4 decoder(each with ag enable tgput) only g-using -five ary decoderc( each with an enable Input) only te) on) gusting two 2:@ decoderc (each with an enable (np Ng uk) Uiing two 3:& decoders (each with an enable tnput) ard 4) : an Inverter which et the statements given above jslare correck 1 OCAIINEU WILT LalllocaOCAIINEU WILT LalllocaTruth table: En da 46 35 TY 8% HQ Bi FO yD YL Yo 7 x x ox x x x x x 0 vo o lez BR ' © © © %© 0 © oo 1 © © 2» ' ° ° 0 «© © oo 1 80 © © 1 ‘ o 5 of} ° \ o oO o too ' ° ° ° ° \ oo © o It \ 6 oo Lo. & & @ 10 oO ‘ 2 0 4 0 © 8 9 © = ! ° 1 6 0 © © © 8 roe ‘ 1 ° ° 0 o 0 8 © ‘ vt V2 = Ty 45 +34 15 Y= So45,4 5, +25 Yo = 4 Ta4 W647, oy EN Ty Y2 (ov) —- Se en Ty ay EN y T, bor) Fe En Ty EN 4 Yo ~ _-\ (on Ta a3 Bs EN 7 OCAIINEU WILT Lalllocaay. ° Ved, z, ° | a = a, —| x, 3e as } 2a fy Ba t > Tf sys | 3 ' yy ' XY \ \ Be ts Ss Be x te I= a, l= a5 = | — IF more +han one input is 4 at a time, Normal encoder wilt not work: >We can overcome thi¢ disadvantage by usleg priority encoder: ~ Ta priority enceder, If more than 4 ilp=4 ata time Tt will consider only high Priority input: We EKS Priority Encoder: Highest g — 4 L— y) Lease 7 —p priort m1 EN ~ OCAIINEU WILT Lallloca a c Ts —-> t— yo 4 2 Yo 2 1Mea Pr) En a> ° x ' ° ‘ v ' ° ‘ ° \ ° i ° \ ° Highert 3,._ Sy: 1,— ority Encoder! ae as 34 x x x °o ° ° © 0 o © © ° ° ° oo 1 ° t x 1 x x x x x 41g Priority Encoder Yi = OLR AX RX © 1oon 1000 © 101 Too; eo 11o orlroprag m3 Ja Ty) to ya “YO e x o ° ° lord z 4 % ° \ ° ° ° \ x o ° I x ok o 1° © ¥ ° t \ | | rook 1 9 © yx 1 oo | ¢ 7 ) x * root \ we) z eo oc oc 1 ° eo 0 | «eo Cn ' x Rk OK ' Vp = 001K, I KKK Colo 100° | OcdIINeU WILT UdllloVy = Sen (4y5 16, 4)89, 15) RY Som (9,3,8)9, 10, - 1 1S) as Oy TIX op ot Mt te SM \ 50 or (4 e Q. Consider the following combinational -unction block Involving four Boolean variaklet %,4,a,b where «a,b ave inputs and q is the output OCAIINEU WILT Lallloca# (4, 4, a,b) { ila te 4) yea; elke yah; } Which one of the following digital logic blocks is the most cuitable for implementing this function? UF Mox (be) D-MUX — (cy DECOBER = (p) EN COPER From given program, \ooxke= y output 2 & e y ¥=0; cutput—b gt te a MUX QIn the Following truth table Vea tt and only if the input (s valid SNPOTS OUTPUTS Do Py Dp PB Re ky o ° ° ° x * © ' ° ° ° ° o ot x \ ° ° ° ' ‘ x x \ ° @ 0° \ x xX \ 1 \ \ What function doet the truth +able represent? GH Priority encoder Cb) Decoder te Multipleter (d) Demultiple ker 1 OCAIINEU WILT LalllocaHere y th similar +o enable signal, then the truth table represents priority encoder R-0'M . al decoder > R:O-M it a combinational ctreuit whieh contains t: at the input stage and ok gates at +he outpu > Size of ROM: 2° & mM bits % Location: n-lnpute . | Decoder t 4 N-adder rm oR qatec — 4 FB memory endicates a'?xg Cres, 1994 boca tionc and each Location har capacity of & bits. OCAIINEU WILT Lalllocathe Follow: Punetions syiate Size a functions OCAIINEU WILT LalllocaA ® Awe A a Aime BiB Ys Ye ¥, Yo —s m+n bik Pv vv 1 0 © 1a» Bata Rom man one (EE A ROM sizes al ya = a ximeny %, 2, Lochtiont Each location hat (man) bits (W Hence +e implement B-bit binary multielfer, ROM eize: a?** X (B43) = ao %G LW To implement square of a Y-bit number a bit AKA os Ay Ao ve Ya Y Ye J] ° 1 ° ° oO ° x as 9 \ © 0 © 4 6 __| 2 3 \ oe o 4 Oo v \ x \ ° ° \ Y Ya Ye VY Ye t £ ROM size. ar xy Addrets Data ‘ oer a x aN fr n=4 bits, ROM cize = arx(axa) = ateg OCAIINEU WILT Lallloca— Consider cquave ef 2 bit number, Aras Ya e ° ° ° ' ° ‘ t Add recs Ya Ya YU Ys always ROM cize: ar xo - . tees, a x(an-a) — With N=4, Rom cize = at (a-a) = ators BI+ the Inputs Kakoxyre to the ROM Iq the Hqure ore & 4 2 | BED numbers ; then the outputs Vere BLD te decimal decoder s Do Dy -- -- Ba Py 1 f | ; [ : \ t Ye ' Ly, fina {—NWy——— Yo CA Gray code numbers cay a4 at BCD Numberc (e) Etcess 2 code numbert SF None of the above OCAIINEU WILT Lalllocaimal Decima 1 ee, number ° ° o v ° ' ° eo oF I * CS oe tio 5 o et 4 | 4 ° \ ° oy s o to 1 s rn * 1 to 4 z t \ \ ° 4 1 It \ q a St if clearly mot Bed conversjon lov) excess 3 since 0 tp S are same- Tt obeys 2 4 2) weight but Y and § are not complimentary pence Me te not @ 4 21 BCD IUMbere conversion, Q For the diode matria shown in the figure the output Y wlll be NW Ke A) eke ®) Xe STK Ke r TT = Db) Ke tha = Xe Ya yt Yo VN Anputs OCAIINEU WILT LalllocaLet ut actume x= 1 and ; ieee howe f X3 =1 1 ' Ye A Yue xeyay¥e 8° RK 3 Une +0 & Line decoder, with active low outputs tS used +o implement a 2 -variable Boolean Funetiont at Shown |n the Aqure. The simplitied form of Boolean Function €(A1B,¢) tmplemented tn Product of Sum? form will be 3x8 Decoder z—_ y ~T WAT (att) (4942) CHD CB) (FAR). (xe Ve D.UV 4%) Co) (av azy: Ce eye et) eave) Ce ey ae coy AVA Z)s CREED) © Cy nye ed O74 ®) f= eet, 3518) = wm (0, 2,414) = (x ayer) Cee¥ 42) Cea 42) (X49 42) OCAIINEU WILT Lallloca= Cx+2) (84942) 4942) Yu toy) wore oo of of Fe (nae) (RATED OD | 8- A 3 45 © decoder fs shorn below i Ga Gy, Yq. froble Siqnale AU the output Line of the chip will be high cohen all the tnputs 2,3 ca) Ave high, Geka. are low (Are high and G, is Low, Ga Is high ©) Ave Lows G, is low, Ga Is high (dy Are high; and &, is high, G2 & low | G@ 4 Pecoder = Te edable decoder, o 0 Disable B,=e and %~! ° \ En able When decoder It disabled,all | 19 pisable — output ines are high irrespective | 1 1 Disable of inputs OCAIINEU WILT Lalllocaa S94 ts detired +o qenerate the -follewing thre Bovlean +tunctions Fr = abet abe+be : Fa- abe pabeare i Fs= QOLeGxabe 1at b Gy using an oR gate array as chown in Aiqure where PL 42 Pe are the product terme in one or move of i the vartables a, a,b; ;0 and © f Write down -the term: Pe Per Pa (Ps, Py and Ps Pz %y Ps Sot" eX Fa Fa 42 =Gbabe = Putts OCAIINEU WILT Lallloca® Programmable Programmable o® Logic Devices (PLD): PLA Programmable Logic Array PAL’ Programmable Array loqle ROM PROM PAL PLA OR AND Fired Fired Prog Fired Axed Prog Proq froq OCAIINEU WILT Lallloca