Materials Today: Proceedings 79 (2023) 292–296

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Materials Today: Proceedings

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Tunnel field effect transistor device structures: A comprehensive review

Pradeep Kumar Kumawat, Shilpi Birla ⇑, Neha Singh
Department of ECE, Manipal University Jaipur, Jaipur 303007, India

a r t i c l e i n f o a b s t r a c t

Article history: Downscaling of metal oxide semiconductor field effect transistors (MOSFET) has resulted in increased
Available online 29 November 2022 short channel effects (SCEs), off-leakage current and subthreshold swing. At room temperature, the min-
imum subthreshold swing for MOSFETs is 60 mV/dec. So, MOSFET is not suitable for the deep submicron
Keywords: regime. A new device structure is being investigated to overcome the limitations of MOSFETs. The tunnel
Tunnel field effect transistor (TFET) field effect transistor is the new emerging device (TFET). TFETs are the most suitable candidate for low
Short channel effects (SCEs) power applications due to their superior performance, such as low power dissipation, low leakage cur-
Subthreshold swing (SS)
rent, and subthreshold swing (SS) less than 60 mV/dec. Ambipolar effect is the main cause of high Ioff cur-
Band-to-band tunneling (BTBT)
Ambipolar effects
rent, this effect can be reduced by the asymmetry in structure and varied doping in source and drain. As a
result, the Ioff current in the TFET may be reduced and the Ion/Ioff current ratio can be increased. TFET is a
simple p-i-n structure with reversed bias at the gate terminal and works on the principle of the band to
band tunneling (BTBT). The basic structure of TFET also suffers from low Ion current. However, with the
variation of physical parameters in structure, the Ion current can be improved. This paper reviews the
physical parameters of TFET and their impact as well as different structures of TFET like surface tunnel
transistors, p-i-n structure TFET, Junctionless TFET, and Dual gate TFETs, Heterojunction TFETs, Vertical
TFETs, PNPN TFET, and Nanowire TFET.
Copyright Ó 2023 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the International Confer-
ence on Startup ventures: Technology Developments and Future Strategies.

1. Introduction threshold voltage is also reduced and leakage current increase in

the transistor thus SCEs in a transistor is undesirable [3].
For high performance and low power consumption, CMOS has The basic structure of TFET suffers from low Ion current [4].
been used in the last few decades. However, as technology However, with the variation of physical parameters in structure,
advances and CMOS downscaling becomes more sophisticated, a the Ion current can be improved, and to get better performance
new emerging device known as TFET has been introduced which and results, many different techniques are used like material engi-
can replace CMOS. TFET shows better characteristics when com- neering and gate engineering. A band-to-band tunneling (BTBT)
pared to CMOS [1]. The electrical parameters can be improved by mechanism transports the charge carriers in TFETs. There are two
changing the physical parameters of the TFET.(See Fig. 1 Table 1). types of TFET based on the dominant charge carrier under the gate
To enhance the performance of metal oxide semiconductors and in the channel: i) n-type TFET and ii) P-type TFET. In this paper
the miniaturization of circuits, the size of the transistor is shrink- TFET structure and working discussed in section 2. Section 3
ing. Moore gave a law regarding the size of transistors [2]. To the explains the various types of TFETs and section 4 explains the
existence of Moore’s law, downscaling of CMOS is done at a large device parameters and their impacts like impact of source doping
scale. The main purpose of scaling is to reduce power, delay the cir- concentration, impact of gate dielectric, impact of body Thickness,
cuit, and to increase the number of transistors in a minimum area. impact of channel length and conclusion is in section 5.
However, downscaling of CMOS show some adverse effects also. As
the channel length decrease, the short channel effects (SCEs) 2. TFET structure and working
occurs and SCEs degrade the performance of the transistor, due
to SCEs, electrons drift characteristics limit in the channel, the 2.1. TFET structure

TFET structure is similar to a simple p-i-n diode structure with

⇑ Corresponding author. reverse biased at a gate terminal. Similar to MOSFET, TFET has

https://doi.org/10.1016/j.matpr.2022.11.203
2214-7853/Copyright Ó 2023 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the International Conference on Startup ventures: Technology Developments and Future
Strategies.
P. Kumar Kumawat, S. Birla and N. Singh Materials Today: Proceedings 79 (2023) 292–296

Fig. 1. A simple TFET biased structure (a) Biasing of n- TFET (b) Biasing of p- TFET [3].

Table 1
Impact of Body Thickness on Ion in DGTFET [23].

Body Thickness (Tsi) Impact on Ion Reason

Tsi = 5 nm Very low Volume of Si is limited at tunneling occur
Tsi less than 10 nm Almost linearly increase Strong dual gate coupling and Gate control
10 nm < Tsi less than 20 nm Increase at slower rate Gate coupling and gate control decrease
Tsi > 20 nm Start to decrease Weaker gate coupling and gate control

three terminals drain, gate, and source. The channel is placed temperature. The challenge is to have better on-state current
between the drain and source and the gate is mounted over the (Ion) with this simple structure of TFET. Thus, many changes in
channel, and isolated by a dielectric material. The most distinctive physical parameters have been done to the structure of the TFET
feature of TFET is its drain and source doping. In conventional to improve its performance of TFET and the type of TFET is defined
MOSFET the doping of Drain and Source is similar while in TFET as a result.
it is different in nature. The doping of drain and source are n-
type and p-type respectively or vice versa and the channel region
3.1. Surface tunnel transistor
is small doped or intrinsic. Under the gate, the dominant carrier
in the channel defines the type of TFET. If the dominant carriers
It was the first transistor based on tunneling. Fig. 2 shows a p-i-
are electrons in the channel, then it is n-TFET, and opposite to this
n structure in which the intrinsic region and gate are isolated with
If the dominant carriers are holes in the channel, then the TFET is
an insulator. The opposite nature of doping is used for drain and
p-type [3].
source. The transfer characteristics of this transistor do not exhibit
saturation [5,6].
2.2. Working of TFET

Band to Band tunneling is the working principle of TFET. The 3.2. P-I-N structured TFET
charge carriers leave the source by tunneling and enter into the
channel this mechanism is done by BTBT. According to BTBT, the The buried oxide (BOX) thin layer makes the p-i-n structure
charge carriers tunnel into the conduction band from the valence transistor different from the surface tunnel transistor shown in
band through the energy band gap or vice versa. At the condition Fig. 3. A silicon dioxide layer is grown on the intrinsic layer under
of off-state in an n-type TFET, the gate voltage is almost zero and the gate region, and after that, the drain and source region develop,
at this condition source region’s valance band lies below the chan- followed by the gate layer. In SOI TFET, the intrinsic region of Si is
nel’s conduction band and the valance band and conduction band used between source and drain to reduce leakage current and the
are misaligned, and BTBT is inhibited. however, it shows an extre- leakage path is blocked by a buried oxide layer [6].
mely low level of drain current. When the positive gate voltage
increases at a sufficient level above the zero volt, the density of 3.3. Junction less TFET
the charge carrier increase under the gate, and the conduction
band of the channel push down and get aligned with the valence In junction less-TFET (JL-TFET), the same material is used for the
band of the source as a result the electrons easily tunnel into con- channel, type, and concentration of doping are equal in source as
duction band through valance band. Due to positive bias at the well as in drain. The structure of JLTFET is shown in Fig. 4. The most
drain, these electrons are swept into the drain. commonly used material is Si and channel is highly doped. The
In p-type TFET at off-state condition, the gate voltage is almost Control gate and P-Gate are isolated and have different work func-
zero. At this condition valance band of the channel region lies tions. Usually, the control gate work function is comparatively less
below the conduction band of the source region, and BTBT is inhib-
ited and shows drain current at an extremely low level. when the
negative gate voltage increases at a sufficient level, the valance
band of the channel pushes up and gets aligned with the conduc-
tion band and the holes are injected into the channel by tunneling,
and these holes are swept to the drain region because the drain is
negative biased [3].

3. Types of TFET

A good steeper subthreshold swing is shown by the simple

structure of a TFET rather than a conventional MOSFET at room Fig. 2. Surface tunnel Transistor [5].

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Fig. 3. p-i-n structured TFET [6].

Fig. 5. Dual Gate TFET [9].

than the p-gate work function to get better Ion and subthreshold
swing [7].
3.7. PNPN structure TFET

3.4. Dual gate TFET The PNPN tunnel structure has a source pocket that is doped
with the opposite nature of the source doping shown in Fig. 8. Tun-
As the name, two gates are used in the structure of Dual gate neling is done under the gate at the junction of the source and the
TFET, one at the top and the second at the bottom along with fully depleted thin pocket layer, which results in tunneling width
two separated dielectric layers [8]. The dual gate TFET structure reduction and improves the tunneling rate. That improves the Ion
is shown in Fig. 5. The gate control can be improved by using and sub-threshold to the conventional design of TFET [12].
two or three gate materials with different metal work functions
that can be used at the top and bottom gates. A dual gate is used
3.8. Nanowire TFET
which results in better electrostatic control, low Ioff, high Ion, and
high Ion/Ioff [9].
The small size of a nanowire makes it suitable for continuously
shrinking transistors. In a nanowire TFET (NWTFET), the most
3.5. Heterojunction TFET important physical parameter is the diameter of the nanowire
[13]. The electrostatic control and current injection are balanced
In hetero-junction TFET, the material used in the source region by the diameter of the nanowire. The reduced diameter of the
differs from that used in the drain region. A heterojunction TFET is nanowire improves the transistor’s gate control, resulting in a
shown in Fig. 6, using InGaAs as drain and channel material and higher Ion and steeper subthreshold swing. Reduced nanowire
AlGaAs as source material. Usually, III-V compound semiconduc- diameter, on the other hand, increases quantum confinement
tors are used as source and drain materials to show better results. effects, resulting in a larger bandgap and lower Ion [14].
To improve Ion small direct gap material is used in the source and
to reduce Ioff wide gap material is used in the channel region and 4. Device parameters and their impact
drain region. Hetero-junction TFETs show optimum results in
terms of leakage current and subthreshold swing [6,10]. A small change in physical parameters has an impact on the
device characteristics. As a result, when designing the device, the
3.6. Vertical TFET device parameters should be set in a way that device performance
should improve. The effects of some TFET device parameters are
In vertical TFETs, the tunneling of the charge carrier occurs in discussed in this section.
the direction of vertical to the gate. The structure of vertical TFET
depicts in Fig. 7. Vertical tunnel field effect transistor is compara- 4.1. Impact of source doping concentration
tively better than lateral TFET. Vertical TFET shows a higher current
and steeper subthreshold swing. In lateral TFET, the tunneling is The source and the drain doping in TFET is different in nature
done at the edge of the gate, while in vertical TFET tunneling is and the charge carrier tunnel into the channel through the source
done under the gate region. Therefore, the current density in verti- at the source-channel junction. Therefore, the concentration of
cal TFET is higher than in lateral TFET. The main disadvantage of source doping impacts the tunneling rate, and the tunneling width.
lateral TFET is direct tunneling from source to drain when the gate Ion current is strongly dependent on the property of tunneling and
is scaled down beyond a critical length, which results in leakage very sensitive to source doping. However, if the doping concentra-
current is increased. In vertical TFET structures, parasitic tunneling tion of source and drain is equal and of opposite nature, TFET will
and lattice vibration are negligible [11]. show an ambipolar current, and an ambipolar current increases the

Fig. 4. Junctionless TFET [7].

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Fig. 6. Heterojunction TFET [10].

material between gate and channel or by reducing the gate dielec-

tric thickness [3,19]. To get a high drain current, it is required that
the gate dielectric thickness be reduced and high dielectric con-
stant (High-k) material be used [20–22]. However, gate dielectric
thickness cannot be reduced at a large scale. If the gate dielectric
thickness is reduced beyond a certain limit, direct tunneling
through the gate dielectric of the carrier will be imposed. It was
Fig. 7. Vertical TFET [11].
experimentally observed that if gate oxide thickness was reduced
from 4.5 nm to 3.5 nm, drain current would increase by 6 times
in an SOI-based TFET [16]. Thus, to get high drain current, the gate
dielectric thickness should be small and a high dielectric material
should be used.

4.3. Impact of body thickness

Two electrical parameters of TFET, known as drain current and

subthreshold swing, depend on body thickness. In a TFET, if silicon
Fig. 8. PNPN structure TFET [12]. body thickness increases, available silicon volume increases for
BTBT, and as a result, drain current increases. However, Gate con-
trol is also dependent on body thickness. Therefore, an increase in
off current in TFET [15]. To reduce ambipolar current, the doping of body thickness degrades the gate control and the drain current is
source should be slightly greater than drain. reduced. Maximum drain current necessitates optimal body
Experimental results show that Ion is increased by two times if thickness.
source doping is doubled [16]. With the increase in the concentra- For the 5 nm body thickness dual gate TFET (DGTFET), Ion cur-
tion of doping, tunnel barrier width decreases because the build in rent degrades because of very small body thickness and low Si vol-
field increases at the tunneling junction, and band narrowing ume at tunneling. As the increase in body thickness up to 10 nm,
increases with an increase in the concentration of source doping, the Si volume increases for BTBT. The resulting Ion increases almost
which results in a decrease in the energy band gap and a decrease linearly because the gate control at the centre of the thin Si layer is
the tunneling distance [17]. However, by arbitrarily raising the effectively reached. Further, as Si body thickness increases beyond
fermi level in the conduction band due to an increase in source 10 nm, gate-to-channel coupling gets weaker, but at a slower rate,
doping, the filtering effect on the fermi tail is reduced, and the sub- and up to 20 nm body thickness, Ion current increases, due to effec-
threshold swing is affected. The abrupt source doping concentra- tive gate-channel coupling. But beyond 20 nm Ion gets reduced
tion affects the tunneling current as well. The electric field at the because of weaker gate control [23].
source channel junction increases as the abruptness of doping If the body thickness is reduced, subthreshold swing improves
increases and it increase Ion. However, we can achieve maximum as well. and it is lower than 60 mV/dec using atomistic simulation
Ion and minimum subthreshold swing without the abruptness of in InAs TFET with single gate and dual-gate for body thicknesses of
source doping by adopting an optimum source doping and less than 4 nm and 7 nm respectively [24]. Thus, Ion current
source-gate overlap engineering [18]. increases with body thickness of TFET increase but gate control
To avoid an ambipolar effect, the source doping concentration decrease over channel and subthreshold swing also improves with
should be higher than the drain doping concentration. Since very body thickness decrease, so an optimum body thickness can be
high doping can affect the subthreshold swing, instead of increas- used to get good results.
ing source doping at a high level, use source pocket and it will also
increase Ion. 4.4. Impact of channel length

4.2. Impact of gate dielectric In TFET, the region under the gate and placed between the
source and drain is known as the channel. In comparison to MOS-
The gate and the channel of the TFET are isolated by a gate FETs, the impact of channel length does not affect Ion at a large
dielectric and it is placed under the gate. Strong coupling between scale in TFET. Tunneling depends on the electrical field and tunnel-
the gate and the channel results in a high drain current and effec- ing width. Therefore, a little impact of channel length is shown on
tive gate control can be obtained by using a high dielectric constant the drain current. However, beyond a critical channel length, the
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