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Violations

This document lists various layout violations found in design checks and provides recommended fixes. Key violations include: - NW_28 nwell continuity issue which can be fixed by adding a tap cell or changing cell orientation. - Shorts in pl_55 that can be addressed by drawing poly over exposed poly or adding shapes over vias. - Spacing errors between v0 and v0 or v0 and via layers in M0_234/233 that may require cell flipping or movement. - Four vias too close together in VCT_485 that can be fixed by adding a standard cell between flexfills. - DFI and kor errors related to minimum metal jogs,

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30 views2 pages

Violations

This document lists various layout violations found in design checks and provides recommended fixes. Key violations include: - NW_28 nwell continuity issue which can be fixed by adding a tap cell or changing cell orientation. - Shorts in pl_55 that can be addressed by drawing poly over exposed poly or adding shapes over vias. - Spacing errors between v0 and v0 or v0 and via layers in M0_234/233 that may require cell flipping or movement. - Four vias too close together in VCT_485 that can be fixed by adding a standard cell between flexfills. - DFI and kor errors related to minimum metal jogs,

Uploaded by

jayapraveen410
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Violations

Sunday, November 3, 2019 11:00 AM

Base violations
Layote---internal (on text)
Bound only fill poly
NW_28 nwell continuity..put tap cell, diff cell orientation
Settings: show cell orientation
NW_22 fix first since cell movements required

pl_55: due to shorts

• PL_63 - draw poly over exposed poly (seen in halo cells area)
• VCT_250 - viat to viat spacing is less/more than reqd…so draw shape over the 2 viats if they both are of the same
net (drc hammer script)
• VCG_250 - same as above
• VCT_61 - enclosure error - will go after metal fill stage.
After mfill if it doesn’t go, draw m0 metal of same net as v0 via near error marker.
• VCG_61 - enclosure error will go after mfill
• Rdgentbase - LD_300 and LD_301 to be ignored for now.
• Drc_VT - check nv1,pv1,nv2,pv2 layers.
**In one line there should be nv1,pv1 or nv2,pv2 layers. Cell(one pitch less than 0.102) with diff pv layers should
not be present in between dark cells (cells which donot have pv1 and nv1) . its ref_name has to be changed. Either
change pv layers or remove pv layers.(change_link ) (eg l to n)
**check for nvid,pvid layers. These are mask for vt layers.Nvid,pvid layers will go if we move the cell. If the gap
(where nvid,pvid layers is absent) is greater than one-pitch then it is allowed. If the gap is of one pitch copy
pastenvid ,pvid layers from adj cells.

M0_234/233

V0 to v0 spacing or v0 to viat spacing is not maintained. Cell flip or cell movement reqd. priority high.

VCT_485: 4 viat coming in a line..keep std cell in b/w flexfills

Dfi_integra
• For KOR errors ,delete blockages near error marker…use kor script
• DFI_B11_lvM6: Min metal Jogs facing top boundary edge: 0.11
 Fixes :- It was seen in right halo cell area, extra internal halo shapes were seen, change reference name of
halo cell with respect to A0 db(after comparing with A0). Align remaining m6,m7,m8,m9,m10 layers with
respect to boundary rules.
• DFI_B25: Large M0 gaps/plugs under TRMETAL1CUT layer must be on a 4.320 pitch ( 5 errors)
(waived)

violations Page 1
(waived)
• DFI_P14_lvM13: Port less than min width spec: 0.472 (29 errors)
Fixes :- delete datatype 2 layer in m13 (all shapes with type m13:2) in all locations where error is present.

Oob
Half drc due to halo cells - ignored

Ipall

• Load error marker, it will be shown in poly


• Switch on viag/t to get the corresponding pin
• Get the net from the pin..go to the first occurring layer/via with error. If length is long add jumper to higher layers.
Otherwise, add diode

→ Add diode
1) create_cell diode_1_new ec0_nn_p1274_diode:ec0ydpd00an2n00x5.frame (name of diode and net
name to which diode is inserted should be of same hierarchy) (ref_phys_block)
2) set_cell_location diode_1_new -coordinates {134.7200 1.2330} (lower left coordinate)
3) connect_net idfi_sram_fwenb diode_1_new2122504/dpd1 (full_name of pin)
4) connect_net vss diode_1_new2122504/vss (or give derive_pg.tcl / connect_pg_nets -automatic)

Drc_MCR

M0mcr layer
Mcr_09 Mcr should not be attached to m0 fill. It can be attached to pin. Remove mcr layers attached to fills(stretch or
delete)

LD_134
Min poly density is less

Fixes :-Changed 2-pitch and 1-pitch poly with big flexfill (10 pitch) in the common window location. Script available.

LD_300 - (density in m0 layer) source script, after that source script to fix mcr_09 and mcr_06 if present.

violations Page 2

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