_UNIT-4 Mumory yTho Memory of 2 computor habds (stan) prom Iwbue komt (What to do), data Conformation) aforaveL C Mamipulated Ov operated Upon deka), and calculations C ALU srovudts) N% Tho CPU Conhol +ho infanmation Stonod +n mom + Milowutrow U fetched, Mamiprdetad (Undov projram tontrat) and written (Or writen back) into Moor fan. Immediate or Jaton Use The jwtonal Momarg | a Compu +4 alo 2afared to os Maw Mimo, global Momay, Main SONG - YT Second ang or auyiliay Memory ( abso cables man Storage) provided by various peri poral device: Memory is suat ike a human brain. at 4) Used te store cata and Iwhuchons. Covputr Momarg (4 the Steonage Space Im te Courputtr, where data ty to be processed Oud ivspuchons ocequained for prowrsing-axe Gat Stared - Tio womang ix cLivided vite Sarge number of gmat part Cota cells. Each Location @r Goll has a cuniqua addhesr, For Rvewple 1 the G@mpuiter Dros 64 le Wands on thy Mum Unt hey 64 xle24 = 65536 Meany Jocation’ - The address Here Locations Vartes -from © peSsS3sae Memany Hiexanc 4 The momary Lrenarch systems Comslsh Omsprsyed wn a Corputlon tig. Cape. Maw Momo Cacho mow J. Figure hows the yb hy - of a Ateonary livicel systom from jo Alow city ausilrony Mamary te a scobatively fout or Y fo ay evom mall aud -foston fo high speed procig Jogrc acearsible ts - veal omen du evarely « AU tLe momay ony davicas cre hw dw te fqure feces AME Cc Drtrensing) Momeg Arerarchy Jy hayered oats thre 4 Ragicter ~ shatding Var Seog isiens ho Stow CDureds (@) e Lagers . Tnternal swgister im a CeU ts Used Fer fables and Jonporary gus edits: Interned ve a wry dma) gyenage; however thyy Combe ‘accoted Waterly-/ 3+ Mau Momuary « Maw Momo i) Large and fay fost external Mommy fleck Gout achive data amd propans ¥ Shenoy Jocattow ww Memory 41 directly add versed by Wa CPU toad and Stare lwhuckon- ¥ Acvas tme 4 hareer be cause of 4b Lave Capacity oud Physically Aaparcled frome Hae CPU: 4. Secondary /auxillory Memory ° a) Seeondary | axrxillay Mamary <0 fient in Gopacity, but Comparatively wer Alow than au th of ea i programs curd fils tha Nei data fle, 3 4 at stow Ui es Consinuserly Wy He Cpu -Semitonductan RAM Memoxter- Semicenductan Random Access memory CRAM) Is 4 -foun ct Computton clada Storage Which Zeros foquartly feSsqeetosneiraaniowd ls“ Ivicvente tha gensrad peed of Qa Ayskom - " ata thems A Stondomn ceeen Memory devive ae ne 2 an. written in amour Tht Re oe Ha ‘physical Jocotiow 4 data a Ame (souapectve o inde tha MuUnory: Semiconductor Memort4y Gwe the volakile mompay Sherorps hot stare Ho program aut data undbil Ho ouler Supply te Hs syitown iS ON’ Tha Cycle imme ol thuse Seri conductor WAunmyres Yauges fergie fo Jo WL Tre Cytle HMA py He es oe ot Ore actex te He heck of Wed A The Semiconductor momane > devo type + Voloble Momarg ond New Volatile mawary: dale mame as RAM) ts HO momory thet Sh tie Hee a wate undit He pater SSupry to the oman Clup au om Nes 4 The Wow valabile rmomory ( such os aa tho dala oF houtrow even Af bo 4 to Hye Money Chi} 4 off2D amd 25 D Memany Ongen calion IBRAM - In Ha 20-RAM orgamiralion , aram of ain Combating a” momouy word of n bit each Suppose — Organica ow of 92 KU2D RAM ey = 25.32 5 mowony ae a meee wom. Cee wv Ot had a ow Select Getoden o| St anne te Goleok 1 ove of A” memory aan ¥ Bach row have ™ column ( every Column wfox esech Individinal bit Ly 2d-RAM argami cation, handwarue 0 fired - & Sb roquinss more number of ogc qale- + gp ram 4 mare Complex Crenuration of 3244 20 RAM Wo An 21) Ey Wr Ay} eae Rew Selected Decodur Be A, Ay fh AN z 2 6 aor oe! 3 Dor! rat oll 56 oo \ oD 0-1 vast all 0 1c (eles Dyzt tet oH?AS D-RAM mh in Rs D-RAM om my wu devicled wvto appre ximeactily equal pats, and ono - fav column gamit alton, 4he Number of ad dniay one for 2tOW- Aolech cletosl er Joleet chcader « In 2sd RAM Korda) ort a var abde ~ ot regured Jen number of Log re gale aw dso Ram ts be Conylt- Row select clecodey 4.) aes © selet Do % wo pe 5 aeleliae ll tolum) @Cache Ms meng aw fresent tn behveem fProcessar ond Maton AOE 2 Foler x» Small im cite- mein tasnlvy acces Bre by x fk rudurey the average te why 4 foster tts Jecabily q suference, Berakon block, ee tein Manned + The tow fer of dolx ee, an rer” meee fa biw Cache é x From fer “| : be 5 wed- es ee eee) _ Prous Coch iW oog Pre_fy ==> Spore for dt ee padres mon geo | i o Lite ea dads 4 blode- peehe M api: F Cat Cache mapbing i a Techni gt by Bt mam meen’ ay broughh Emory © a of Hee typ)iw virtual Meman ore Tea ti ot ne ¢ opbears te be present but actually gt) nat present Ge Nang Mamery - + g4 Yrouide \Lua tom * NV ie ee Techn) qud allows Users ty Ue magne mony for & progam tha Aha vead peony a Coynpaber » % Virtual Memory 3 Lho Concept notes (ee fo tha Wer ahet WW9 wilt We fo 40 Capacity c) Ge condary Sreuyt widta (oval! tomar) - virtual Maomtry bo imayinad mou we ave amorang: 4 0% eon cunet oun tho enceel sxe a mom MUnOnt NOs nassl fo Use th Comopt ot eel Nts gS ayy a fom tors amd pduch Lo ved aang coh He = gam (or maw ed ae - virtyad Memory ay a ney manegererd Capability of oral operating Apion that We trandipara & Sohne’ fa OUeOs Corpulor to compensate P+ physical e mamony Shortage L 2Cache Mapping + Cache mapping defiives how a block from the main memory is mapped to the cache mer case of a cache miss ~_ bs OR + Cache mapping is a technique by which the contents of main momory are brought into the eaety memory, The following diagram illustrates the mapping process. Virtual Memory Mapping Cache Mapping Processor Main Memory Now, before proceeding further, itis important to note the following points- NOTES » Main memary is divided into equal size partitions called » Cache memory is divided into partitions having same Biz as lines. » During cache mapping, block of main memory is simply copied to the cache and the block is not actually brought from the main memory, 2 blocks or frames ‘that of blocks called Cache Techniqu, Cache mapping is performed using following three different techniques Cache Mapping Techniques Mapping 1, Direct Mapping 2. Fully Associative Mapping 3. Kaway Set Associative Mapping 1. Direct Mapping In direct mapping, * particular block of main memory can map only to a particular line of the cache. * The line number of cache to which a particular block can map is given by- Cache line number = (Main Memory Block Address ) Modulo (Number of lines in Cache) Example. * Consider cache memory is divided into ‘n’ number of lines. + Then, block ‘j of main memory can map to line number (j mod n) only of the cache.Main Memory Direct Mapping Need of Replacement Algorithm- In direct mapping, ‘+ There is no need of any replacement algorithm. ‘+ This is because a main memory block can map only to a particular line of the cache. ‘+ Thus, the new incoming block will always replace the existing block (if any) in that particular line, ision of Physical Address- {In direct mapping, the physical address is divided as-Cae) Block Number Division of Physical Address in Direct Mapping 2. Fully Associative Mapping- In fully associative mapping, + Ablock of main memory can map to any line of the cache that is freely available at that moment. ‘+ This makes fully associative mapping more flexible than direct mapping Example- Consider the following scenario- Line m Line m+1 Cache Main Memory Fully Associative MappingHere. + Allthe lines of cache are freely available + Thus, any block of main memory can map to any line of the cache. + Had al the cache lines been occupied, then one of the existing blocks will have to be replaced Need of Replacement Algorithm- Wn fully associative mapping A replacement algorithm is required. Replacement algorithm suggests the block to be replaced if all the cache lines are occupied Thus, replacement algorithm like FCFS Algorithm, LRU Algorithm etc is employed, Division of Physical Address- {In fully associative mapping, the physical address is divided as- Division of Physical Address in Fully Associative Mapping 3. K-way Set Associative Mapping- In k-way set associative mapping, Cache lines are grouped into sets where each set contains k number of lines. A particular block of main memory can map to only one particular set of the cache However, within that set, the memory block can map any cache line that is freely available ‘The set of the cache to which a particular block of the main memory can map is given by- Cache set number = (Main Memory Block Address ) Modulo (Number of sets in Cache) ll eedExample: Consider the following example of 2-way set associative mapping Cache Main Memory 2-Way Set Associative Mapping Here, k= 2 suggests that each set contains two cache lines, Since cache contains 6 lines, s0 number of sels in the cache = 6/2= 3 sets. Block '{ of main memory can map to set number (/ mod 3) only of the cache, ‘Within that set, block ‘can map to any cache line that is freely available at that moment "Wall the cache lines are occupied, then one of the existing blocks will have to be replaced. Need of Replacement Algorithm + Set associative mapping is a combination of direct mapping and fully associative mapping + Ituses fully associative mapping within each set. + Thus, set associative mapping requires a replacement algorithm,/ Division of Physical Address- In set associative mapping, the physical address is divided as Tag Division of Physical Address in K-way Set Associative Mapping Special Cases- «= Ifk=1, then k-way set associative mapping becomes direct mapping i.e 4away Set Associative Mapping = Direct Mapping If k= Total number of lines in the cache, then k-way.set associative mapping becomes fully, associative mapping.Application of Cache Memory ~ oe Usually, the cache memory can store a reasonable number of blocks at any given time, but this number is small compared to the (otal number of blocks in the main memory. ‘The correspondence between the main memory blocks and those in the cache is specified by a mapping function. ‘Types of Cache — Primary Cache ~ A primary cache is always located on the processor chip. ‘This cache is small and its access time is comparable to that of processor registers. Secondary Cache — Secondary cache is placed between the primary cache and the rest of the memory. It is referred to as the level 2 (L2) cache. Often, the Level 2 cache is also housed on the processor chip. Locality of reference - Since size of cache memory is less as compared to main memory. So to check which part of main memory should be given priority and loaded in cache is decided based on locality of reference. ‘Types of Locality of reference ‘Spatial Locality of reference This says that there is a chance that element will be present in the close proximity to the reference point and next time if again searched then more close proximity to the point of reference. ‘Temporal Locality of reference In this Least recently used algorithm will be used. Whenever there is page fault occurs within a word will not only load word in main memory but complete page fault will be loaded because spatial locality of reference rule says that if you are referring any word next word will be referred in its register that’s why we load complete page tuble so the complete block will be loaded.