T Flip-Flop
Block Diagram: Truth Table:
Inputs Outputs
clk rst t q qb
1 1 1 1 0
1 1 0 0 1
X 0 X 0 1
Program:
module tff(clk,rst,t, q,qb);
input clk,rst,t;
output q,qb;
reg temp;
always @(posedge clk or negedge rst)
begin
if(~rst)
begin
temp=1'b0;
end
else
if(t)
begin
temp=~temp;
end
else
begin
temp=temp;
end
end
assign q=temp;
assign qb=~temp;
endmodule
CYCLE –3
3. Write a VERILOG code to interface DAC and generate a SINE Waveform.
// Main module
module sine_wave(Clk,data_out);
//declare input and output
input Clk;
output [7:0] data_out;
//declare the sine ROM - 30 registers each 8 bit wide.
reg [7:0] sine [0:71];
//Internal signals
integer i;
reg [7:0] data_out;
//Initialize the sine rom with samples.
initial begin
i = 0;
sine[0] = 128;//77;
sine[1] =138;//93 ;
sine[2] = 148;//108;
sine[3] = 160;//122;
sine[4] = 169;//135;
sine[5] = 181;//147;
sine[6] = 192;//158;
sine[7] = 201;//168;
sine[8] = 210;
sine[9] = 217;
sine[10] =226;
sine[11] =232;
sine[12] =238;
sine[13] =244;
sine[14] =248;
sine[15] =251;
sine[16] =253;
sine[17] =254;
sine[18] =255;
sine[19] =254;
sine[20] =253;
sine[21] =251;
sine[22] =248;
sine[23] = 244;
sine[24] = 238;
sine[25] =226;
sine[26] =217;
sine[27] =210;
sine[28] =201;
sine[29] =192;
sine[30] =181;
sine[31] =169;
sine[32]=160 ;
sine[33]=148 ;
sine[34] =138;
sine[35] =128;
sine[36] =117 ;
sine[37] = 106;
sine[38] = 96;
sine[39] = 84;
sine[40] = 73;
sine[41] = 64;
sine[42] =55;
sine[43] =46;
sine[44] =37;
sine[45] =30;
sine[46] =23;
sine[47] =17;
sine[48] =12;
sine[49] =8;
sine[50] =4;
sine[51] =2;
sine[52] =1;
sine[53] =0;
sine[54] =1;
sine[55] = 2;
sine[56] = 4;
sine[57] =8;
sine[58] =12;
sine[59] =17;
sine[60] =23;
sine[61] =30;
sine[62] =37;
sine[63] =46;
sine[64] =55;
sine[65] =64;
sine[66] =73;
sine[67] =84;
sine[68] =96;
sine[69] =106;
sine[70] =117;
sine[71] =128;
end
reg[20:0]clk_signal;
reg clk_1;
initial
clk_signal=21'd0;
always@(posedge Clk)
begin
clk_signal=clk_signal+1;
clk_1=clk_signal[8]; // To change frequency use clk_signal[4]
end
//At every positive edge of the clock, output a sine wave sample.
always@ (posedge(clk_1))
begin
data_out = sine[i];
i = i+ 1;
if(i == 71)
i = 0;
end
endmodule
Waveform:
#PINLOCK_BEGIN
NET "clk" LOC = P2; Connect to 100K Clock Pin
NET "op<0>" LOC = P4; -> To Pin 21 of DAC
NET "op<1>" LOC = P5; -> To Pin 22 of DAC
NET "op<2>" LOC = P7; -> To Pin 19 of DAC
NET "op<3>" LOC = P9; -> To Pin 20 of DAC
NET "op<4>" LOC = P10; ->To Pin 17 of DAC
NET "op<5>" LOC = P11; ->To Pin 18 of DAC
NET "op<6>" LOC = P12; ->To Pin 15 of DAC
NET "op<7>" LOC = P13; ->To Pin 16 of DAC
Connect Pin 26 of DAC to GND Pin
#PINLOCK_END
BLOCK DIAGRAM OF RAMP / TRIANGULAR / SQUARE WAVEFORM
Data out
CLK FPGA DAC CRO
4. Write a VERILOG code to interface DAC and generate a Triangular
Waveform.
//Main module
moduletri_dac (clk,rst,op);
inputclk;
inputrst;
output [7:0] op;
wire [7:0] op;
reg [7:0] q;
regud;
initial
begin
ud = 1'b 0;
end
always @(posedgeclk or negedgerst)
begin
if (rst == 1'b 0)
q = 8'b 0;
else
begin
if (ud == 1'b 0)
q = q + 1;
else if (ud == 1'b 1 )
q = q - 1;
end
end
assign op = q;
always @(posedgeclk)
begin
if (q == 8'b 11111110)
ud<= 1'b 1;
else if (q == 8'b 00000001 )
ud<= 1'b 0;
end
endmodule
Waveform:
#PINLOCK_BEGIN
NET "clk" LOC = P2; Connect to 100K Clock Pin
NET "rst" LOC = P3;
NET "op<0>" LOC = P4; -> To Pin 21 of DAC
NET "op<1>" LOC = P5; -> To Pin 22 of DAC
NET "op<2>" LOC = P7; -> To Pin 19 of DAC
NET "op<3>" LOC = P9; -> To Pin 20 of DAC
NET "op<4>" LOC = P10; ->To Pin 17 of DAC
NET "op<5>" LOC = P11; ->To Pin 18 of DAC
NET "op<6>" LOC = P12; ->To Pin 15 of DAC
NET "op<7>" LOC = P13; ->To Pin 16 of DAC
Connect Pin 26 of DAC to GND Pin
#PINLOCK_END
BLOCK DIAGRAM OF RAMP / TRIANGULAR / SQUARE WAVEFORM
OP
CLK FPGA DAC CRO
RST
5. .Write a VERILOG code to interface DAC and generate a Square
Waveform.
//Main module
modulesquarewave(clk,rst,op);
inputclk,rst;
output [7:0] op;
wire [7:0] op;
reg [7:0] temp;
reg [7:0] q;
always@(posedgeclk)
begin
if(~rst)
q=8'b0;
else
q=q+1;
end
always@(q)
begin
if(q<=127)
temp=8'b00000000;
else
temp=8'b11111111;
end
assign op = temp;
endmodule
Waveform:
#PINLOCK_BEGIN
NET "clk" LOC = P2; Connect to 100K Clock Pin
NET "rst" LOC = P3;
NET "op<0>" LOC = P4; -> To Pin 21 of DAC
NET "op<1>" LOC = P5; -> To Pin 22 of DAC
NET "op<2>" LOC = P7; -> To Pin 19 of DAC
NET "op<3>" LOC = P9; -> To Pin 20 of DAC
NET "op<4>" LOC = P10; ->To Pin 17 of DAC
NET "op<5>" LOC = P11; ->To Pin 18 of DAC
NET "op<6>" LOC = P12; ->To Pin 15 of DAC
NET "op<7>" LOC = P13; ->To Pin 16 of DAC
Connect Pin 26 of DAC to GND Pin
#PINLOCK_END
BLOCK DIAGRAM OF RAMP / TRIANGULAR / SQUARE WAVEFORM
OP
CLK FPGA DAC CRO
RST
6. Write a VERILOG code to control the Direction and speed of Stepper
motor and demonstrate it.
Theory:
A stepper motor is a digital motor. It can be driven by digital signal. The motor has two phase with center tap
winding. The centre taps of these windings are connected to the 12V supply. Due to this motor can be excited by
grounding four terminals of the two windings.
Motor can be rotated in steps by giving proper excitation to these windings. These excitation signals are buffered
using transistor. The transistors are selected such that they can source the stored current for the windings.Motor is rotated
by 1.8 degree per excitation. Speed can be changed by varying the clock.
//Main module
modulestepm(clk,rst,dir,step_ctrl,dout);
inputclk,rst,dir;
input [1:0] step_ctrl;
output [3:0] dout;
reg [3:0] dout;
reg [20:0] dclk;
regdiv_clk;
always@(posedgeclk)
begin
dclk=dclk+1;
end
always@(posedgeclk)
begin
case(step_ctrl)
2'b00:div_clk=dclk[20];
2'b01:div_clk=dclk[18];
2'b10:div_clk=dclk[16];
2'b11:div_clk=dclk[14];
endcase
end
always@(posedgediv_clk)
begin
if(!rst)
dout=4'b1001;
else
case(dir)
1'b0:dout={dout[0],dout[3:1]};
1'b1:dout={dout[2:0],dout[3]};
endcase
end
endmodule
#PINLOCK_BEGIN
NET "clk" LOC = P2; Connect to 100K Clock Pin
NET "rst" LOC = P3;
NET "dir" LOC = P4;
NET "step_ctrl<0>" LOC = P5; Speed Control PIN’s
NET "step_ctrl<1>" LOC = P7;
NET "dout<0>" LOC = P31;
NET "dout<1>" LOC = P33;
NET "dout<2>" LOC = P34; Connect Pin 1, 2, 3 and 4 of Stepper Motor
NET "dout<3>" LOC = P35;
#PINLOCK_END
BLOCK DIAGRAM OF STEPPER MOTOR
RST
dout FPGA STEPPER MOTOR
MOTOR
CLK
Dir Step Control [1:0]
