Stereo PDM to I2S/TDM Converter

Data Sheet ADAU7112

FEATURES FUNCTIONAL BLOCK DIAGRAM
1.10V TO 1.98V 1.70V TO 3.63V
2 channels of PDM audio inputs from digital microphones
64× decimation ratio of PDM to PCM audio data
24-bit resolution to support high sound pressure level (SPL)
microphones DVDD GND IOVDD
126 dB A-weighted SNR
4 kHz to 96 kHz output sampling rate
Bit clock rates of 64×, 128×, 192×, 256×, 384×, or 512× the PDM_CLK BCLK
PDM DIGITAL I2S/TDM
output sampling rate INPUT DECIMATION OUTPUT FSYNC
Automatic PDM clock generation PORT FILTERING PORT
PDM_DAT SDATA
Automatic power-down when BCLK is removed
0.36 mA DVDD operating current at 48 kHz sampling rate ADAU7112

17232-001
and 1.8 V supply
CONFIG
Slave I2S or TDM output interface
Figure 1.
Up to TDM-16 supported
Configurable TDM slots
I/O supply voltage from 1.70 V to 3.63 V
DVDD core supply voltage from 1.10 V to 1.98 V
4 μA typical DVDD shutdown current
9-ball, 1.26 mm × 1.26 mm, 0.4 mm pitch WLCSP
Power-on reset

APPLICATIONS
Mobile computing
Portable electronics
Consumer electronics
Professional electronics

GENERAL DESCRIPTION
The ADAU7112 converts stereo pulse density modulation The ADAU7112 is specified over a commercial temperature
(PDM) bit streams into one pulse code modulation (PCM) output range of −40°C to +85°C. The ADAU7112 is available in a
stream. The source for the PDM data can be two microphones halide-free, 9-ball, 1.26 mm × 1.26 mm, 0.4 mm pitch, wafer
or other PDM sources. The PCM audio data is output on a serial level chip scale package (WLCSP).
audio interface port in either inter-IC serial (I2S) or time domain
multiplexed (TDM) format.

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADAU7112 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................7
Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8
Functional Block Diagram .............................................................. 1 Theory of Operation .........................................................................9
General Description ......................................................................... 1 Power-Up and Initialization.........................................................9
Revision History ............................................................................... 2 Clocking..........................................................................................9
Specifications..................................................................................... 3 Power-Down State .........................................................................9
Serial Port Timing Specifications ............................................... 4 Serial Audio Output Interface .....................................................9
PDM Input Timing Specifications ............................................. 5 Applications Information .............................................................. 13
Absolute Maximum Ratings............................................................ 6 Outline Dimensions ....................................................................... 14
Thermal Resistance ...................................................................... 6 Ordering Guide .......................................................................... 14
ESD Caution .................................................................................. 6

REVISION HISTORY
6/2019—Revision 0: Initial Version

Rev. 0 | Page 2 of 14
Data Sheet ADAU7112

SPECIFICATIONS
DVDD = 1.10 V to 1.98 V, IOVDD = 1.70 V to 3.63 V, TA = 25°C, unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT
Input Voltage
High Level (VIH) 0.7 × V
IOVDD
Low Level (VIL) 0.3 × V
IOVDD
Input Leakage Digital input pins with pull-down resistor
High Level (IIH) 2.5 μA
Low Level (IIL) at 0 V 1 μA
Input Capacitance (CI) 2 pF Guaranteed by design
DIGITAL OUTPUT
Output Voltage
High Level (VOH) 0.85 × V Source current when output is high (IOH) = 1 mA
IOVDD
Low Level (VOL) 0.1 × V Source current when output is low (IOL) = 1 mA
IOVDD
Digital Output Pins, The digital output pins are driving low impedance
Output Drive printed circuit board (PCB) traces to a high
impedance digital input buffer
IOVDD = 1.8 V Nominal
Drive Strength 2.8 mA
IOVDD = 3.3 V Nominal
Drive Strength 10 mA
PERFORMANCE
Dynamic Range 126 dB 20 Hz to 20 kHz, −60 dB input, A-weighted filter
(rms), relative to 0 dBFS output
Signal-to-Noise Ratio 126 dB A-weighted filter, fifth-order input, relative to
(SNR) 0 dBFS output
Decimation Ratio 64× Only 64× is supported
Frequency Response −0.1 +0.01 dB DC to 0.45 × output sampling rate
Stop Band 0.566 × output Hz
sampling rate
(fS)
Stop Band Attenuation 75 dB
Group Delay 4.47 4.47 4.47 FSYNC cycles 0.02 fS input signal
Gain 0 0 0 dB PDM to PCM
Start-Up Time 63 64 64 FSYNC cycles After power-up reset and initialization code is run
Bit Resolution 24 Bits Internal and output
Interchannel Phase 0 0 0 Degrees
CLOCKING
Output Sampling Rate (fS) 4 48 96 kHz FSYNC pulse rate
Bit Clock Frequency (fBCLK) 0.256 12.288 24.576 MHz
PDM_CLK Frequency 0.256 3.072 6.144 MHz
(fPDM_CLK)
POWER
Supply Voltage
Digital Core Voltage 1.10 1.98 V Supply for digital circuitry
(DVDD Pin)
Input/Output (I/O) 1.70 3.63 V Supply for I/O circuitry, including pads and level
Supply Voltage shifters
(IOVDD Pin)
Rev. 0 | Page 3 of 14
ADAU7112 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Supply Current
I/O Current (IOVDD Pin) Dependent on the clock rates and characteristics of
external loads
Operation State 1.6 mA IOVDD = 3.3 V, fS = 48 kHz, TDM-8 format, 25 pF
capacitance
0.86 mA IOVDD = 1.8 V, fS = 48 kHz, TDM-8 format, 25 pF
capacitance
Shutdown Current 16 µA Power applied, frame and bit clocks applied, then
clocks removed. This specification is highly
dependent on the external loads.
Digital Current
(DVDD Pin)
Operation State 0.4 mA Over all temperatures, full voltage range, and
silicon skews, fS = 48 kHz, I2S format
0.36 mA DVDD = 1.8 V, fS = 48 kHz
0.21 mA DVDD = 1.2 V, fS = 48 kHz
Shutdown Current 4 µA Power applied, frame and bit clocks applied, then
clocks removed

SERIAL PORT TIMING SPECIFICATIONS

TA = −40°C to +85°C, DVDD = 1.10 V to 1.98 V, IOVDD = 1.70 V to 3.63 V, unless otherwise noted.

Table 2.
Parameter Min Max Unit Description
SERIAL PORT
fFSYNC 96 kHz FSYNC frequency, 1/tFSYNC, not included in Figure 2
tFSYNC 10.42 µs FSYNC period
fBCLK 24.576 MHz BCLK frequency, sample rate ranging from 4 kHz to 96 kHz, 1/tBCLK, not included in Figure 2
tBCLK 40.7 ns BCLK period
tBIL 18 ns BCLK low pulse width, slave mode, BCLK frequency = 24.576 MHz, BCLK period = 40.7 ns
tBIH 18 ns BCLK high pulse width, slave mode, BCLK frequency = 24.576 MHz, BCLK period = 40.7 ns
tLIS 10 ns FSYNC setup to BCLK input rising edge, slave mode, FSYNC frequency = 96 kHz
tLIH 10 ns FSYNC hold from BCLK input rising edge, slave mode, FSYNC frequency = 96 kHz
tSOD 20.63 ns SDATA delay from BCLK output falling edge, 25 pf load over entire range of IOVDD, all temperatures
and skews
9.03 ns IOVDD = 3.3 V ± 10%, with 25 pf load
20.63 ns IOVDD = 1.7 V to 1.89 V, with 25 pf load

tBIH tBCLK tLIH

BCLK

tBIL
tLIS
FSYNC

tFSYNC

SDATA MSB
tSOD
17232-002

SDATA
ALL MODES

Figure 2. Serial Port Timing Diagram

Rev. 0 | Page 4 of 14
Data Sheet ADAU7112
PDM INPUT TIMING SPECIFICATIONS
TA = −40°C to +85°C, DVDD = 1.10 V to 1.98 V, IOVDD = 1.70 V to 3.63 V, PDM data is latched on both edges of the clock (see Figure 3),
unless otherwise noted.

Table 3.
Parameter tMIN tMAX Unit Description
tSETUP 9 ns Data setup time
tHOLD 3 ns Data hold time

PDM_CLK

tSETUP tHOLD

17232-003
PDM_DAT R L R L

Figure 3. PDM Timing Diagram

Rev. 0 | Page 5 of 14
ADAU7112 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4. THERMAL RESISTANCE
Parameter Rating Thermal performance is directly linked to PCB design and
DVDD to GND 1.98 V operating environment. Careful attention to PCB thermal
IOVDD to GND 3.63 V design is required.
Digital Inputs DGND − 0.3 V to
IOVDD + 0.3 V Table 5. Thermal Resistance
Maximum Operating Ambient −40°C to +85°C Package Type θJA1 θJC2 Unit
Temperature Range CB-9-8 57.1 0.5 °C/W
Junction Temperature Range −65°C to +165°C 1
Thermal impedance simulated values are based on a JEDEC 1S0P thermal
Storage Temperature Range −65°C to +150°C test board. See JEDEC JESD-51.
Soldering Temperature (60 sec) 300°C 2
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-51.
Electrostatic Discharge (ESD) 4.5 kV
Susceptibility ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. 0 | Page 6 of 14
Data Sheet ADAU7112

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADAU7112
BALL A1
CORNER 1 2 3

A DVDD GND IOVDD

B SDATA CONFIG PDM_DAT

C FSYNC BCLK PDM_CLK

17232-004
TOP VIEW
(BALL SIDE DOWN)
Not to Scale

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
A1 DVDD Internal Core Digital Power Supply.
A2 GND Ground.
A3 IOVDD Digital I/O Power Supply.
B1 SDATA I2S/TDM Serial Data Output.
B2 CONFIG Configuration Pin.
B3 PDM_DAT PDM Input Data.
C1 FSYNC I2S/TDM Frame Synchronization or Left/Right Clock.
C2 BCLK I2S/TDM Bit Clock.
C3 PDM_CLK PDM Output Clock.

Rev. 0 | Page 7 of 14
ADAU7112 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0 –100
–10 –102
–20 –104
–30 –106
–40 –108
–50 –110

THD + N LEVEL (dBFS)

–60 –112
–70 –114
LEVEL (dBFS)

–80 –116
–90 –118 CH1
–100 –120 CH2
–110 –122
–120 –124
–130 –126
CH1
–140 CH2 –128
–150 –130
–160 –132
–134
–170
–136
–180
–138
–190
–140

17232-005

17232-008
20 100 1k 10k 20k 20 100 1k 10k 20k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 5. Fast Fourier Transform (FFT), fS = 48 kHz, −60 dBFS Input, 64× Figure 8. Total Harmonic Distortion + Noise (THD + N) Level vs. Frequency at
Decimation, Fifth Order −10 dBFS Unweighted, fS = 48 kHz, 64× Decimation, Fifth Order

1.0
0.9 0
0.8
–20
0.7
0.6
–40
0.5
RELATIVE LEVEL (dB)

0.4
–60
MAGNITUDE (dB)

0.3
0.2 –80
0.1
0 –100
–0.1
–0.2 –120
–0.3
–0.4 –140
–0.5
–0.6 –160
–0.7
–0.8 –180
–0.9

17232-009
17232-006

0 0.5 1.0 1.5

20 100 1k 10k 20k
FREQUENCY (MHz)
FREQUENCY (Hz)

Figure 6. Relative Level vs. Frequency at −10 dBFS Normalized, 64× Figure 9. Magnitude vs. Frequency, 48 kHz Output, 64× Decimation
Decimation, fS = 48 kHz

160 0
150 –10
140 –20
130
–30
120
THD + N LEVEL (dBFS)

–40
110
GROUP DELAY (µs)

100 –50
90 –60
CH1
80 –70 CH2
70 –80
60 –90
50
–100
40
–110
30
20 –120
10 –130
0 –140
17232-010
17232-007

20 100 1k 10k 20k –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
MEASURED LEVEL (dBFS)
FREQUENCY (Hz)

Figure 7. Group Delay vs. Frequency, fS = 48 kHz, 64× Decimation Figure 10. THD + N Level vs. Measured Level, 1 kHz, Unweighted, 64×
Decimation, Fifth Order, fS = 48 kHz

Rev. 0 | Page 8 of 14
Data Sheet ADAU7112

THEORY OF OPERATION
The ADAU7112 provides up to two channels of decimation The ADAU7112 requires a BCLK rate that is a minimum of 64×
from a 1-bit PDM source to a 24-bit PCM audio output. The the frame sync (FSYNC) sample rate. BCLK rates of 128×, 192×,
downsampling ratio is 64 × fS, with fS being the PCM output 256×, 384×, and 512× the FSYNC rate are also supported. The
sampling rate. All channels decimate at the same ratio. The 24-bit ADAU7112 automatically detects the ratio between BCLK and
downsampled PCM audio is output via standard I2S or TDM FSYNC and generates a PDM clock output at 64× the FSYNC
format. rate. The minimum sampling rate is 4 kHz, and the maximum
The input sources for the ADAU7112 can be any device that has sample rate is 96 kHz. The PDM clock range is 256 kHz to
a slave PDM output, such as a digital microphone. The output 6.144 MHz. Internally, all processing is performed at the
pins of these microphones can connect directly to the input pins PDM_CLK rate.
of the ADAU7112. POWER-DOWN STATE
The PDM_DAT input pin is connected to the data output of the The ADAU7112 can be placed in a power-down state by
PDM sources. Internally, there are two channels, Channel 0 and stopping the frame and bit clocks that are being sent to the device.
Channel 1. The mapping of the PDM_DAT input data to To exit power-down mode, resume sending frame and bit clocks
internal channels is shown in Table 7. to the device.
Table 7. PDM_DAT to Internal Channel Mapping SERIAL AUDIO OUTPUT INTERFACE
Input Pin PDM_CLK Edge Internal Channel The ADAU7112 supports I2S and TDM serial output formats.
PDM_DAT Falling 0 Up to TDM-16 can be used, but the ADAU7112 can only place
Rising 1 data in the first eight slots. The internal channel pair can be
POWER-UP AND INITIALIZATION routed to one of four different pairs of output slots using the
The ADAU7112 requires two power supplies to function: IOVDD CONFIG pin.
and the DVDD. Both power supplies can be applied at the same Table 9 lists the available settings using the CONFIG pin. For
time. If the power supplies are applied at different times, IOVDD the I2S configuration, the two internal channels are placed in
must be applied first and then DVDD can be applied at any the audio stream as shown in Figure 11.
point after. There are no timing restrictions. For the TDM format, the configuration is independent of the
After the power supplies stabilize, the device initializes and is actual number of TDM slots available. The configuration
ready to accept incoming I2S clocks. determines the slots in which the data is placed. However, if the
After the initialization is complete and I2S clocks are applied, it bit clock to frame clock ratio is such that the slot can never be
takes 16 full frame synchronization cycles to begin sending out reached, the data is lost.
PDM clocks. When the PDM clocks start, and after another 48 For example, if the CONFIG pin is pulled up through a 47 kΩ
frame synchronization cycles, the PDM data is available on the resistor to IOVDD, the data is placed in Slot 5 and Slot 6. Then,
SDATA pin. These 64 frame sync cycles are listed in Table 1. if the bit clock being sent is 128 × fS, there are only four slots in
each frame. Slot 5 and Slot 6 are never reached.
CLOCKING
See Table 8 for supported bit clock to frame clock ratios and the
After power is applied and the power-up initialization is complete,
resulting number of TDM data slots. Figure 14 through Figure 17
the device is ready to accept I2S clocks. At this point, it takes 16
show the different options for placing the data in Slot 1 to Slot 8.
full frame synchronization cycles for the device to fully initialize
and start sending PDM clocks. If during normal operation the These options also apply to any of the supported bit clock to
frame clock ratios.
bit clock or frame synchronization is removed, the ADAU7112
PDM_CLK outputs stop immediately and the ADAU7112 For the TDM-12 and TDM-16 clock rates, the data can only be
automatically enters a low power state. See the Power-Down State placed in Slot 1 to Slot 8.
section for more details. When the clocks resume, the ADAU7112 The SDATA pin is in tristate high impedance mode, except
relocks to the bit clock and the frame synchronization signals and when the port is driving serial data.
adjusts the PDM_CLK outputs accordingly. The length of time
With the CONFIG pin tied to IOVDD, the serial port is in I2S
before the PDM clock outputs resume is 4 frames ± 1 frame to
stereo mode with a 50/50 duty cycle frame clock expected. In
lock to the incoming signal. If the format of the clock signals
this mode, the frame starts with the falling edge of the frame
changes, the ADAU7112 detects this change at the end of the
synchronization, and the expected duty cycle is 50% high and
frame and stops the PDM clock outputs. Then, the device
50% low. Channel 0 sends out data when the clock is low, and as
reconfigures and resumes sending PDM clocks with no user
soon as the frame synchronization goes high, the data from
intervention. Again, this usually takes 4 frames ± 1 frame to
Channel 0 is stopped and Channel 1 begins sending data. Both
lock to the incoming signal.
edges of the frame synchronization clock are used. If the duty
Rev. 0 | Page 9 of 14
ADAU7112 Data Sheet
cycle is not 50/50, there may be errors in the resulting data. In Table 8. Supported TDM Bit Clock Rates
this mode, there must be 64 bit clock cycles per frame. Number of
Bit Clock Rate Data Slots Notes
The ADAU7112 can support six different bit clock rates of 64×,
128×, 192×, 256×, 384×, or 512× the output sample rate. These 64 × fS 2 I2S mode see (Figure 11)
bit clock rates result in five different TDM formats that are 128 × fS 4 See Figure 12
supported. A ratio of 64 × fS changes the ADAU7112 to I2S 192 × fS 6 See Figure 13
mode. See Table 8 for details. 256 × fS 8 See Figure 14
384 × fS 12 See Figure 18
In TDM mode, the frame synchronization is expected to be a 512 × fS 16 See Figure 19
positive going pulse that is at least one bit clock period wide.
The falling edge is not important and is not considered as long
as it is low long enough to meet the timing specification to be
read as a low before going back high. The frame starts with the
rising edge of this pulse.

Table 9. CONFIG Pin Options

Device Setting CONFIG Pin Configuration
I2S Format Tie to IOVDD
TDM Slot 1 to Slot 2 Driven, 32-Bit Slots Tie to GND
TDM Slot 3 to Slot 4 Driven, 32-Bit Slots Open
TDM Slot 5 to Slot 6 Driven, 32-Bit Slots Tie to IOVDD through a 47 kΩ resistor
TDM Slot 7 to Slot 8 Driven, 32-Bit Slots Tie to GND through a 47 kΩ resistor

FSYNC

BCLK

SDATA I2S CH 0 TRISTATE I2S CH 1 TRISTATE

17232-011
24 8
BCLKs BCLKs

Figure 11. I2S Mode, BCLK = 64 × fS, CONFIG Pin Tied to IOVDD

FSYNC

BCLK

SDATA CH 0 CH 1 TRISTATE TRISTATE

24 8
BCLKs BCLKs
17232-012

SLOT 1 SLOT 2 SLOT 3 SLOT 4

Figure 12. TDM-4, BCLK = 128 × fS, CONFIG Pin Tied to GND

Rev. 0 | Page 10 of 14
Data Sheet ADAU7112

FSYNC

BCLK

SDATA CH 0 CH 1 TRISTATE TRISTATE TRISTATE TRISTATE

24 8
BCLKs BCLKs

17232-013
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6

Figure 13. TDM-6, BCLK = 192 × fS, CONFIG Pin Tied to GND

FSYNC

BCLK

SDATA CH 0 CH 1 TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE

24 8
BCLKs BCLKs

17232-014
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8

Figure 14. TDM-8, BCLK = 256 × fS, CONFIG Pin Tied to GND

FSYNC

BCLK

SDATA TRISTATE TRISTATE CH 0 CH 1 TRISTATE TRISTATE TRISTATE TRISTATE

24 8
BCLKs BCLKs

17232-015
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8

Figure 15. TDM-8, BCLK = 256 × fS, CONFIG Pin Open

FSYNC

BCLK

SDATA TRISTATE TRISTATE TRISTATE TRISTATE CH 0 CH 1 TRISTATE TRISTATE

24 8
BCLKs BCLKs
17232-016

SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8

Figure 16. TDM-8, BCLK = 256 × fS, CONFIG Pin Tied to IOVDD Through a 47 kΩ Resistor

Rev. 0 | Page 11 of 14
ADAU7112 Data Sheet

FSYNC

BCLK

SDATA TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE CH 0 CH 1

24 8
BCLKs BCLKs

17232-017
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8

Figure 17. TDM-8, BCLK = 256 × fS, CONFIG Pin Tied to GND Through a 47 kΩ Resistor

FSYNC

BCLK

SDATA CH 0 CH 1 TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE

24
BCLKs

17232-018
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9 SLOT 10 SLOT 11 SLOT 12

Figure 18. TDM-12, BCLK = 384 × fS, CONFIG Pin Tied to GND

FSYNC

BCLK

SDATA CH 0 CH 1 TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE

24
BCLKs

17232-019
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9 SLOT 10 SLOT 11 SLOT 12 SLOT 13 SLOT 14 SLOT 15 SLOT 16

Figure 19. TDM-16, BCLK = 512 × fS, CONFIG Pin Tied to GND

Rev. 0 | Page 12 of 14
Data Sheet ADAU7112

APPLICATIONS INFORMATION
Figure 20 details an example application circuit using two PDM To keep PCB manufacturing costs low, a via-in-pad is not
sources and details how to set the CONFIG pin for the optional required for most common configurations. The CONFIG pin
data formats. can be left floating or a PCB trace on the top layer can connect
the CONFIG pin to the nearby IOVDD pin or GND pin. A via-
in-pad is only required when a pull-up or pull-down resistor is
required.
IOVDD
DVDD

I OVDD

C1
C9 C20
I OVDD

0.10µF
0.10µF 0.10µF

1
LRSEL_I N
VDD
DATA_OUT U2

A3

A1
5 PDM_DAT
PDM_CLK 4 2
CLK_I N GND M1 IOVDD DVDD
3 PDM Source 1
PDM CLock R18 0Ω R20 0Ω
C3 C1 FSYNC
PDM_CLK PDM_CLK FSYNC
I OVDD
R21 0Ω
PDM Dat a R19 0Ω ADAU7112 BCLK
C2 BCLK
C2
I OVDD

0.10µF PDM_DAT
R22 0Ω
B3 PDM_DAT SDATA B1 SDATA

IOVDD
1
LRSEL_I N
VDD
5
DATA_OUT PDM_DAT 47.5kΩ R5 CONFIG GND
PDM_CLK 4 2
CLK_I N GND M2

B2

A2
3 PDM Source 2
DVDD

R6
47.5kΩ
NOTE:
ONLY STUFF R5, R6 OR NONE, DO NOT STUFF BOTH.
INSTALL R5 WITH 0Ω JUMPER FOR I 2S FORMAT.
INSTALL R6 WITH 0Ω JUMPER FOR TMD FORMAT SLOT 1 AND SLOT 2.

17232-020
DO NO STUFF R5 AND R6 FOR TDM FORMAT SLOT 3 AND SLOT 4.
INSTALL R5 WITH 47.5kΩ RESISTOR FOR TDM FORMAT SLOT 5 AND SLOT 6.
INSTALL R6 WITH 47.5kΩ RESISTOR FOR TDM FORMAT SLOT 7 AND SLOT 8.

Figure 20. Example Application Circuit

Rev. 0 | Page 13 of 14
ADAU7112 Data Sheet

OUTLINE DIMENSIONS
1.300
1.260
1.220
3 2 1

IDENTIFIER
0.80
REF B

C
0.40
BSC
TOP VIEW BOTTOM VIEW
(BALL SIDE DOWN) (BALL SIDE UP)

0.560
0.500 SIDE VIEW
0.440
COPLANARITY
0.05

SEATING 0.230
PLANE 0.300
0.200

06-12-2018-A
0.260
PKG-005978

0.170
0.220

Figure 21. 9-Ball Wafer Level Chip Scale Package [WLCSP]

1.26 mm × 1.26 mm Body
(CB-9-8)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADAU7112ACBZRL −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP], 13” Tape and Reel CB-9-8
ADAU7112ACBZR7 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP], 7” Tape and Reel CB-9-8
EVAL-ADAU7112Z Evaluation Board
1
Z = RoHS Compliant Part.

©2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D17232-0-6/19(0)

Rev. 0 | Page 14 of 14