TRF371125

www.ti.com SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010

INTEGRATED IQ DEMODULATOR
Check for Samples: TRF371125

1FEATURES DESCRIPTION
•
2 Frequency Range: 700 MHz to 4000 MHz The TRF371125 is a highly linear and integrated
• Integrated Baseband Programmable-Gain direct-conversion quadrature demodulator. The
Amplifier TRF371125 integrates balanced I and Q mixers, LO
buffers, and phase splitters to convert an RF signal
• On-Chip Programmable Baseband Filter
directly to I and Q baseband. The on-chip
• High Out-of-Band IP3: 24 dBm at 2400 MHz programmable-gain amplifiers allow adjustment of the
• High Out-of-Band IP2: 60 dBm at 2400 MHz output signal level without the need for external
• Hardware and Software Power Down variable-gain (attenuator) devices. The TRF371125
integrates programmable baseband low-pass filters
• Three-Wire Serial Interface that attenuate nearby interference, eliminating the
• Single Supply: 4.5-V to 5.5-V Operation need for an external baseband filter.
• Silicon Germanium Technology Housed in a 7-mm × 7-mm QFN package, the
TRF371125 provides the smallest and most
APPLICATIONS integrated receiver solution available for high-
• Multicarrier Wireless Infrastructure performance equipment.
• WiMAX
• High-Linearity Direct-Downconversion
Receiver
• LTE (Long Term Evolution)
To Microcontroller
To Microcontroller
READBACK
STROBE
MIXIoutp

MIXIoutn

Gain_B0
Gain_B1
Gain_B2
CLOCK
DATA

NC
NC

NC

48 47 46 45 44 43 42 41 40 39 38 37
GNDDIG 1 36 VCCBBI
VCCDIG 2 35 GND
CHIP_EN 3 34 BBIoutn
To ADC I
VCCMIX1 4 33 BBIoutp
GND 5 32 GND
RFin MIXinp 6 31 LOip LOin
TRF371125
MIXinn 7 30 LOin
GND 8 29 VCCLO
VCCMIX2 9 28 BBQoutp
To ADC Q
NC 10 27 BBQoutn
NC 11 26 GND
GND 12 25 VCCBBQ
13 14 15 16 17 18 19 20 21 22 23 24
MIXQoutn

VCCBIAS
GNDBIAS
GND
GND
GND
MIXQoutp

NC
NC

NC
VCM
REXT

30 kW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TRF371125
SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE DEVICE OPTIONS (1)

SPECIFIED
PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT TEMPERATURE
LEAD DESIGNATOR(1) MARKING NUMBER MEDIA, QUANTITY
RANGE
TRF371125IRGZR Tape and Reel, 2500
TRF371125 QFN-48 RGZ –40°C to 85°C TRF371125
TRF371125IRGZT Tape and Reel, 500

FUNCTIONAL DIAGRAM

MIXIoutp
MIXIoutn
45

44

ADC Driver
33 BBIoutp
VCCs PGA 34 BBIoutn
GND
24 VCM
DC Offset Control I

30 LOin
0°
MIXinp 6 90° 31 LOip
MIXinn 7

DC Offset Control Q

27 BBQoutn
PGA 28 BBQoutp
ADC Driver
3 Power 48
CHIP_EN DC Offset Control CLOCK
Down
47
DATA
LPFADJ Control SPI 46
STROBE
37
PGA Control Q READBACK
41
40
39
16
17

Gain_B0
Gain_B1
Gain_B2
MIXQoutp
MIXQoutn

B0385-01

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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DEVICE INFORMATION

PIN ASSIGNMENTS
space
RGZ PACKAGE
QFN-48
(TOP VIEW)

READBACK
STROBE
MIXIoutp

MIXIoutn

Gain_B0
Gain_B1
Gain_B2
CLOCK
DATA

NC
NC

NC
48 47 46 45 44 43 42 41 40 39 38 37
GNDDIG 1 36 VCCBBI
VCCDIG 2 35 GND
CHIP_EN 3 34 BBIoutn

VCCMIX1 4 33 BBIoutp
GND 5 32 GND
MIXinp 6 31 LOip
TRF371125
MIXinn 7 30 LOin
GND 8 29 VCCLO
VCCMIX2 9 28 BBQoutp

NC 10 27 BBQoutn
NC 11 26 GND
GND 12 25 VCCBBQ
13 14 15 16 17 18 19 20 21 22 23 24
MIXQoutn

VCCBIAS
GNDBIAS
GND
GND
GND
MIXQoutp

NC
NC

NC
VCM
REXT

PIN FUNCTIONS
PIN
I/O DESCRIPTION
NO. NAME
1 GNDDIG Digital ground
2 VCCDIG Digital power supply
3 CHIP_EN I Chip enable
4 VCCMIX1 Mixer power supply
5 GND Ground
6 MIXinp I Mixer input: positive terminal
7 MIXinn I Mixer input: negative terminal
8 GND Ground
9 VCCMIX2 Mixer power supply
10 NC No connect
11 NC No connect
12 GND Ground
13 GND Ground
14 GND Ground
15 GND Ground

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PIN FUNCTIONS (continued)

PIN
I/O DESCRIPTION
NO. NAME
16 MIXQoutp O Mixer Q output: positive terminal
17 MIXQoutn O Mixer Q output: negative terminal
18 NC No connect
19 NC No connect
20 REXT O Reference bias external resistor
21 VCCBIAS Bias block power supply
22 GNDBIAS Bias block ground
23 NC No connect
24 VCM I Baseband common-mode input voltage
25 VCCBBQ Baseband Q chain power supply
26 GND Ground
27 BBQoutn O Baseband Q (in quadrature) output: negative terminal
28 BBQoutp O Baseband Q (in quadrature) output: positive terminal
29 VCCLO Local oscillator power supply
30 Loin I Local oscillator input: negative terminal
31 Loip I Local oscillator input: positive terminal
32 GND Ground
33 BBIoutp O Baseband I (in-phase) output: positive terminal
34 BBIoutn O Baseband I (in-phase) output: negative terminal
35 GND Ground
36 VCCBBI Baseband I (in phase) power supply
37 NC No connect
38 READBACK O SPI readback data
39 Gain_B2 I PGA fast gain control bit 2
40 Gain_B1 I PGA fast gain control bit 1
41 Gain_B0 I PGA fast gain control bit 0
42 NC No connect
43 NC No connect
44 MIXIoutn O Mixer I output: negative terminal
45 MIXIoutp O Mixer I output: positive terminal
46 STROBE I SPI enable
47 DATA I SPI data input
48 CLOCK I SPI clock input

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
Supply voltage range (2) –0.3 to 6 V
Digital I/O voltage range –0.3 to 6 V
Operating free-air temperature range, TA –40 to 85 °C
Operating virtual junction temperature range, TJ –40 to 150 °C
Storage temperature range, Tstg –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Power supply voltage 4.5 5 5.5 V
Power supply voltage ripple 940 µVpp
TA Operating free-air temperature range –40 85 °C
TJ Operating virtual junction temperature range –40 150 °C

THERMAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT
Soldered slug, no airflow 26
RqJA Soldered slug, 200-LFM airflow 20.1
Thermal resistance, junction-to-ambient °C/W
Soldered slug, 400-LFM airflow 17.4
RqJA (2) 7-mm × 7-mm 48-pin PDFP 25
RqJB Thermal resistance, junction-to-board 7-mm × 7-mm 48-pin PDFP 12 °C/W

(1) Determined using JEDEC standard JESD-51 with high-K board

(2) 16 layers, high-K board

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ELECTRICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
DC PARAMETERS
ICC Total supply current 360 mA
Power-down current 2 mA
IQ DEMODULATOR AND BASEBAND SECTION
fRF Frequency range 700 4000 MHz
Gain range 22 24 dB
Gain step See (1) 1 dB
Pinmax Max. RF power input Before damage 25 dBm
OIP3 Output third-order intercept point Gain setting = 24 (2) 30 dBVrms
P1dBmin Min. output compression point 1 tone (3) 3 dBVrms
Min. baseband low-pass filter cutoff
fmin 1–dB point (4) 700 kHz
frequency
Max. baseband low-pass filter cutoff
fmax 3–dB point (4) 15 MHz
frequency
fbypass Baseband low-pass filter cutoff frequency in
3–dB point (5) 30 MHz
bypass mode
1 × fC 1
1.5 × fC 8
Baseband relative attenuation at LPF cutoff 2 × fC 32
Fsel dB
frequency (fC) (6) 3 × fC 54
4 × fC 75
5 × fC 90
Image suppression –40 dB
Output BB attenuator 3 dB
Parallel resistance 1 kΩ
Output load impedance
Parallel capacitance 20 pF
Measured at I- and Q-channel
Vcm Output, common-mode 1.5 V
baseband outputs
Second harmonic (7) –100 dBc
Baseband harmonic level (7)
Third harmonic –93 dBc
LOCAL OSCILLATOR PARAMETERS
Local oscillator frequency 700 4000 MHz
(8)
LO input level See –3 0 6 dBm
LO leakage At MIXinn/p at 0-dBm LO drive level –58 dBm
DIGITAL INTERFACE
VIH High-level input voltage 0.6 × VCC 5 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage 0.8 × VCC V
VOL Low-level output voltage 0.2 × VCC V

(1) Two consecutive gain settings

(2) Two CW tones at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
(3) Single CW tone at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
(4) Baseband low-pass filter cutoff frequency is programmable through SPI register LPFADJ. LPFADJ = 0 corresponds to max bandwidth;
LPFADJ = 255 corresponds to minimum BW.
(5) Filter Ctrl setting equal to 0
(6) Attenuation relative to passband gain
(7) LO frequency set to 2.4 GHz. Power-in set to –40 dBm. Gain setting at 24. DC offset calibration engaged. Input signal set at 2.5-MHz
offset.
(8) LO power outside of this range is possible but may introduce degraded performance.

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ELECTRICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C (1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fLO = 700 MHz
Gmax Maximum gain (2) Gain setting = 24 50 dB
NF Noise figure Gain setting = 24 8.5 dB
IIP3 Third-order input intercept point Gain setting = 24 (3) (4) 14 dBm
IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 60 dBm
fLO = 1740 MHz
Gmax Maximum gain (2) Gain setting = 24 44 dB
NF Noise figure Gain setting = 24 11 dB
(3) (4)
IIP3 Third-order input intercept point Gain setting = 24 22 dBm
IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 60 dBm
fLO = 1950 MHz
Gmax Maximum gain (2) Gain setting = 24 43 dB
NF Noise figure Gain setting = 24 12 dB
IIP3 Third-order input intercept point Gain setting = 24 (3) (4) 23 dBm
IIP2 Second-order input intercept point Gain Setting = 24 (4) (5) 60 dBm
fLO = 2025 MHz
Gmax Maximum gain (2) Gain setting = 24 42.5 dB
N3F Noise figure Gain setting = 24 12.5 dB
(3) (4)
IIP3 Third-order input intercept point Gain setting = 24 22 dBm
IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 60 dBm
fLO = 2400 MHz
Gmax Maximum gain (2) Gain setting = 24 40 dB
NF Gain setting = 24 13.5 dB
Noise figure
Gain setting = 16 15 dB
IIP3 Third-order input intercept point Gain setting = 24 (3) (4) 24 dBm
IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 60 dBm

(1) For broadband frequency sweeps, the Picosecond balun (model #5310A) is used at the RF and LO input. For frequency band between
2100 MHz and 2700 MHz the Murata balun LDB212G4005C-001 is used. Performance parameters adjusted for balun insertion loss.
Recommended baluns for respective frequency band is shown below:
700 MHz: Murata LDB21897M005C-001 (or equivalent)
1740 MHz: Murata LDB211G8005C-001 (or equivalent)
1950 MHz: Murata LDB211G9005C-001 (or equivalent)
2025 MHz: Murata LDB211G9005C-001 (or equivalent)
2500 MHz: Murata LDB212G4005C-001 (or equivalent)
3500 MHz: Johanson 3600BL14M050E (or equivalent)
(2) Gain defined as voltage gain from Mixin (Vrms) to either baseband output: BBI/Qout (Vrms)
(3) Two CW tones of –30 dBm at fRF1 = fLO ±(2 × fC) and fRF2 = fLO ±[(4 × fC) + 100 kHz] (fC = baseband filter 1-dB cutoff frequency).
(4) Because the 2-tone interferers are outside of the baseband filter bandwidth, the results are inherently independent of the gain setting.
Intermodulation parameters are recorded at maximum gain setting, where measurement accuracy is best.
(5) Two CW tones at –30 dBm at fRF1 = fLO ±2 × fC and fRF2 = fLO ±[(2 × fC) + 100 kHz]; IM2 product measured at 100-kHz output frequency
(fC = baseband filter 1-dB cutoff frequency)

TIMING REQUIREMENTS
VCC = 5 V, LO power = 0 dBm, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(CLK) Clock period 50 ns
tsu1 Setup time, data 10 ns
th Hold time, data 10 ns
tw Pulse width, STROBE 20 ns
tsu2 Setup time, STROBE 10 ns

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TYPICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)

Table of Graphs
Gain vs LO frequency (1) (2) Figure 1, Figure 2, Figure 3
(1) (2)
Noise figure vs LO frequency Figure 4, Figure 5, Figure 6
IIP3 vs LO frequency (3) (4) (5) Figure 7, Figure 8, Figure 9
IIP2 vs LO frequency (3) (4) (5) Figure 10, Figure 11, Figure 12
Gain vs LO frequency Figure 13, Figure 14, Figure 15
IIP3 vs LO frequency (4) (5) Figure 16, Figure 17, Figure 18, Figure 19
IIP2 vs LO frequency (4) (5) Figure 20, Figure 21, Figure 22, Figure 23
(4) (5) (6)
Optimized IIP2 vs LO frequency Figure 24
Optimized IIP3 vs LO frequency (4) (5) (6) Figure 25
Noise figure vs LO frequency Figure 26, Figure 27, Figure 28
OIP3 vs Frequency offset (7) Figure 29, Figure 30, Figure 31, Figure 32
Noise figure vs BB gain setting Figure 33
Gain vs BB gain setting Figure 34
Gain vs Frequency offset Figure 35, Figure 36
Gain vs Frequency offset (bypass mode) Figure 37, Figure 38
1-dB LPF corner frequency vs LPFADJ setting Figure 39
Relative LPF group delay vs Frequency offset (8) Figure 40
Image rejection vs BB frequency offset Figure 41
DC offset limit vs Temperature (9) Figure 42
Out-of-band P1dB vs Relative offset multiplier to corner frequency (10) Figure 43

(1) Measured with broadband Picosecond 5310A balun on the LO input and single ended connection on the RF input. Performance gain
adjusted for the 3 dB differential to single-ended insertion loss.
(2) Performance ripple due to impedance mismatch on the RF input.
(3) Measured with broadband Picosecond 5310A balun on the LO input and RF input. Balun insertion loss is compensated for in the
measurement.
(4) Out-of-band intercept point is defined with tones that are at least 2 times farther out than the programmed LPF corner frequency that
generate an intermodulation tone that falls inside the LPF passband.
(5) Out-of-band intercept point is dependent on the demodulator performance and not the baseband circuitry; the measurement is taken at
max gain but is valid across all PGA settings.
(6) Optimized intercept point within the band 2.5 to 2.7 GHz is achieved by setting trim values Mix GM trim, Mix LO Trim, LO Trim, Mix Buff
Trim, Filter trim, Out Buff Trim to: 2, 3, 0, 1, 2, 1 respectively.
(7) Measured with filter in bypass mode to characterize the passband circuitry across baseband frequencies.
(8) Relative to the low frequency offset group delay in bypass mode.
(9) Idet set to 50 µA; RF signal is off; LO at 2.4 GHz at 0 dBm; Det filter set to 1 kHz; Clk Div set to 1024.
(10) In-band tone set to 1 MHz; out-of-band jammer tone set to specified relative offset ratio from the programmed corner frequency. Jammer
tone is increased until in-band tone compresses 1 dB.

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TYPICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)

GAIN vs LO FREQUENCY GAIN vs LO FREQUENCY

52 52
T A = −40°C VCC = 4.5V
50 T A = −10°C 50 VCC = 5V
T A = 25°C VCC = 5.5V
48 T A = 85°C 48

46 46
Gain (dB)

Gain (dB)
44 44

42 42

40 40

38 38

36 36
See Notes 1 and 2 See Notes 1 and 2
34 34
500 1000 1500 2000 2500 3000 3500 4000 500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G001
LO Frequency (MHz) G002

Figure 1. Figure 2.

GAIN vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY

52 22
LO Pwr = −3dBm T A = −40°C
50 LO Pwr = 0dBm 20 T A = −10°C
LO Pwr = 3dBm T A = 25°C
48 LO Pwr = 6dBm T A = 85°C
18
Noise Figure (dB)

46
16
Gain (dB)

44
14
42
12
40
10
38

36 8
See Notes 1 and 2 See Notes 1 and 2
34 6
500 1000 1500 2000 2500 3000 3500 4000 500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G003
LO Frequency (MHz) G004

Figure 3. Figure 4.

NOISE FIGURE vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY

22 22
VCC = 4.5V LO Pwr = −3dBm
20 VCC = 5 V 20 LO Pwr = 0dBm
VCC = 5.5V LO Pwr = 3dBm
18 18 LO Pwr = 6dBm
Noise Figure (dB)

Noise Figure (dB)

16 16

14 14

12 12

10 10

8 8
See Notes 1 and 2 See Notes 1 and 2
6 6
500 1000 1500 2000 2500 3000 3500 4000 500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G005
LO Frequency (MHz) G006

Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
36
TA = −40°C
34 TA = −10°C
32 TA = 25°C
TA = 85°C
30
28
26
IIP3 (dBm)

24
22
20
18
16
14
12
10
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 350 400
Q
36
34
32
30
28
26
IIP3 (dBm)

24
22
20
18
16
14
12
See Notes 3, 4 and 5
10
500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G007

Figure 7.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
VCC = 4.5V
32 VCC = 5V
VCC = 5.5V
30

28

26
IIP3 (dBm)

24

22

20

18

16

14

12
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 350 400
Q
34

32

30

28

26
IIP3 (dBm)

24

22

20

18

16

14
See Notes 3, 4 and 5
12
500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G008

Figure 8.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
LO Pwr = −3dB
32 LO Pwr = 0dB
LO Pwr = 3dB
30 LO Pwr = 6dB
28

26
IIP3 (dBm)

24

22

20

18

16

14

12
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 350 400
Q
34

32

30

28

26
IIP3 (dBm)

24

22

20

18

16

14
See Notes 3, 4 and 5
12
500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G009

Figure 9.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
TA = −40°C
TA = −10°C
90 TA = 25°C
TA = 85°C

80
IIP2 (dBm)

70

60

50

40

30
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 350 400
Q
100

90

80
IIP2 (dBm)

70

60

50

40

See Notes 3, 4 and 5

30
500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G010

Figure 10.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
VCC = 4.5V
VCC = 5V
90 VCC = 5.5V

80
IIP2 (dBm)

70

60

50

40

30
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 350 400
Q
100

90

80
IIP2 (dBm)

70

60

50

40

See Notes 3, 4 and 5

30
500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G011

Figure 11.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
LO Pwr = −3dB
LO Pwr = 0dB
90 LO Pwr = 3dB
LO Pwr = 6dB

80
IIP2 (dBm)

70

60

50

40

30
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 350 400
Q
100

90

80
IIP2 (dBm)

70

60

50

40

See Notes 3, 4 and 5

30
500 1000 1500 2000 2500 3000 3500 4000
LO Frequency (MHz) G012

Figure 12.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
GAIN vs LO FREQUENCY GAIN vs LO FREQUENCY
44 44
T A = −40°C VCC = 4.5V
43 T A = −10°C 43 VCC = 5V
T A = 25°C VCC = 5.5V
42 T A = 85°C 42

41 41
Gain (dB)

Gain (dB)
40 40

39 39

38 38

37 37

36 36
2100 2200 2300 2400 2500 2600 2700 2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G013
LO Frequency (MHz) G014

Figure 13. Figure 14.

GAIN vs LO FREQUENCY
44
LO Pwr = −3dBm
43 LO Pwr = 0dBm
LO Pwr = 3dBm
42 LO Pwr = 6dBm

41
Gain (dB)

40

39

38

37

36
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G015
Figure 15.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
TA = −40°C
32 TA = −10°C
TA = 25°C
30
TA = 85°C
28

26
IIP3 (dBm)

24
22

20

18

16
14

12

10
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
34
32

30
28

26
IIP3 (dBm)

24
22
20
18
16
14

12
See Notes 4 and 5
10
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G016

Figure 16.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
VCC = 4.5V
32 VCC = 5V
VCC = 5.5V
30

28

26
IIP3 (dBm)

24
22

20

18

16
14

12

10
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
34
32

30
28

26
IIP3 (dBm)

24
22
20
18
16
14

12
See Notes 4 and 5
10
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G017

Figure 17.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
LO Pwr = −3dB
32 LO Pwr = 0dB
LO Pwr = 3dB
30
LO Pwr = 6dB
28

26
IIP3 (dBm)

24
22

20

18

16
14

12

10
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
34
32

30
28

26
IIP3 (dBm)

24
22
20
18
16
14

12
See Notes 4 and 5
10
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G018

Figure 18.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
LPFADJ = 0
32 LPFADJ = 24
LPFADJ = 82
30
LPFADJ = 142
28

26
IIP3 (dBm)

24
22

20

18

16
14

12

10
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
34
32

30
28

26
IIP3 (dBm)

24
22
20
18
16
14

12
See Notes 4 and 5
10
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G019

Figure 19.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
TA = −40°C
TA = −10°C
90 TA = 25°C
TA = 85°C
80

70
IIP2 (dBm)

60

50

40

30

20
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
100

90

80

70
IIP2 (dBm)

60

50

40

30
See Notes 4 and 5
20
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G020

Figure 20.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
VCC = 4.5V
VCC = 5V
90 VCC = 5.5V

80

70
IIP2 (dBm)

60

50

40

30

20
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
100

90

80

70
IIP2 (dBm)

60

50

40

30
See Notes 4 and 5
20
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G021

Figure 21.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
LO Pwr = −3dB
LO Pwr = 0dB
90 LO Pwr = 3dB
LO Pwr = 6dB
80

70
IIP2 (dBm)

60

50

40

30

20
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
100

90

80

70
IIP2 (dBm)

60

50

40

30
See Notes 4 and 5
20
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G022

Figure 22.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
LPFADJ = 0
LPFADJ = 24
90 LPFADJ = 82
LPFADJ = 142
80

70
IIP2 (dBm)

60

50

40

30

20
2100 2200 2300 2400 2500 2600 2700
210 220 230 240 250 260 270
Q
100

90

80

70
IIP2 (dBm)

60

50

40

30
See Notes 4 and 5
20
2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G023

Figure 23.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
OPTIMIZED IIP2 vs LO FREQUENCY
W
I
90
TA = −40°C
85 TA = −10°C
TA = 25°C
80
TA = 85°C
75
Optimized IIP2 (dBm)

70

65
60

55

50

45
40

35

30
2500 2525 2550 2575 2600 2625 2650 2675 2700
250 2520 2550 2575 2600 2625 2650 2675 270
Q
90
85

80
75
Optimized IIP2 (dBm)

70

65
60
55
50
45
40

35
See Notes 4, 5 and 6
30
2500 2525 2550 2575 2600 2625 2650 2675 2700
LO Frequency (MHz) G024

Figure 24.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
OPTIMIZED IIP3 vs LO FREQUENCY
W
I
34
TA = −40°C
32 TA = −10°C
TA = 25°C
30 TA = 85°C
28
Optimized IIP3 (dBm)

26

24

22

20

18

16

14

12
2500 2525 2550 2575 2600 2625 2650 2675 2700
250 2520 2550 2575 2600 2625 2650 2675 270
Q
34

32

30

28
Optimized IIP3 (dBm)

26

24

22

20

18

16

14
See Notes 4, 5 and 6
12
2500 2525 2550 2575 2600 2625 2650 2675 2700
LO Frequency (MHz) G025

Figure 25.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
NOISE FIGURE vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY
20 20
T A = −40°C VCC = 4.5V
19 T A = −10°C 19 VCC = 5 V
18 T A = 25°C 18 VCC = 5.5V
T A = 85°C
17 17
Noise Figure (dB)

Noise Figure (dB)

16 16
15 15
14 14
13 13
12 12
11 11
10 10
2100 2200 2300 2400 2500 2600 2700 2100 2200 2300 2400 2500 2600 2700
LO Frequency (MHz) G026
LO Frequency (MHz) G027

Figure 26. Figure 27.

NOISE FIGURE vs LO FREQUENCY OIP3 vs FREQUENCY OFFSET

20 52
LO Pwr = −3dBm T A = −40°C
19 50 T A = 25°C
LO Pwr = 0dBm
18 LO Pwr = 3dBm 48 T A = 85°C
LO Pwr = 6dBm
17 46
Noise Figure (dB)

OIP3 (dBm)

16 44

15 42

14 40

13 38

12 36

11 34
See Note 7
10 32
2100 2200 2300 2400 2500 2600 2700 0 5 10 15 20 25
LO Frequency (MHz) G028
Frequency Offset (MHz) G029

Figure 28. Figure 29.

OIP3 vs FREQUENCY OFFSET OIP3 vs FREQUENCY OFFSET

52 50
VCC = 4.5V BB Gain = 12dB
50 VCC = 5V 48 BB Gain = 16dB
48 VCC = 5.5V BB Gain = 20dB
46 BB Gain = 24dB
46
44
OIP3 (dBm)

OIP3 (dBm)

44
42
42
40
40
38
38
36 36

34 34
See Note 7 See Note 7
32 32
0 5 10 15 20 25 0 5 10 15 20 25
Frequency Offset (MHz) G030
Frequency Offset (MHz) G031

Figure 30. Figure 31.

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
OIP3 vs FREQUENCY OFFSET NOISE FIGURE vs BB GAIN SETTING
50 28
3dB Attn On 3dB Attn On
48 3dB Attn Off 3dB Attn Off
46 25

Noise Figure (dB)

44
OIP3 (dBm)

22
42

40
19
38

36 16
34
See Note 7
32 13
0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 22 24
Frequency Offset (MHz) G032
BB Gain Setting G033

Figure 32. Figure 33.

GAIN vs BB GAIN SETTING GAIN vs FREQUENCY OFFSET

43 20
3dB Attn On
40 3dB Attn Off
0
37
34
-20
31
Gain (dB)

Gain (dB)

28 -40
25
-60
22
LPFADJ = 0
19 LPFADJ = 25
-80
16 LPFADJ = 85
LPFADJ = 142
13 -100
0 2 4 6 8 10 12 14 16 18 20 22 24 0.1 1 10 100
BB Gain Setting G034
Frequency Offset (MHz) G035

Figure 34. Figure 35.

GAIN vs FREQUENCY OFFSET GAIN vs FREQUENCY OFFSET

5 20
LPFADJ = 0
4 LPFADJ = 25
LPFADJ = 85 0
3
LPFADJ = 142
2
-20
1
Gain (dB)
Gain (dB)

0 -40
-1
-60
-2
Filter Ctrl 0
-3 Filter Ctrl 1
-80
-4 Filter Ctrl 2
Filter Ctrl 3
-5 -100
0.1 1 10 100 0.1 1 10 100 1000
Frequency Offset (MHz) G036
Frequency Offset (MHz) G037

Figure 36. Figure 37. Bypass Mode

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TYPICAL CHARACTERISTICS (continued)

VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
GAIN vs FREQUENCY OFFSET 1-dB LPF CORNER FREQUENCY vs LPFADJ SETTING
5 16
Filter Ctrl 0
4

1-dB LPF Corner Frequency (MHz)

Filter Ctrl 1 14
3 Filter Ctrl 2
Filter Ctrl 3 12
2
1 10
Gain (dB)

0 8
-1 6
-2
4
-3
-4 2

-5 0
0.1 1 10 100 0 50 100 150 200 250
Frequency Offset (MHz) G038
LPFADJ Setting G039

Figure 38. Bypass Mode Figure 39.

RELATIVE LPF GROUP DELAY vs FREQUENCY OFFSET IMAGE REJECTION vs BB FREQUENCY OFFSET
500 0
See Note 8 Bypass
LPFADJ = 0
400 -10
Relative LPF Group Delay (ns)

LPFADJ = 25
LPFADJ = 85
Image Rejection (dB)

LPFADJ = 142
300 -20

200 -30

100 -40

0 -50

-100 -60
0.1 1 10 100 -25 -20 -15 -10 -5 0 5 10 15 20 25
Frequency Offset (MHz) G040
BB Frequency Offset (MHz) G041

Figure 40. Figure 41.

DC OFFSET LIMIT vs TEMPERATURE OUT-OF-BAND P1dB vs

60
REL OFFSET MULTIPLIER to CORNER FREQUENCY
See Note 9 15
LPFADJ = 0
40 10 LPFADJ = 25
LPFADJ = 85
DC Offset Limit (mV)

Out-of-Band P1dB (dBm)

20 5 LPFADJ = 142

0
0
-5
-20 -10

-40 -15

-20
-60 See Note 10
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 -25
Temperature (°C) G042 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Relative Offset Multiplier to Corner Frequency G043

Figure 42. Figure 43.

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REGISTER INFORMATION

SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION

The TRF371125 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift
register. There are three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin
46). DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of CLOCK. STROBE is asynchronous
to CLOCK, and at its rising edge the data in the shift register is loaded into the selected internal register. The first
two bits (DB0–DB1) are the address to select the available internal registers.

READBACK Mode
The TRF371125 implements the capability to read back the content of the serial programming interface registers.
In addition, it is possible to read back the status of the internal DAC registers that are automatically set after an
auto dc-offset calibration. Each readback is composed by two phases: writing followed by the actual reading of
the internal data (see timing diagram in Figure 44).
During the writing phase, a command is sent to the TRF371125 to set it in readback mode and to specify which
register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into
the READBACK pin and can be read at the following falling edge (LSB first). The first clock after LE goes high
(end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the
READBACK pin.
tsu1 th t(CLK) t(CL)
t(CH)

st nd
1 32
CLOCK Write Write
CLOCK CLOCK
Pulse Pulse
Register Write

DB29 DB30 DB31 (MSB)

DB0 (LSB) DB1 DB2 DB3
DATA READBACK DATA READBACK DATA READBACK DATA
Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3
Bit 29 Bit 30 Bit 31

tsu2 tw

"End of Write
Latch Cycle"Pulse
Enable

nd st nd nd rd
32 1 2 32 33
CLOCK Write Read Read Read Read
CLOCK CLOCK CLOCK CLOCK CLOCK
Pulse Pulse Pulse Pulse Pulse
tsu2 tw
td
READBACK

"End of Write
STROBE Cycle" Pulse

READ READ
READBACK READBACK BACK BACK READBACK READBACK
DATA Data Bit 0 Data Data Data Bit 30 Data Bit 31
Bit 1 Bit 29

T0265-02

Figure 44. Serial Programming Timing Diagram

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Table 1. Register Summary (1)

Bit # Reg 1 Reg 2 Bit # Reg 3 Reg 5 Bit # Reg 0
Bit0 Bit0 Bit0
Bit1 Register address Register address Bit1 Register address Register address Bit1 Register address
Bit2 Bit2 Bit2
Bit3 Bit3 Bit3
SPI bank addr SPI bank addr SPI bank addr SPI bank addr SPI bank addr
Bit4 Bit4 Bit4
Bit5 PWD RF En auto-cal Bit5 Bit5
Mix GM trim ID
Bit6 NU Bit6 Bit6
Bit7 PWD buf Bit7 Bit7
ILoadA Mix LO trim
Bit8 P Bit8 Bit8
Bit9 NU Bit9 Bit9
IDAC for dc offset LO trim
Bit10 PWD DC OFF DIG Bit10 Bit10
Bit11 NU Bit11 Bit11 NU
Mix buf trim
Bit12 Bit12 Bit12
Bit13 Bit13 Bit13
ILoadB Fltr trim
Bit14 BB gain Bit14 Bit14
Bit15 Bit15 Bit15
Out buf trim
Bit16 Bit16 Bit16
Bit17 Bit17 Bit17
QDAC for dc offset
Bit18 Bit18 Bit18
Bit19 Bit19 Bit19
QLoadA DC offset Q DAC
Bit20 Bit20 Bit20
LPFADJ
Bit21 Bit21 Bit21
Bit22 Bit22 Bit22
IDet
Bit23 Bit23 Bit23
Bit24 Cal sel Bit24 NU Bit24
Bit25 DC detector Bit25 Bit25
QLoadB
Bit26 bandwidth CLK div ratio Bit26 Bit26
Bit27 Fast gain Bit27 Bit27
DC offset I DAC
Bit28 Gain sel Cal clk sel Bit28 Bit28
Bit29 Osc test Bit29 Bypass Bit29
Bit30 NU Osc trim Bit30 Bit30
Fltr ctrl
Bit31 En 3dB attn Bit31 Bit31

(1) Register 4 is not used.

Table 2. Register 1 Device Setup

REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 1
Bit1 ADDR<1> 0 Register address
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
SPI bank address
Bit4 ADDR<4> 0
Bit5 PWD_MIX 0 Mixer power down (Off = 1)
Bit6 NU 0 Not used
Bit7 PWD_BUF 1 Mixer out test buffer power down (Off = 1)
Bit8 PWD_FILT 0 Baseband filter power down (Off = 1)
Bit9 NU 0 Not used
Bit10 PWD_DC_OFF_DIG 1 DC offset calibration power down (Off = 1)

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Table 2. Register 1 Device Setup (continued)

REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION
Bit11 NU 1 Not used
Bit12 BBGAIN_0 1
Bit13 BBGAIN_1 1 Baseband gain setting. Default = 15. Range is from 0 (minimum gain
setting) to 24 (maximum gain setting). See the Application Information
Bit14 BBGAIN_2 1
section for more information on gain setting and fast gain control
Bit15 BBGAIN_3 1 options.
Bit16 BBGAIN_4 0
Bit17 LPFADJ_0 0
Bit18 LPFADJ_1 0
Bit19 LPFADJ_2 0
Bit20 LPFADJ_3 0 Sets programmable low-pass filter corner frequency. Range = 255
(lowest corner frequency) to 0 (highest corner frequency). Default value
Bit21 LPFADJ_4 0 is 128.
Bit22 LPFADJ_5 0
Bit23 LPFADJ_6 0
Bit24 LPFADJ_7 1
Bit25 EN_FLT_B0 0 Selects dc offset detector filter bandwidth.
Bit26 EN_FLT_B1 0 Setting {00, 01, 11} = {10 MHz, 10 kHz, 1 kHz}
Bit27 EN_FASTGAIN 0 Enable external fast-gain control
Bit28 GAIN_SEL 0 Fast-gain control multiplier bit (×2 = 1)
Bit29 OSC_TEST 0 Enables osc out on readback pin if = 1
Bit30 NU 0 Not used
Bit31 EN 3dB Attn 0 Enables output 3-dB attenuator

EN_FLT_B0/1: These bits control the bandwidth of the detector used to measure the dc offset during the
automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0
controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff
frequencies of the detector bandwidth are summarized in the following table (see the Application Information
section for more detail on the dc offset calibration and the detector bandwidth).

EN_FLT_B1 EN_FLT_B0 TYPICAL 3-dB CUTOFF FREQ NOTES

x 0 10 MHz Maximum bandwidth, bypass R, C
0 1 10 kHz Enable R
1 1 1 kHz Minimum bandwidth, enable R, C

Table 3. Register 2 Device Setup

REGISTER 2 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 0
Bit1 ADDR<1> 1 Register address
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
SPI bank address
Bit4 ADDR<4> 0
Bit5 EN_AUTOCAL 0 Enable autocal when = 1; reset to 0 when done.
Bit6 IDAC_BIT0 0
Bit7 IDAC_BIT1 0
Bit8 IDAC_BIT2 0
Bit9 IDAC_BIT3 0
I-DAC bits to be set during manual dc offset cal
Bit10 IDAC_BIT4 0
Bit11 IDAC_BIT5 0
Bit12 IDAC_BIT6 0
Bit13 IDAC_BIT7 1

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Table 3. Register 2 Device Setup (continued)

REGISTER 2 NAME RESET VALUE WORKING DESCRIPTION
Bit14 QDAC_BIT0 0
Bit15 QDAC_BIT1 0
Bit16 QDAC_BIT2 0
Bit17 QDAC_BIT3 0
Q-DAC bits to be set during manual dc offset cal
Bit18 QDAC_BIT4 0
Bit19 QDAC_BIT5 0
Bit20 QDAC_BIT6 0
Bit21 QDAC_BIT7 1
Bit22 IDET_B0 1 Set reference current for digital calibration; Settings {00 to 11}
Bit23 IDET_B1 1 = {50 µA to 200 µA}. Setting 00 = highest resolution.
Bit24 CAL_SEL 1 DC offset calibration select. 0 = manual cal; 1 = autocal.
Bit25 Clk_div_ratio<0> 0
Clk divider ratio. Setting {000 to 111} = {1, 8, 16, 128, 256, 1024, 2048,
Bit26 Clk_div_ratio<1> 0 16684}. A higher div ratio (slower clk) improves cal accuracy and
reduces speed.
Bit27 Clk_div_ratio<2> 0
Bit28 Cal_clk_sel 1 Select internal oscillator when 1, SPI clk when 0
Bit29 Osc_trim<0> 1
Internal oscillator frequency trimming; Setting {000} = ~300 kHz;
Bit30 Osc_trim<1> 1
Setting {111} = ~1.8 MHz. Nominal setting {110} = ~900 kHz.
Bit31 Osc_trim<2> 0

Table 4. Register 3 Device Setup

REGISTER 3 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 1
Bit1 ADDR<1> 1 Register address
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
SPI bank address
Bit4 ADDR<4> 0
Bit5 ILOAD_a<0> 0
Bit6 ILOAD_a<1> 0
Bit7 ILOAD_a<2> 0
I mixer offset side A
Bit8 ILOAD_a<3> 0
Bit9 ILOAD_a<4> 0
Bit10 ILOAD_a<5> 0
Bit11 ILOAD_b<0> 0
Bit12 ILOAD_b<1> 0
Bit13 ILOAD_b<2> 0
I mixer offset side B
Bit14 ILOAD_b<3> 0
Bit15 ILOAD_b<4> 0
Bit16 ILOAD_b<5> 0
Bit17 QLOAD_a<0> 0
Bit18 QLOAD_a<1> 0
Bit19 QLOAD_a<2> 0
Q mixer offset side A
Bit20 QLOAD_a<3> 0
Bit21 QLOAD_a<4> 0
Bit22 QLOAD_a<5> 0

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Table 4. Register 3 Device Setup (continued)

REGISTER 3 NAME RESET VALUE WORKING DESCRIPTION
Bit23 QLOAD_b<0> 0
Bit24 QLOAD_b<1> 0
Bit25 QLOAD_b<2> 0
Q mixer offset side B
Bit26 QLOAD_b<3> 0
Bit27 QLOAD_b<4> 0
Bit28 QLOAD_b<5> 0
Bit29 Bypass 0 Engage filter bypass
Bit30 Fltr Ctrl_b<0> 1 Used to adjust for filter peaking response; set to 0 in bypass mode, 1
Bit31 Fltr Ctrl_b<1> 0 otherwise

I/Q Mixer Load A/B: these bits adjust the load on the mixer output. All values should be 0. No modification is
necessary.
Register 4: No programming required for Register 4

Table 5. Register 5 Device Setup

REGISTER 5 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 1
Bit1 ADDR<1> 0 Register address
Bit2 ADDR<2> 1
Bit3 ADDR<3> 1
SPI bank address
Bit4 ADDR<4> 0
Bit5 MIX_GM_TRIM<0> 1
Mixer gm current trim
Bit6 MIX_GM_TRIM<1> 0
Bit7 MIX_LO_TRIM<0> 1
Mixer switch core VCM trim
Bit8 MIX_LO_TRIM<1> 0
Bit9 LO_TRIM<0> 1
LO buffers current trim
Bit10 LO_TRIM<1> 0
Bit11 MIX_BUFF_TRIM<0> 1
Mixer output buffer current trim
Bit12 MIX_BUFF_TRIM<1> 0
Bit13 FLTR_TRIM<0> 1
Filter current trim
Bit14 FLTR_TRIM<1> 0
Bit15 OUT_BUFF_TRIM<0> 1
Filter output buffer current trim
Bit16 OUT_BUFF_TRIM<1> 0
Bit17 0
Bit18 0
Bit19 0
Bit20 0
Bit21 0
Bit22 0
Bit23 0
Bit24 NU 0 Not used
Bit25 0
Bit26 0
Bit27 0
Bit28 0
Bit29 0
Bit30 0
Bit31 0

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Trims: the trim values allow for minor bias adjustments of internal stages. Generally it is recommended to leave
all trim values at the default value of 1. Linearity performance improvement over a small band of frequencies is
possible by selective adjustment of the trim values. Optimized intercept point within the band 2.5 GHz to 2.7 GHz
is achieved by setting trim values Mix GM trim, Mix LO Trim, LO Trim, Mix Buff Trim, Filter Trim, Out Buff Trim to:
2, 3, 0, 1, 2, 1, respectively.
Readback (Write Command)

0 0 0 1 0 Zero Fill
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
Zero fill Register address 1
Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31

Reg 0:DAC/Device ID Readback

Register Address SPI Bank Addr ID NU

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
DC offset Q DAC DC offset I DAC
Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31

Table 6. Register 0 Device Setup (Read-Only)

READBACK REGISTER NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 0
Bit1 ADDR<1> 0 Select SPI reg 1 to 5
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Select SPI bank 1 to 3
Bit4 ADDR<4> 0
Bit5 ID<0> 1
Version ID: 01 = –25
Bit6 ID<1> 0
Bit7 0
Bit8 0
Bit9 0
Bit10 0
Bit11 NU 0 Not used
Bit12 0
Bit13 0
Bit14 0
Bit15 0
Bit16 DC_OFFSET_Q<0> 0
Bit17 DC_OFFSET_Q<1> 0
Bit18 DC_OFFSET_Q<2> 0
Bit19 DC_OFFSET_Q<3> 0
DC offset DAC Q register
Bit20 DC_OFFSET_Q<4> 0
Bit21 DC_OFFSET_Q<5> 0
Bit22 DC_OFFSET_Q<6> 0
Bit23 DC_OFFSET_Q<7> 1

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Table 6. Register 0 Device Setup (Read-Only) (continued)

READBACK REGISTER NAME RESET VALUE WORKING DESCRIPTION
Bit24 DC_OFFSET_I<0> 0
Bit25 DC_OFFSET_I<1> 0
Bit26 DC_OFFSET_I<2> 0
Bit27 DC_OFFSET_I<3> 0
DC offset DAC I register
Bit28 DC_OFFSET_I<4> 0
Bit29 DC_OFFSET_I<5> 0
Bit30 DC_OFFSET_I<6> 0
Bit31 DC_OFFSET_I<7> 1

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APPLICATION INFORMATION

Gain Control
The TRF371125 integrates a baseband programmable-gain amplifier (PGA) that provides 24 dB of gain range
with 1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 1 bits<12,16>). Alternatively,
the PGA can be programmed by a combination of 5 bits programmed through the SPI and 3 parallel external bits
(pins Gain_B2, Gain_B1, Gain_B0). The external bits are used to reduce the PGA setting quickly without having
to reprogram the SPI registers. The fast gain control multiplier bit (register 1, bit 28) sets the step size of each bit
to either 1 dB or 2 dB. This allows a fast gain reduction of 0 dB to 7 dB in 1-dB steps or 0 dB to 14 dB in 2-dB
steps.
The PGA gain control word (BBgain<0,4>) can be programmed to a setting between 0 and 24. This word is the
SPI programmed gain (register 1 bits<12,16>) minus the parallel external 3 bits as shown in Figure 45. Note that
the PGA gain setting rails at 0 and does not go any lower. Typical applications set the nominal PGA gain setting
to 17 and use the fast-gain control bits to protect the analog-to-digital converter in the event of a strong input
jammer signal.

Composite
SPI + PGA Setting
(min: 0, max 24)

X
Fast Gain Select (x1, x2)
Gain_B1
Gain_B2
Gain_B0

B0386-01

Figure 45. PGA Gain Control Word

For example, if a PGA gain setting of 19 is desired, then the SPI can be programmed directly to a value of 19.
Alternatively, the SPI gain register can be programmed to 24 and the parallel external bits set to 101 (binary)
corresponding to 5-dB reduction.

Automated DC Offset Calibration

The TRF371125 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q
paths. The internal calibration requires a clock in order to function. The TRF371125 can use the internal
relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method, which is
selected by setting the Cal_Sel_Clk (register 2, bit 28) to 1. The internal oscillator frequency is set through the
Osc_Trim bits (register 2, bits <29,31>). The frequency of the oscillator is detailed in Table 7; however, it is
expected the actual frequency of operation can vary plus or minus 35% due to process variations. The oscillator
frequency can be monitored on the READBACK pin when the Osc_Test register (Register 1, bit 29) is set to 1.

Table 7. Internal Oscillator Frequency Control

Osc_Trim<2> Osc_Trim<1> Osc_Trim<0> FREQUENCY
0 0 0 300 kHz
0 0 1 500 kHz
0 1 0 700 kHz
0 1 1 900 kHz
1 0 0 1.1 MHz
1 0 1 1.3 MHz
1 1 0 1.5 MHz
1 1 1 1.8 MHz

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The default setting of these registers corresponds to a 900-kHz oscillator frequency. This is sufficient for
autocalibration; modification is not required except for faster calibration convergence.
The output full-scale range of the internal dc offset correction DACs is programmable (IDET_B<0,1, register 2
bit<22,23>). The range is shown in Table 8.

Table 8. DC Offset Correction DAC Programmable Range

I(Q) Det_B0 I(Q) Det_B1 Full Scale
0 0 50 µA
0 1 100 µA
1 0 150 µA
1 1 200 µA

The I- and Q-channel output maximum dc offset correction range can be calculating by multiplying the values in
the table by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed
maximum correction range. For optimum resolution and best correction, the dc offset DAC range should be set to
50 µA with the PGA gain set for the nominal condition. The dc offset correction DAC output is affected by a
change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGA gain
during normal operation does not significantly impair the dc offset balance. For example, if the optimized
calibration yields a dc offset balance of 2 mV at a gain setting of 17, then the dc offset maintains less than 10 mV
balance as the gain is adjusted ±7 dB.
The dc offset correction DACs are programmed from the internal registers when the AUTO_CAL bit (register 2,
bit 24) is set to 1. At start-up, the internal registers are loaded at half scale corresponding to a decimal value of
128. The auto-cal is initiated by toggling the EN_AUTOCAL bit (register 2, bit 5) to 1. When the calibration is
over, this bit is automatically reset to 0. During calibration, the RF local oscillator must be applied. The dc offset
DAC state is stored in the internal registers and maintained as long as the power supply is kept on or until a new
calibration is started.
The required clock speed for the optimum calibration is determined by the internal detector behavior (integration
bandwidth, gain, sensitivity). The input bandwidth of the detector can be adjusted by changing the cutoff
frequency of the RC low-pass filter in front of the detector (register 1, bits 25–26). EN_FLT_B0 controls the
resistor (bypass = 1) and EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff frequencies of
the detector bandwidth are summarized in Table 9. The speed of the clock can be slowed down by selecting a
clock divider ratio (register 2, bits 25–27).

Table 9. Detector Bandwidth Settings

EN_FLT_B1 EN_FLT_B0 TYPICAL 3-dB CUTOFF FREQUENCY NOTES
X 0 10 MHz Maximum bandwidth, bypass R, C
0 1 10 kHz Enable R
1 1 1 kHz Minimum bandwidth, enable R, C

The detector has more averaging time with a slower clock; hence, it is desirable to slow down the clock speed for
a given condition to achieve optimum results. For example, if there is no RF present on the RF input port, the
detection filter can be left wide (10 MHz) and the clock divider can be left at div-by-128. The autocalibration
yields a dc offset balance between the differential baseband output ports (I and Q) that is less than 15 mV. Some
minor improvement may be obtained by increasing the averaging of the detector by increasing the clock divider
up to 256 or 1024.
On the other hand, if there is a modulated RF signal present at the input port, it is desirable to reduce the
detector bandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1-kHz
corner frequency. With the modulated signal present and with the detection bandwidth reduced, additional
averaging is required to get the optimum results. A clock divider setting of 1024 will yield optimum results.
Of course, an increase in the averaging is possible by increasing the clock divider at the expense of longer
converging time. The convergence time can be calculated by the following:
(Auto_Cal_Clk_Cycles) ´ (Clk_Divider)
tc =
Osc_Freq (1)

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The dc offset calibration converges in approximately nine cycles. For the case with a clock divider of 1024 and
with the nominal oscillator frequency of 900 kHz, the convergence time is:
(9) ´ (1024)
tc = = 10.24 ms
900 kHz (2)

Alternate Method for Adjusting DC Offset

The internal registers controlling the internal dc current DAC are accessible through the SPI, providing a user-
programmable method for implementing the dc offset calibration. To employ this option the CAL_SEL bit must be
set to 0. During this calibration, an external instrument monitors the output dc offset between the I/Q differential
outputs and programs the internal registers (IDAC_BIT<0,7> and QDAC_BIT<0,7> bits) to cancel the dc offset.

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PCB Layout Guidelines

The TRF371125 device is fitted with a ground slug on the back of the package that must be soldered to the PCB
ground with adequate ground vias to ensure a good thermal and electrical connection. The recommended via
pattern and ground pad dimensions are shown in Figure 46. The recommended via diameter is 8 mils (0.2 mm).
The ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground.
Additional ground vias may be added if space allows. The no-connect (NC) pins can also be tied to the ground
plane.
Decoupling capacitors at each of the supply pins is recommended. The high-frequency decoupling capacitors for
the RF mixers (VCCMIX) should be placed close to their respective pins. The value of the capacitor should be
chosen to provide a low-impedance RF path to ground at the frequency of operation. Typically, this value is
around 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close to their
respective pins as possible.
The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCB
layout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. The I/Q
output traces should be routed as differential pairs and their lengths all kept equal to each other. Decoupling
capacitors for the supply pins should be kept symmetrical where possible. The RF differential input lines related
to the RF input and the LO input should also be routed as differential lines with their respective lengths kept
equal. If an RF balun is used to convert a single-ended input to a differential input, then the RF balun should be
placed close to the device. Implement the RF balun layout per the manufacturer’s guidelines to provide best gain
and phase balance to the differential outputs. On the RF traces, maintain proper trace widths to keep the
characteristic impedance of the RF traces at a nominal 50 Ω.
0.200 (5.08)
0.025 (0.635)
Ø0.008 (0.203)

0.025 (0.635)

0.0125 (0.318)
0.200 (5.08)

Note: Dimensions are in inches (mm)

M0177-01

Figure 46. PCB Layout Guidelines

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Application Schematic
The typical application schematic is shown in Figure 47. The RF bypass capacitors and coupling capacitors on
the supply pins should be adjusted to provide the best high-frequency bypass based on the frequency of
operation.
To Microcontroller
To Microcontroller

READBACK
STROBE
MIXIoutp

MIXIoutn

Gain_B0
Gain_B1
Gain_B2
CLOCK
DATA

NC
NC

NC
48 47 46 45 44 43 42 41 40 39 38 37
GNDDIG 1 36 VCCBBI
VCCDIG 2 35 GND
CHIP_EN 3 34 BBIoutn
To ADC I
VCCMIX1 4 33 BBIoutp
GND 5 32 GND
RFin MIXinp 6 31 LOip LOin
TRF371125
MIXinn 7 30 LOin
GND 8 29 VCCLO
VCCMIX2 9 28 BBQoutp
To ADC Q
NC 10 27 BBQoutn
NC 11 26 GND
GND 12 25 VCCBBQ
13 14 15 16 17 18 19 20 21 22 23 24
MIXQoutn

VCCBIAS
GNDBIAS
GND
GND
GND
MIXQoutp

NC
NC

NC
VCM
REXT

30 kW

Figure 47. TRF371125 Application Schematic

The RF input port and the RF LO port require differential input paths. Single-ended RF inputs to these ports can
be converted with an RF balun that is centered at the band of interest. Linearity performance of the TRF371125
is dependent on the amplitude and phase balance of the RF balun; hence, care should be taken with the
selection of the balun device and with the RF layout of the device. The recommended RF balun devices are
listed in Table 10.

Table 10. RF Balun Devices

MANUFACTURER PART NUMBER FREQUENCY RANGE UNBALANCE IMPEDANCE BALANCE IMPEDANCE
Murata LDB21897M005C-001 897 MHz ±100 MHz 50 Ω 50 Ω
Murata LDB211G8005C-001 1800 MHz ±100 MHz 50 Ω 50 Ω
Murata LDB211G9005C-001 1900 MHz ±100 MHz 50 Ω 50 Ω
Murata LDB212G4005C-001 2.3 GHz to 2.7 GHz 50 Ω 50 Ω
Johanson 3600BL14M050E 3.3 GHz to 3.8 GHz 50 Ω 50 Ω

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Application for a High-Performance RF Receiver Signal Chain

The TRF371125 is the centerpiece component in a high performance direct downconversion receiver. The device
is a highly integrated direct downconversion demodulator that requires minimal additional devices to complete
the signal chain. A signal chain block diagram example is shown in Figure 48.

ADS62P42 TRF371125

14
0
90 LNA

14

TRF3761

Figure 48. Block Diagram of Direct Downconvert Receiver

The lineup requires a low-noise amplifier (LNA) that operates at the frequency of interest with typical 1- to 2-dB
noise figure (NF) performance. An RF band-pass filter (BPF) is selected at the frequency band of interest to
eliminate unwanted signals and images outside the band from reaching the demodulator. The TRF371125
incorporates the direct downconvert demodulation, baseband filtering, and baseband gain-control functions. An
external synthesizer, such as the TRF3761, is used to provide the local oscillator (LO) source to the TRF371125.
The differential outputs of the TRF3761 directly mate with LO input of the TRF371125. The quadrature outputs
(I/Q) of the TRF371125 directly drive the input to the analog-to-digital converter (ADC). A dual ADC like the
ADS62P42 14-bit 65-MSPS ADC mates perfectly with the differential I/Q output of the TRF371125. The
baseband output pins (pins 27, 28, 33, 34) can be connected directly to the corresponding input pins of typical
ADCs. The positive and negative terminal connections between the TRF371125 and the ADC can be swapped to
facilitate a clean routing layout. The swapped connection can be reversed by flipping the signals in the digital
domain, if desired. In addition, the common-mode output voltage generated by the ADC is fed directly into the
common-mode port (pin 24) to ensure the optimum dynamic range of the ADC is maintained.

EVALUATION TOOLS
An evaluation module is available to test the TRF371125 performance. The TRF371125EVM can be configured
with different baluns to enable operation in various frequency bands. The TRF371125EVM is available for
purchase through the Texas Instruments web site at www.ti.com.

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REVISION HISTORY

Changes from Revision A (March, 2010) to Revision B Page

• Corrected y-axis value in Figure 29 .................................................................................................................................... 27

• Corrected y-axis value in Figure 30 .................................................................................................................................... 27
• Corrected y-axis value in Figure 31 .................................................................................................................................... 27
• Corrected y-axis value in Figure 32 .................................................................................................................................... 27

Changes from Original (January, 2010) to Revision A Page

• Corrected product name discussed throughout document ................................................................................................... 1

• Added Evaluation Tools ...................................................................................................................................................... 42

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 43

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 PACKAGE OPTION ADDENDUM

www.ti.com 23-Apr-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TRF371125IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 TRF
371125IRGZ
TRF371125IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 TRF
371125IRGZ

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-Apr-2022

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TRF371125IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TRF371125IRGZR VQFN RGZ 48 2500 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RGZ 48 VQFN - 1 mm max height
7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224671/A

www.ti.com
 PACKAGE OUTLINE
RGZ0048D SCALE 1.900
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

7.1 A
B
6.9

0.5
0.3
PIN 1 INDEX AREA

7.1
6.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL

1.0
0.8
C

SEATING PLANE
0.05
0.00 0.08 C

5.6 0.1
2X 5.5
(0.2) TYP
13 24
44X 0.5
12
25

EXPOSED
THERMAL PAD

2X 49 SYMM
5.5

SEE TERMINAL
DETAIL

1 36
0.30
48X
48 37 0.18
PIN 1 ID SYMM 0.1 C A B
(OPTIONAL) 0.5
48X 0.05
0.3

4219046/B 11/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGZ0048D VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 5.6)
SYMM
48 37
48X (0.6)

1
36

48X (0.24)
6X
(1.22)

44X (0.5)
10X
(1.33)
49
SYMM

(6.8)

(R0.05)
TYP

( 0.2) TYP
VIA
12 25

13 24
10X (1.33) 6X (1.22)
(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:12X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING
EXPOSED METAL

EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219046/B 11/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RGZ0048D VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.665 TYP) (1.33) TYP

16X ( 1.13)
48 37
48X (0.6)
49
1
36

48X (0.24)

44X (0.5) (1.33)

TYP

(0.665)
SYMM TYP

(6.8)

(R0.05) TYP

12 25

METAL
TYP
13 24
SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X

4219046/B 11/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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