Course Content Overview
MOSFET physics (W1)
Short channel effect (W2)
Advanced Devices module:(W2-W5)
Multi-Gate device structure
FinFet and Gate all-around
High-k materials + metal gate
Strained technology
Silicide process and RSD
High mobility Channel
Process integration (W6)
Future device candidates (W6)
Gate
Si
Planar FinFET Gate-all-around
1
Device Improvement
Ion=W/LG * Cox * (Vdd-Vtgm))2 * F(Rsd, )
Cox
• High-k materials + metal gate
• Metal gate – gate depletion
Gate Control (Vtgm, DIBL)
• Short channel control
• Minimize off-state D/S leakage
• Multi-gate
Mobility enhancement
• Strained technology
S/D parasitic resistance
• Abrupt-Raise LDD, Raise S/D, advanced anneal
• Metal Schottky S/D
2
Strain Techniques
Universal (surface) Mobility Put mechanical stresses on the
MOSFET, the universal mobility
can increase (or decrease).
Preferred mechanical stresses
for nMOSFET (electrons) and
pMOSFET (holes)
General guide:
Tensile stress for NFET
Compressive stress for PNFET
un-strained Si (without stress)
With mechanical stress
1 W
I DS COX (VGS Vt ) 2
3 2 L
Strain Techniques
Tensile stress:
Change atom arrangement μ
1 W
I DS COX (VGS Vt ) 2
2 L
General guide:
Tensile stress NFET ;
4
compressive PFET
Substrate-Induced Strain –Global Strain
5 K.Rim, VLSI-01& J.L.Hoyt, IEDM-02
Sub-band Engineering
2
E E0
(k x2 k y2 k z2 )
2m
Lower conductivity mass (0.19m0) Higher conductivity mass (0.315m0)
– High mobility – Low mobility
Higher mz (0.916m0) Lower mz (0.19m0)
• Thinner inversion layer – Thicker inversion layer
• Lower subband energy – Higher subband energy
6
Mobility Enhancement
Strain-induced band splitting
Strained-Si MOSFETs Takagi, IEDM 1997
Strain induces larger energy splits between
(sub)bands/valleys.
Increase in energy split between 2-fold and 4-
fold valleys enhances mobility.
Electrons in 4-fold valleys are transferred
to 2-fold valleys.
The average conductivity mass is reduced.
Inter-valley scattering between 2-fold and
4-fold valley is suppressed.
7
Desired Stress for CMOS Devices
Stress engineering is
NMOS PMOS mainly applied to (or along)
this Longitudinal direction.
Longitudinal(X) Tensile Compressive
Be aware of the Lateral
Lateral(Y) Tensile Tensile
and Si-Depth (vertical)
Si-Depth Compressive Tensile directions, but no
engineering efforts.
desired nFET stress
longitudinal
Si-depth(or vertiacl)
desired pFET stress
8
Lattice Mismatched S/D Technology
During epi-growth
lattice constant
Room temp.
Ge atoms exert a large stress on the near-
by Si, due to the slightly larger lattice
constant a0.
Compressive stress to the channel.
Carbon has a smaller a0 than Si, so emb-
SiC has tensile stress.
9
PMOS S/D Strain Technology-SiGe
Ge Content in SiGe S/D for P-FET
Scalable to pure Ge?
Intel 45nm
[Ge] is limited to within ~50-60%.
[Ge] ↑ dislocations
Stress relaxation
Junction leakage
10
Embedded SiGe
S/D laterally compresses channel (SiGe has
higher lattice constant than Si)
Embedded SiGe is the most important
stressor for pFET
Etch source /drain recess
Grow SiGe epitaxially
in recessed regions
Build source/drain
regions & deposit
Factors that can shift a “universal curve”:
1) Tox, 2) RSD, 3) Weff, 4) SCE, 5)mobility
11
Embedded-SiGe for pFET
2003 2005 2007 2009 2011 2014 2017 2018 2020
90nm 65nm 45nm 32nm 22nm 14nm 10nm 7nm 5nm
Invented 2nd Gen.
Invented 2nd Gen. First to
Gate-Last Gate-Last
SiGe SiGe Implement
High-k High-k
Strained Silicon Strained Silicon Tri-Gate
Metal Gate Metal Gate
SiGe on p-FinFET
Rounded “U-shaped” SiGe Sharp “Diamond-shaped” SiGe on p-FinFET
SiP (or SiAs) on n-FinFET
(or “D-shaped”) SiGe
Process for the emb-SiGe implementation:
Recess dimensions & shape (rounded vs. “diamond”), [Ge]%
and profile, [B] profile, dislocation
Device parameters:
Hole mobility, S/D resistance, junction leakage, SCE, body
effect, Ion vs. Ioff.
The U-shape or D-shape S/D Si recess region
For FinFET technologies, the epi-SiGe over the Si fin is usually
12
Diamond shaped as well, but it’s not the same as the above.
pFET Emb-SiGe: Shape Effect
U-shaped embedded-SiGe for pMOS Dimond-shaped (D-shaped) embedded-SiGe.
U-shaped vs D-shaped emb-SiGe:
Ioff (normalized)
D-shaped 10% ION gain for pMOS
Hole mobility enhancement (by ≳20%).
Mechanical stress decays with increasing
28LP distance. Proximity and Shape of SiGe
are critical
D-shaped SiGe can exert stress closer to
the channel (than U-shaped), and thus
have higher hole mobility (and ION ).
Ion (normalized)
13
NMOS S/D Strain Technology-SiC
Silicon-Carbon Region Interacts with Adjacent Si Channel.
Strain in the Si channel is compressive in vertical direction and
tensile in horizontal direction.
Lateral Tension
In the Channel
14
Planar Transistors with Si:C S/D
Drive Current Enhancement (10 – 20%) was
observed for SiC S/D.
15
Scaling Trend
At 32nm node, stress enhances hole mobility by 3.5x
SiGe plays a key role in PMOS
Si:C is used in NMOS, but is less efficient
Strain was first introduced at 90nm, and its contribution
has increased in each subsequent generation.
16 Kelin Kuhn / CNNA / Berkeley / 2010
STI-Induced Strain
Due to the different thermal expansion
coefficients between Si and STI, there
exists biaxial compressive residual
stress in the active region after processing.
STI-stress generally increases PMOS
current and decreases NMOS current.
Stress relaxes exponentially with
increased distance from Si/STI
boundary.
17
Stress Memorization Technique (SMT)
Longitudinal tensile
+ Vertical Compressive stress
Good for NMOS mobility
Missing (i.e. vacancy) {111}
plane due to SMT for a
30nm deep amorphized Si
•~350 Mpa tensile
longitudinal stress is
present in the channel
Tensile SiN is usually hydrogen-rich. A post-deposition
anneal can drive out the excessive hydrogen, and the
SiN will shrink (and become tensile). 18
Stress Memorization Technique (SMT)
The stress effect is transferred to the channel during the
front-end processing.
There is no permanent layer on the devices, therefore there
is no layout dependence.
It enhances electron mobility for NMOS devices.
Amorphize poly & Anneal to make nitride more
diffusion with silicon tensile and transfer nitride
implant (n-FET areas) tension to crystallizing
amorphous diffusion
Deposit tensile nitride, Remove nitride stressor
remove it from the p- (tension now frozen in
FET areas diffusion)
SMT Process (for planar NFET only): Annealing process transfer the
tensile stress from SiN to n-FET S/D areas, after removing, the tensile stress
remains in the underlying n-FET (as if the stress is “memorized”). Thus it is
called “Stress Memorization Technique.”
S/D implant to pre-amorphize the surface before the tensile-SiN deposition,
so that the stress can be better transferred and memorized during the re-
19
crystallization anneal.
Mechanical Stress Sources
Thin spacers (SPT, Stress Proximity Technique)
Compressive Nitride Liner Tensile Nitride Liner
STI STI STI
PMOS NMOS
Embedded SiGe SMT (Stress Memorization Technique) (for planar n-FET)
Embedded-SiP (for n-FinFET)
Techniques of process induced
Improves
stress
Embedded SiGe in S/D pFET
Stress Memorization Technique(SMT) nFET
Single Stress Liner (SSL) nFET
all SSL uses tensile
Dual Stress Liner (DSL) nFET & pFET SiN to help nFET.
DSL+eSiGe nFET & pFET
Stress Proximity Technique for DSL
nFET & pFET
(SPT)
20
Contact Etch Stop Layer (CESL)
NMOS:
Longitudinal tensile
PMOS:
Longitudinal
compressive
Isat enhancement of 11%/20%.
H.-S. Yang, IEDM (2004)
21
Mechanical Stress Sources
Thin spacers (SPT, Stress Proximity Technique)
Compressive
Nitride Liner Tensile Nitride Liner
Dual Stress
Liner (DSL) STI STI STI
PMOS NMOS
SMT (Stress Memorization Technique)
Embedded SiGe
SPT (Stress Proximity Technique)
Tensile
Nitride Liner Tensile Nitride Liner
Single Stress
Liner (SSL)
STI STI STI
PMOS NMOS
Embedded SiGe SMT (stress memorization technique)
For DSL process, the stress liners
Stress Technique N-MOSFET P-MOSFET
overlap or underlap, can cause yield
SMT loss.
Emb-SiGe Emb-SiGe is very effective for pFET,
and thus pFET can live with the
SPT(Stress Proximity)
tensile stress liner (SSL), which
DSL marginally reduces the compressive
22 SSL (Tensile SiN) stress but not by much.
Incorporate DSL (Dual Stress Liner)
Compressive SiN dep /
SPT etch away on nFET
DSL
Thin etch-stop oxide dep
(not drawn)
Tensile SiN dep
Etch away on pFET
DSL is ideal for enhancing both electron and hole mobility.
There is a “fence” along the DSL boundary, which can
cause yield loss due to process and topology issues.
To avoid this problem, most people use tensile SSL and
compromise some p-FET ION.
23
The Effects of SMT & CESL (contact
etch stop layer):
SMT (Stress Memorization Technique)
is used for nFET.
A single tensile SiN as CESL (contact
etch stop layer) is often used to benefit
nFET (called SSL, or single stress liner)
SSL is good for nFET, but not for pFET
(it degrades pFET by ~10-12%,
△ Considered acceptable, emb-SiGe
can boost pFET Ion by >30-40%.)
DSL (dual stress liner) optimizes
performance for both n & pFET, but
have process and topology related
issues SSL is widely used.
24
Stress Proximity Technique (SPT)
Conventional
DSL(w/o SPT)
DSL with SPT
Large spacers will block the stress from CESL (SSL or DSL) to
reach the gate area.
SPT is to thin down the spacers (remove spacer2, and leave only
spacer1 ) to make the stress liner more effective.
Spacer2 and spacer1 must use different material, usually nitride
and oxide, respectively, so that there is an etch selectivity. (e.g.
25 use hot phosphorus acid to remove SiN, and stop on SiO2)
Spacer Proximity Technique (SPT)
Spacer 1 (only) (Spacer 2 removed)
Spacer 1 (SiO2) with SPT
with SPT
Spacer 2 (SiN)
26
Effects of SPT (Spacer Proximity)
Amount of stress is dependent on the
spacer thickness.
Thinner spacer allows higher stress
on channel needs SPT !
Linear region (small VD):
ID = µCox W/L (VG–VT) VD
R = VD / ID = L /(µCox W (VG–VT))
Slope ∝ 1/µ
Smaller slope higher µ
27
Effects of SPT and DSL (on nFET)
NFET also benefits from SPT, though not as effective (only
28
3% gain) as PFET.
Effects of SPT and DSL (on pFET)
SPT contributes 20%
pFET Ion gain !
Fig.12 Id-Vg and Id-Vd curves of PFET w. And w/o SPT.
29
Contacted Poly Pitch (CPP)
30 Aaron Thean, IEDM 2016 short course
Strain: Pitch Dependence
31 Kelin Kuhn / CNNA / Berkeley / 2010
Beyond 10nm node: Scaling scenario’s
Scaling the CGP and fin pitch
Scaling from one node to the next
→scaling gate length (LG), contacted poly pitch (CGP), fin pitch
Node CGP(=CPP)
10nm 58~60nm
7nm 40nm
5nm 28~29nm
Scaling CGP (contacted poly pitch)
CPP (contacted poly pitch) = CGP Scaled CPP (or CGP)
Node CGP(=CPP)
CGP is the most critical (FEOL) rule for
10nm 58~60nm
logic gate density.
CPP volume of emb-SiGe stress 7nm 40nm
mobility (Gm_max) and ION 5nm 28~29nm
emb-SiGe volume, mobility, and ION
SCE trades off with performance
Impact of density scaling
PFET mobility enhancement w.r.t. relaxed Si
Scenario 1 Scenario 2 (due to SCE)
Scaling all dimensions x0.7 Reduced LG scaling
Si stressors
SRB
None
S/D stress
SiGe 35%
20nm recess
CESL
10nm, -2GPa
TiN Gate
5nm, +1GPa
Gate Fill
W, +1GPa
Contact
W, trench, +1GPa
Ideal scaling: mobility enhancement is maintained when scaling CGP
Reduced LG scaling: strong mobility loss when scaling
Scenario 1 (scale all dimensions by 0.7X) ideal case.
Scenario 2 (reduced LG scaling: current practice!)
LG scales less (i.e. > 0.7X) due to SCE (even though
FinFET in general has good SCE control).
The effectiveness of S/D stressor (e.g. SiGe)
decreases with scaling, due to S/D opening space
reduced.
Substrate stressors 2016 IEDM
short course
Tensile biaxial stress with Si on SiGe SRB(strain relaxed buffer)
Before growth After growth
The higher the germanium concentration in the substrate, the higher the stress in
the strained silicon:
𝜎𝑥𝑥 = 𝜎𝑦𝑦750MPa/(10% Ge concentration of the substrate)
Typical strained silicon thickness: 5-20nm
Principle of the technique: epitaxial growth of silicon
on SiGe → biaxial tensile stress in silicon
35
2016 IEDM
Strain Relaxed Buffer (SRB) short course
Si1-xGex substrate creates a tensile biaxial Mobility enhancement vs.
substrate Ge concentration
stress in the silicon top layer
For nMOS: strong mobility improvement, saturates above
30% substrate Ge%.
For pMOS: µ slight decrease for low Ge%, increase for
high Ge%.
pMOS: longitudinal direction needs compressive, lateral direction
needs tensile. so maybe lateral direction takes over at high [Ge].
36
Biaxial Uniaxial Strain
Moving from biaxial stress to uniaxial stress
in FinFETs
smaller volume, harder to apply stress
37 2016 IEDM short course
What about FinFET?
NFET mobility enhancement
w.r.t. relaxed Si
Effective stressor for NMOS - Si
S/D can be used as S/D stressor
Common buffer allows to integrate
both strained Si for nMOS and
strained Sige for PMOS
Fin width=10nm, FP=42nm, CGP=58nm
G. Eneman et al., IEDM 2012
SRB (strain relaxed buffer) is an effective way of
introducing (tensile) stress. It can be comparable
or even more effective than S/D stressor.
38
Scaling L SRB more effective stress
2016 IEDM
short course
SRB (Strained Relaxed Buffer)
Ideal scaling: mobility enhancement is
maintained when scaling CGP
Reduced LG scaling: SRB effectiveness is
maintained, but S/D stressor becomes ineffective
Stress from substrate becomes more important!
39
Review and Summary
Strain Techniques (Sub-band Engineering)
Mobility Enhancement
Desired Stress for CMOS Devices
Strain module :
S/D Strain -Embedded SiC/SiGe
Stress Proximity Technique (SPT)
Stress Memorization Technique (SMT)
Contact Etch Stop Layer (CESL)-DSL or SSL
Strain Relaxed Buffer (SRB)- Strained channel
Scaling L :
Stress Transfer Efficiency↓
SRB is important!
40
