Infineon” Using the EiceDRIVER™ 2EDi product family of dual-channel functional and reinforced isolated MOSFET gate drivers Design guidelines and application example in the Infineon 800 W ZVS PSFB evaluation board About this document ‘Scope and purpose This application note introduces the EiceDRIVER™ 2EDi product family of dual-channel isolated gate drivers for power MOSFETs. The document opens with an overview of safety isolation standards and certifications. A second section provides guidelines to properly design a gate drive circuit using 2E0i. Finally a practical application example is. given; in particular, the 2605 is evaluated in a phase-shift full-bridge (PSF8) DC-DC converter and compared with the widely-used gate transformer solution, Intended audience ‘This application note is targeted for application engineers and designers of switch mode power supplies (SMPS) looking for isolated solutions to drive power MOSFETS. The benefits 2EDi products offer in most of the commonly used SMPS stages (PFC, LLC, PSFB, .. are discussed. Application Note Please read the Important Notice and Wamings atthe ene ofthis document vad worwinfineon.com/2EDt page 1of2¢ 2003-03-08,Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Table of contents Table of contents About this document. 2 Table of contents. 2 2 Overview of isolation standards ..... esenee 24 ‘System isolation standards: IEC60950, IEC62368 .nrnennmnnnsnnninenernr 22 Isolator component standards: |EC60747-17, UL1S77, VDE-0884-1x.. 3 Design guidelines. BL Shunt resistor dimensioning. 32 Bypass capacitors dimensioning, 321 Input bypass capacitor wnnenrmemnnrninnennnnninrn 3.22 Output bypass capacttOrinnnninnnnnnnnnnnnenn 33 Bootstrap circuit dimensioning. 34 Gate resistance dimensioning 4 PCB layout recommend: 5 Evaluation of 2EDS vs gate transformer in 800W PSFB evaluation board .. 5.1 Reduced gate switching noise 5.2 Efficiency improvement at light-load 53 Volume saving with 2EDS.. ' 54 No concerns about core saturation with the 2EDi product family 6 Summary. 7 References sues Application Note 20f24 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Introduction to EiceDRIVER™ 2EDi 1 Introduction to EiceDRIVER™ 2EDi ‘The 2EDi products benefit from the well-known features of the EiceDRIVER™ family; they are particularly attractive in fast switching power systems (for further details please visit the EiceDRIVER™ family webpages (1), [2], [3}) and the dedicated documentation (e, [3]. ‘The key feature of EiceDRIVER™ 2£Di is isolation based on coreless transformer (CT) technology. The 2EDi- family offers functional and reinforced isolated gate driver solutions for power MOSFET. Different isol levels are associated with the different creepage and clearance distances of the packages offered. Figure 1 shows the intended range of usage for the 2EDi products: ‘+ 2EDPex75F (NB-DSO1G package) in high voltage (HV) PFC stages based on half-bridge structure 2EDSex65H (WB-DSO16 package) in isolated DC-DC stages 2EDFT2x5K (LGA mm x5 mm) in isolated and non-isolated DC-DC bricks; the compact LGA package is preferred here since low voltage (LV) DC-DC bricks are less demandingiin terms of working voltage and package size He | ococ FF Datacenter PDU eM pe-oc [Datacenter PDU | | iter | rr ne tvsr || Nonsolated | ——————_ Pec | Primary DcjoC brick | | patacenter CPU } ' _— 2eDFr2TSF 2ense26sH 2e0FT275K 2EDFe27SF ZEDS926SH 2eDF7225K 2EDF9275F DEDSTIGSH Functional sotation 2EDFATSE 2epser6si Reinforced isolation BSS oe Functional sola % pso16-pin Dso16-pin nar) narcow body wide body 5x5 mm Figure —_Intended usage range for 2EDi products in SMPS The input-to-output and channel-to-channel isolation makes the 2Di drivers suitable to drive both high- and low-side switches in half-bridge (HB) and full-bridge (FB) structures. But even systems utilizing low-side switches only may exhibit significant differences between driver and controller ground potential, e.g, when 4-pin switches with Kelvin source connection have to be driven or when. high parasitic PCB inductances cannot be avoided. Then a functionally isolated driver is a solution to safely avoid any erroneous interpretation of the control signal. If functional isolation is not sufficient in terms of safety, the 2EDS reinforced input-to-output isolation ensures “double protection” according to the safety isolation standards (see section 3) Application Note 3 0f24 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Overview of solation standards 2 Overview of isolation standards EiceDriver™2EDi can be regarded as a family of magnetic digital isolators and thus must be certified according. to common isolation standards. Isolation standards are mainly separated into two categories: ‘+ System standards, defining the safety requirements of the overall end-system ‘+ Isolator component standards, defining test-procedures to test the robustness of single isolators Due to the robust on-chip isolation utilizing a thick $i02 layer, the isolation level ofa 2EDi product is usually limited by the package. The system standards of interest define minimum distances (creepage and clearance) between any two conductive points of the system (pins/pads) to avoid creation of undesired conductive paths (due to pollution con the PCB or airspark). The single packages must meet this criterion regarding input-to-output or channel-to- channel pin distances. The isolator “package” then forms the bridge between system and component standards. Component standards define test voltages according to system standards and package limitations, 21 System isolation standards: IEC60950, IEC62368 ‘System isolation standards define the overall system operating environment, human safety requirements and test procedures to make end equipment safe and production tests standardized globally. ‘The system standard of highest relevance for 2EDi applications is IEC60950. This standard has been widely used over the years for information processing, office machinery and telecom equipment. Today, the new IEC62368 standard is taking the lead; its 3° version has been published in 2018 including the 1EC60950 together with the IE60660 standard for audio and video equipment. It addresses consumer electronics (game station, musical instruments etc.), data processing and computer network equipment (PCs, laptop, servers, routers etc), office appliances (electronic type-writers, copy machines etc.) and telecommunications equipment (telephone system, modem etc.) fee @UiDE 112 ed ree sn Figure2 Evolution of relevant end-system standards Application Note 4of2e va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers Overview of isolation standards Compared to the previous standards, the IEC62368 introduces a different approach (hazard-based approach) that focuses on clarifying the hazards mechanisms and causes rather than prescribing solutions. Along transition period has been considered necessary to adapt to the new safety approach. Actually the standards are coexisting but certification bodies will be forced to only certify according to the new standard from June 2019; the previous standards will be completely replaced in December 2020. ‘The 2Di product family is certified according to the 1EC62368 and the included IEC60950 system standards with related European, Canadian (CSA) and Chinese (CQC) certifications. ‘The isolation specification section of the 2EDi datasheet [5] includes several references to different IEC standards; these are simply sub-standards including specific sections of the global EC62368 standard. For ‘example, the IEC6064-x defines the minimum creepage (CPG) and clearance (CLR) distances required to ensure system level isolation. 2.2 Isolator component standards: 1EC60747-17, UL1577, VDE-0884-1x The isolator component standards define certification tests for the isolation barrier robustness in isolated ICs. UL1577 is the first isolator component standard, released in USA for optocouplers. Its international equivalent, 1EC60747-5-5, came in 2007 followed by the compliant German standard VDE0884-5-5. USA(UL body) International standardization ‘Germany (VDE body) ree bors ence Re ‘rsen optocoupler oe wor =Mognetictcapactne Figure3 Evolution of isolator component standards With the development of digital isolators based on magnetic or capacitive isolation, component isolation standards for both magnetic and capacitive couplers have been introduced (Figure 3); the first standard {VDE0884-10) has been developed under the coordination of VDE in Germany working as an independent body for certification. ‘The most recent German standard VDE-0884-11, released in January 2017, is the basis for the future global world wide standard IEC60747-17 (release planned in 2020) for magnetic and capacitive isolated devices. ‘As UL1S77 is the only component standard available in USA, it has been widely used even to certify non-optical digital isolator. The reinforced isolated 2EDS is certified according to VDE0884-10 (VDEO884-11 is planned) as well as according to ULIS77. Application Note S02 va 2003-03-08Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Overview of isolation standards ‘The VDE-0884-1x standards define additional test methods emulating possible stresses on the isolation barrier in operating conditions. Key tests include the determination of the parameters below: + maximum surge isolation voltage (Vis) * maximum transient isolation voltage (Viomm) «maximum repetitive peak voltage (Vioas) * working voltage (Viowm) Vosu tests simulate a lightning strike on the isolation barrier coming from the electrical power grid. Vons tests simulate a non-periodic stress on the isolation barrier, e.g. an unintended voltage overshoot due to load jumps. Vioru and Vimy tests simulate a periodic stress on the isolation barrier; an examples the periodic HV signal applied between primary and secondary GND in a high-side driver. In addition, the VOE-0884-1x standards define a common mode transient immunity (CMTI) test. Going beyond pure robustness tests, CMTI intends to test the noise immunity ofthe isolation barrier by applying fast voltage transients between primary and secondary side. ‘The new VDE-0884-11 standard adds the time dependent dielectric breakdown (TDDB) test. It intends to test the long-term reliability ofthe insulation material through an accelerated test-stress. A DC or AC voltage significantly higher than Vows is applied across the barrier for a time necessary to break down the barrier. The test is repeated varying the voltage level in order to obtain a voltage versus time graph; the product lifetime at the rated working voltage is determined by extrapolation. Application Note 6of2e va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines 3 Design guidelines The CT technology, decoupling input and output sides, makes the 2EDi family suitable to drive half-bridge and full-bridge configurations; in particular, the reinforced isolated 2EDS is suggested to drive the HV primary-side MOSFETs in common PSFB and LLC topologies based on secondary-side control, while the functional isolated 2EDF is suggested to drive PFCs and LV synchronous rectifier topologies based on half-bridge or full-bridge structures. A typical example of a 2EDS based gate drive circuit driving such a half-bridge is given in Figure 4. oN Figures Gatedi ig circuit using 2EDS to drive HV MOSFETs in a PSFB converter The following subchapters provide guidelines for dimensioning the driving circuit components: ‘+ Shuntresistor (R80) ‘+ Input bypass capacitance Cj, (C30) ‘+ Output bypass capacitance Coys (C32) # Boostrap components: resistance RB (61), capacitance CB (°:) and diode DB (011) ‘© Source (R14, R20) and sink (R13, RIS) gate resistances. 34 Shunt resistor dimensioning ‘The input side of 2EDi must be powered with a nominal 3.3 V (maximum 3.5 V) through the pin VDI in Figure . Ifthe available input side supply (Vn. suru Figure 5 is exceeding 3.5 V, the shunt low-dropout regulator {SLDO) embedded in the driver must be activated, For that purpose the IC provides an active-low SLDO pin; to activate the SLDO, the pin must be connected to GNDI. In ths situation, a proper resistor has to be placed between the available supply voltage (e.g. 12 V) and the VODI pin (regulated to 3.3 V);its value must ensure a driver input current high enough to properly feed both the input logic and the SLDO. Figure S shows the VDDI supply with and without activated SLDO. Application Note Toft va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines Vac sey 3:5 V (SLDO OFF) Vy. gern” 35V (SLDO ON) Vix suvrty ie a=: 7 ee Figures sct and SLDO-regulated VDDI supply When the SLDO is active, the supply current entering the input chip flows into the logic circuit and into the SLDO. The input logic is responsible to encode the input PWM signals into a sequence of short current pulses to drive the coreless transformer. Depending on the PWM switching frequency, the logic circuit is absorbing the almost constant current with temperature shown in Figure 6 and reported in the 26Di datasheet. * Laan) ° 0) «ata Typical DDL eatent temperature and frequency Figure6é Current consumption vs frequency of driver input logic To properly run the SLDO, a minimum current of 0.5 mA must flow into the SLDO, Then, the input current provided to the driver must exceed at least 0.5 mA the current Iyppy absorbed by the logic circuitry for encoding operations (Figure 6). The minimum requirement for the input current leads to a limitation on the selectableSLDO resistor value: Rupp, < oni =33V 1 vor ® Typo + 05mA o In (1) the minimum value, due to ripple, ofthe DC supply voltage (Vrms) has to be considered, AppicatonNote sotze vasa 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines For typical switching frequencies, the current absorbed by the input logic is 1.48 mA (Figure 6). Considering 0.5 mA margin on this current and 5% ripple on the supply voltage, the shunt resistances in Table 1 are recommended for different external supply voltages and switching frequencies. Itis recommended to use resistors in SMD 0805 package with 1 percent tolerance, Table 1 Suggested shunt resistances ‘Switching frequency Available supply VDD | 100 KHz ‘3MHz sv 7320 3160 ay 2.150 137k 5953.0 Rv $4.02 KO =2.61k0 51,78 KO 1sV $5.49 KO 3.48 KO 2.43 KO The SLDO provides flexibility in selecting the input side supply. This could bring a layout benefit since the closest low-voltage plane can be connected to the driver VDD! just activating the SLDO and placing the shunt resistor; any long connection to a 3.3 V microcontroller supply can thus be avoided in this case. Moreover, the input side robustness is strongly increased using the SLDO. In case of overvoltages on the input supply the shunt resistor may act as a fuse and disconnect the driver. This is particularly beneficial for the protection of the isolation barrier on the input chip. Finally, the shunt resistor together with the input bypass capacitanceforms a high-frequency bidirectional filter dampening both the noise injected from the auxiliary supply into the driver and the noise generated by the driver due to the CT current pulses. 3.2 Bypass capacitors dimensioning Both the high gate current during switching transients and the short current pulses driving the coreless transformer cause voltage drops on the parasitic resistances and inductances of the driver supply connections; this could affect the driver supply introducing unacceptable noise. Itis thus mandatory to use bypass capacitors between the supply pins and the related GND pins both on input and output side of the IC (see Figure 4). The bypass capacitors must be located as close as possible to the driver. 3.2.1 Input bypass capacitor Even in non-switching operation the CT is driven by a sequence of 150 mA/2ns current pulses at a non-constant repetition rate (0.4 to 1.6 us). Each of these pulses corresponds to a charge AQ of 0.3 nC; this causes a voltage ripple on the input bypass capacitance (C;q) given by ag ave 2 Cin ® To keep AV sufficiently low (e.g. in the few tens of mV range), a minimum Ci. of 10 nFis recommended. On the other hand, if the SLDO is activated, Cs, should not exceed 22 nF due to stability reasons. Itis suggested to use a ceramic capacitor in SMD 0805 package with 25 V DC voltage rating. Application Note 9 0f24 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines 3.2.2 Output bypass capacitor During the turn-on commutation of a MOSFET a short high-current pulse is drained from the driver output bypass capacitance to charge the equivalent input capacitance of the MOSFET (Cjoqq). That operation leads to 2 partial discharge of the bypass capacitance Caysby a value AV depending on the ratio of the two involved capacitances: V=Vopa x tt — “ Cour + Choad Itis important to distinguish between the equivalent input capacitance Cigaq and the input capacitance Ci. aS. reported in the MOSFET's datasheet. Ci, isthe instantaneous value ofthe input capacitance fora certain gate- torsource and dain-to-source voltage; itchanges during a switching transient. ‘The MOSFET equivalent input capacitance Cioaq is, instead, 2 mean value and can be derived from the total gate charge Qc necessary to switch the MOSFET according to = 2 5 Goad = Veg © In MOSFET datasheets Qc is usually provided in the gate charge characteristics, a graph showing the dependence of gate-to-source voltage from gate charge; an example is given in Figure 7 for a specific 280 m0 CoolMOS™ switch. [Basten ToT one dare * ante Figure? _Typical gate charge characteristic of CoolMOS™ IPAGOR280CFD7 A reasonable output supply voltage ripple below 5% would then from equation (4) result in Y<5% + Cou > 19 Coad 3) Vova A proper dimensioning thus requires to choose an output bypass capacitance which is atleast 20 times larger than the equivalent input capacitance of the MOSFET; a range from 100 nF to 1 uF is common when driving Infineon CoolMOS™ switches. As for the input bypass capacitance, itis suggested to use a ceramic capacitance in SMD 0805 package with 25 VDC voltage rating, Application Note 100824 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines 33 Bootstrap circuit dimensioning Bootstrappingiis a very cost effective method to create the floating supply voltage for driving high-side MOSFETs in half-bridge topologies. The bootstrap circuit is highlighted in Figure 8 and is made up by three components: bootstrap capacitor (Ce), bootstrap resistor (Rs) and fast recovery diode (Ds}. Vou Bootstrap areultry = Figure8 Bootstrap circuit to generate the HV floating supply The bootstrap circuit operation is defined by two main periods: ‘+ Charging period: capacitor Cs is charged while the low-side (LS) switch is ON and the high-side switch is OFF, When the LS MOSFET is ON, the diode Da's forward:-biased (Vs =0V) and the current flows from the isolated LS voltage source VDDB (+12 V) into Cs through the bootstrap resistor Re, diode Ds, and the low-side switch that finally closes the loop to ground. Simultaneously, the necessary quiescent current (Woot) iS supplied to the driver. ‘+ Sourcing period: when the low-side switch is turned off andor the high-side switch starts conducting, the source voltage of the HS switch (Vis) quickly rises until it approaches the half-bridge supply voltage (Viv ‘As.a consequence, the bootstrap diode Ds gets reverse biased and disconnects the ground supply from Cs. The capacitor Cs must be dimensioned to store the energy required to keep the HS switch ON until the next commutation; in this way, a supply voltage of Vaux * VDDA (+12 V) is ensured during the sourcing period for proper HS MOSFET driving, ‘The bootstrap circuit requires careful design in order to ensure robust and safe operation. More specifically, the charging period must be sufficiently large to charge Cs, and the ripple on the supply voltage due to Cx discharge during the sourcing period must fulfil the specifications (e.g. 5 percent maximum ripple}. Additional situations of discharge must also be taken into account; the burst mode is in particular critical from Cadimensioning point of view. Burst mode is characterized by extended non-switching times with duration tsxe (e.g. 1 ms) during low-load operation. The driver quiescent current discharges the capacitance Cs during ts; the risks that for very long tap Ce is discharged below the UVLO level of the driver. The dimensioning of Cs based on burst mode consideration is then more restrictive than for normal PWM mode operation to avoid any false triggering of UVLO. This section provides some guidelines for dimensioning the bootstrap components Cs, Re and for selecting the current and voltage ratings of the bootstrap diode Ds Application Note ofa vad 2023-08-23Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines ‘The dimensioning of Cs must guarantee a voltage ripple (AVcs) within specifications; AVcs depends on the charge Qce that has to be provided by Cx as follows: AVes = co) Ca thus can be dimensioned by calculating the charge ripple AVcs. ‘and considering the limitation on the maximum During normal PWM mode, the Qceis given by the gate charge Qe transferred in order to turn-on the HS MOSFET and the quiescent current drawn by the driver during the sourcing period. The worst case in terms of Cs discharge has to be considered: longest sourcing period and maximum HS MOSFET duty cycle (Dus) 1 Rep = Og + Dusk * ooAgu2 — ® In systems with burst mode operation at low-load, the discharging during tay must be considered by adding the term ypygqua * tx )€0 (8). ‘The capacitor Cs is defined by the maximum ripple AVce. Acommon criterion is to accept a maximum ripple of 5 percent of VOD. Considering burst mode operation, the dimensioning is more critical and must always guarantee a supply voltage above the driver UVLO level. The value of the bootstrap resistor Rp can be determined from the requirement to ensure full charge of Cs during the charging period. Assuming five time constants as a proper duration for full charging (= Dstax) tan = = SRy Cy (a0) Then the equation for Re results as follows: 1 Datax Ras a 5% Cp x towne ay After dimensioning of Cs and Rs, the selection of the proper bootstrap diode Dy can follow. Dy should have a current rating (Ihax) higher than or equal to nym (2) avira Invme is the maximum average current through the diode; the largest value is given by the shortest charging period. The voltage rating of Dsmust be sufficiently high to block Vaux during the sourcing period. Finally, the diode must have a sufficiently fast reverse recovery time to avoid that its reverse current discharge the capacitor Cp. 34 Gate resistance dimensioning ‘As widely known, the total resistance in the gate path (Rezor) defines switching time and switching losses. Rezor is made up by three contributions: the sourcing/sinking output resistance of the driver IC (Ran sic! Rey) the external sourcing/sinking resistance (Rescusce / Resne) and the internal gate resistance of the MOSFET (Re) The low-ohmic output stage of the 2EDi family results in negligible Rey sacand Res nx contributions. Application Note 120ft4 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Design guidelines The internal gate resistance of the MOSFET changes with the MOSFET technology; when driving Infineon CoolMOS™ devices, itis suggested to refer to the dedicated CoolMOS™ application notes for getting first indications on how to select the external source and sink resistances fora specific product. The differentiation of the external gate resistance allows to independently optimize “on” and “off” transients; thisis particularly important in soft switching topologies. In the PSFB topology e.g., the zero voltage switching (for low output currents) at turn-on allows to select an external source resistance larger than the sink resistance as the turn-on switching losses are not affected in the soft switching approach. Besides, an increased source resistance dampens gate voltage overshoots during turn-on. Optimizing gate resistors is a complex task: it requires to consider the basic tradeoffs between switching time/ efficiency and voltage overshoots/EMI, as well as the interaction mechanisms between the switches in a half- bridge (spurious turn-on, shoot-through]. In addition, a good estimation of package and PCB parasitics (particularly power loop inductance) is indispensable. A detailed discussion on how to select and dimension optimized gate resistors is beyond the purpose of this application note, Dedicated application notes, e.g, [6], describe the main parameters to consider. Application Note 130824 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - PCB layout recommendations 4 PCB layout recommendations ‘The impact of PCB parasitic is particularly critical in fast-switching power systems and requires a proper layout. This section provides hints to optimize and speed up the PCB layout around EiceDRIVER™ 2EDi products: ‘+ Usealow-ESR decoupling capacitance for each input (VDD!) and output (VDDA, VODB) supply and place itas close as possible to the driver ‘+ Place the gate resistors and the MOSFETS as close as possible to the driver in order to minimize the gate loop inductance ‘+ Use GND planes to reduce the parasitic inductance of ground connections + Use viasin parallel to reduce the resistance of connections + When using the dead-time control (DTC) functionality(2EDF7235A), place the external DTC resistor (see Figure 11) as close as possible to the driver; any coupling capacitance to a high-side node has to be strictly avoided Figure, Figure 10 and Figure 11 provide layout recommendations for 2EDSxx6SH, 2EDFxx75F and 2EDF7235K, respectively The figures show top layer layouts with the gate driver and the MOSFETs on the same side; this is suggested when using SMD MOSFETs. Only single gate resistance (no differentiation between source and sink behaviour) are considered for sake of simplicity fu Figure? _2EDS8x65H in shunt mode - Layout recommendation Application Note sofa va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers PCB layout recommendations Figure10 _ 2EDF7x75F - Layout recommendation Figure11 _2EDF7235K - Layout recommendation Application Note 150f24 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Evaluation of 2EDS vs gate transformer in 800W PSFB evaluation board 5 Evaluation of 2EDS vs gate transformer in 800 W PSFB evaluation board ‘A 2EDSx gate driver has been tested in Infineon’s 800 W zero voltage switching (2VS) phase-shift full-bridge (PSFB) evaluation board. This board is a DC-DC converter intended for use in SMPS for server and industrial applications (1) Driving the HV primary side from the secondary side microcontroller requires an isolated driving scheme; the original version of the board uses a non-isolated gate driver (EiceDRIVER™ 2EDN) plus a gate transformer (ICE G 05-111-100) and is available at the webpage Evaluation board Eval_800w_zvs_fb_cfd7, The modified evaluation board in Figure 12 has been realized by re-designing the HV full-bridge gate drive scheme with the reinforced isolated 2EDS gate drivers. Purpose of the new design isto test the 2EDS gate driver behavior in 2 real and widely used application. In addition to the necessary PCB changes, this requires to redimension the gate resistors and adapt the software for optimizing dead times, Figure12 Internal variant of the 800 W ZVS PSFB board using the 2EDS for evaluation purposes The evaluation shows that 2EDS works properly in the application representing an attractive alternative to the gate transformer solution with lower volume and increased low-load efficiency. 5.1 Reduced gate switching noise Itis well known that the lower limit of the gate resistors is on the one hand defined by the switching node's voltage overshoots; this strongly depends on parasitic inductances and switching conditions (hard/soft). On the other hand the gate resistors also have to dampen ringingiin the gate loop. From oscillator theory, this depends on gate loop inductance and gate capacitance. Here the 2EDS solution is by far superior due to the removal of the leakage inductance associated with the gate driver transformer. The coreless transformer used in the 2EDi product family, however, is characterized by a nearly negligible leakage inductance. This s evident also from the measured waveforms in Figure 13 and Figure 14 depicting the induced noise during a hard turn-on transition (10 A load); the same dVss/dt of 12.9 V/ns is guaranteed in both versions. Application Note 160124 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Evaluation of 2EDS vs gate transformer in 800W PSFB evaluation board Figure13 Gate voltage noise during hard turn-on (10 A) in the original evaluation board using 2EDN plus gate transformer - gate-to-source voltage of the leading leg LS MOSFET [cyan], its drain-to-source voltage [yellow], and current in the transformer [green] oo TT —— 1v Figure 14 Gate voltage noise during hard turn-on (10 A) in the new evaluation board using 2EDS - gate-to-source voltage of the leading leg LS MOSFET [cyan], its drain-to-source voltage Iyellow], and the current in the transformer [green] Figure 13 shows that, in order to avoid cross-conduction in the half-bridge due to the significant gate transformer induced noise, a bipolar voltage driving has been used in the original board; this allows to be safe Application Note sTofza va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Evaluation of 2EDS vs gate transformer in 800W PSFB evaluation board and avoid shoot-through events without increasing the gate resistance and without sacrificing the switching, losses. However, higher gate drive losses result from bipolar voltage operation. With the 2EDS solution the limited gate noise obtained for the same dVos/dt does not require a bipolar driving. Moreover, the lower noise with the 2EDS driver provides some margin to increase dVzs/dt by reducing the gate resistor, thereby speeding up switching transients and gaining efficiency without the risk of shoot-through issues. 5.2 Efficiency improvement at light-load ‘The efficiency characterization is done for the complete output current range including the bias and the fan absorption. Infineon 2EDS8265H Bos GTO5-111-100 Load [a’ “ Figureis Efficiency plots ‘The plot highlights that 2EDS works properly in this application, keeping the efficiency of the converter nearly unchanged (except for light-load, the efficiency mismatch in the remaining range is simply due to the different tolerances of the 2 PCBs under test) ‘The higher noise immunity with 2EDS (section 5.1) allows to speed up the switching event and reduce the switching losses compared to the gate transformer solution. However, switching losses significantly influence overall efficiency only for low output currents, asin this range zero-voltage switching (2VS) is not completely achieved 5.3 Volume saving with 2EDS Using 2EDS allows to remove the discrete gate transformer, which for the typical PSFB switching frequencies (100 KH2) isa bulky component; the gate transformers originally used in the evaluation board are highlighted in the board top view in Figure 16. The 2EDN driver isnot visible since itis located on the bottom side of the PCB. Application Note 18 0f24 vad 2003-03-03an Using the EiceDRIVER™ 2EDi product family of dual-channel I n fi neon functional and reinforced isolated MOSFET gate drivers Evaluation of 2EDS vs gate transformer in 800W PSFB evaluation board Figure16 Bulky gate transfomers in the top layer of the original evaluation board In the new design, 2EDN and gate transformers are replaced by 2EDS. The 2EDS gate drivers are located on the bottom side of the PCB across the isolation barrier, as can be seen in Figure 17. Figurei7 _ 2EDS replace the 2EDN and the gate transformer in the modified evaluation board The volume saving that can be achieved by replacing the gate transformers with 2EDS drivers is estimated to be at least 25 percent. This would allow a significant increase in power density (40 W/inch’ in the original board). Application Note 190124 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Evaluation of 2EDS vs gate transformer in 800W PSFB evaluation board 5.4 No concerns about core saturation with the 2EDi product family Additional concerns are due to the nature of the discrete gate transformer with the well-known problem of core saturation imposing a limit on the minimum switching frequency in the converter. Besides, it requires an almost symmetric driving signal which limits the duty cycle to a maximum of 0 percent. A driving solution not based on gate transformers is in generalmore flexible. With 2EDS and the CT technology the relation between core size and frequency is no longer of concern for the designer. Moreover, the minimum, converter switching frequency is not limited any more, providing freedom and flexibility to test and operate a converter at different frequencies; this is particularly important during the first development phases. Inthe described PSFB topology the duty cycle is 50 percent, which does not add particular concerns regarding, core saturation; however, saturation could happen in special conditions like e.g burst mode. In the original board this is avoided by applying an even number of pulses during burst mode to maintain the transformer excitation voltage symmetry; with the 2EDi product family replacing the gate transformer the designer no longer has to face such constraints. Application Note 200f24 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - summary 6 Summary This document introduces the EiceDriver™2EDi family of isolated gate driver for power MOSFETs. The main intention is to address the usage of 2£Di products in the different SMPS stages and to support engineers using 2EDi gate drivers. Design and layout guidelines are provided allowing engineers to autonomously design an optimized and complete gate drive scheme using 2EDi. Furthermore, the performance of 2£Di has been evaluated in a typical PSF8 application with focus on reinforced isolated 2EDS. This evaluation has shown the advantages of 2EDi over conventional gate transformers, essentially inked to the innovative coreless transformer (CT) technology. Adding very low parasitics to the gate loop, 2EDi represents an attractive solution in fast-switching power systems; compared to the common gate transformer driving solutions, using 2EDi guarantee limited switching noise on the gate voltage reducing the risk for dangerous situations (shoot-through) The volume saving and increase in system power density is an additional advantage of 2EDi. Moreover, without core saturation problems, the 2E0i CT techonology provides design flexibility and allows to simplify the control scheme. With 2EDi, asymmetrical control signals and duty cycles above 50 percent are possible Furthermore, the converter switching frequency can be easily changed with no impact on the 2EDi driving scheme In addition, due to better noise immunity, 2EDi provides some margin to increase system efficiency by reduction of gate resistors. Asa conclusion, the investigation has shown that 2EDi is an attractive alternative to the gate drive transformer representing a compact, flexible and easy-to-use isolated driving solution. Application Note riof24 va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers References 7 References [1] _ Eicedriver™ 2EDN Gate Driver for Mosfets [2] Eicedriver™ 2EDN Gate Driver for Mosfets [3] Dual-channet jolated gate driver | Eicedriver™ 2EDI [4] AN_201609_PL52_031 Benefits of low-side MOSFET drivers in SMPS {5] Datasheet Revision 2.2 EiceDRIVER™2EDi product family - fast, robust, dual-channel, functional and reinforced isolated MOSFET gate-driver with accurate and stable timing [6] _AN2015-06 EiceDRIVER™ — gate resistor for power devices [7] AN_201709_PL52_027 800 W ZVS Phase-shift full-bridge evaluation board - using 600 V CoolMOS™ CFT and digital control by XMC4200 [8] T. Fujihira, 36, pp. 6254-62, 1997 Application Note 220f24 ‘Theory of Semiconductor Superjunction Devices”, Japanese Journal of Applied Physics vol. va 2023-0208Using the EiceDRIVER™ 2EDi product family of dual-channel Infineon functional and reinforced isolated MOSFET gate drivers - Revision history Revision history Document version | Date of relea Description of changes vio 23-11-2018 1 version v2.0 28-05-2019 Written form revised ‘Added new 2EDF9275F, 2EDS926SH part numbers for 650V v3.0 2020-05-15 CoolSic™ driving ‘Adjusted values in Figure 6 vao 2022-03-22 ‘Added new 2EDF8275F, 2EDS7165H part numbers var 2023-03-08 Editiorial changes Application Note 230f24 vaa 2023-0208[ireterenced producto service names and trademark are the property oftherrespctive owners dition 2023-03-08 Published by Infineon Technologies AG 81726 Munich, Germany {© 2023 nfingon Technologies AG. AULRghts Reserved. Doyouha document? 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