U.S.N.

B.M.S. College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

September / October 2023 Semester End Main Examinations

Programme: B.E. Semester: III

Branch: Electronics and Communication Engineering Duration: 3 hrs.
Course Code: 22EC3PCDSD Max Marks: 100
Course: Digital System Design

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may be suitably assumed.

UNIT - I
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank

1 a) Obtain the minimal expression using K-map for the following incompletely 10
specified function and draw the logic diagram using only NAND gates.
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = ∑ 𝑚 (0,1,4,6,7,9,15) + ∑ 𝑑 (3,5,11,13)

b) List all the Verilog datatypes and explain in detail with examples. 10
pages. Revealing of identification, appeal to evaluator will be treated as malpractice.

UNIT - II
2 a) Design a combinational circuit with two 2-bit inputs and 3 outputs of 1-bit. 12
Values of the outputs is decided by the comparison results of two input values.
Write truth table, logic expression and logic diagram.
b) Write Verilog code for above design. 04
c) Analyse the following logic circuit to obtain the expression for F(ABCD) 04
shown in fig 1

fig 1
UNIT - III
3 a) Design 4 to 1 Multiplexer using if-else and if-else-if sequential statements. 12
b) Design a Verilog code for finding factorial of a positive number using while 08
loop statement.
OR
4 a) How many unused combinations are there in the representations of BCD 12
numbers using 8421 weighted schemes? Design a combinational circuit for a
 4-bit input X and single-bit output Y, has the condition as output is high for
the unused combinations in the above BCD representation. Write Verilog code
for the same.
b) Explain ‘repeat’ and ‘forever’ statements with syntax and necessary examples. 08

UNIT - IV
5 a) Design a synchronous mod-6 counter whose counting sequence is 0,6,5,3,2,1,0 12
using positive edge triggered JK flipflop.
b) Write a Verilog structural description for JK flipflop using logic gates as 08
components.
OR
6 a) A 4-bit shift register shown in fig 2, which shifts 1bit to the right at every clock 12
pulse is initialized to the values 1000 for Q0Q1Q2Q3. The D input is derived
from Q0Q2Q3 through two XOR gates as shown in figure. Assume propagation
delay of each gate is zero.

fig 2
i) write the 4-bit values Q0Q1Q2Q3 after each clock pulse till the
pattern (1000) reappears on Q0Q1Q2Q3.
ii) To what values should the shift register be initialized so that the
pattern (1001) occurs after the first clock pulse.
b) Draw the flowchart or provide the logic for implementing D-latch with active 08
high enable and write the Verilog HDL behavioural description.
UNIT - V
7 a) Analyze the synchronous sequential circuit shown in figure 3. Obtain its state 10
table and the state diagram.

figure 3
b) Design a state machine for the sequence 110. Also write Verilog HDL code 10
for the same.
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