Bs rify Truth Table of Logie Gates (AND, OR, NOT, NAND & NOR Gates). EQUIPMENT REQUIRED: - All the basic gate mention in the fig. ‘THEORY: - There are different gates available in digital electronic filed. Which is used to perform the different tasks they are as follow:- [AND GATE: - This gate is used for the multiplication of two binary digits. OR GATE: - This gate is used for the addition of two binary digits. NOT GATE: - This gate gives the compliment of given binary digit NAND GATE: - This gate is used for giving compliment of multiplication of two binary digits. NOR GATE: - This gate is used forgiving compliment of the addition of two binary digits DAIGRAM! \2—tnpact AND gate. 9 input OR gue g 8 Sipe re udput Saget B— = ale abe | (re lam L-input NOT gate 2 ypu NAND gate Scanned with CamScannerScanned with CamScannerPlace the IC on IC Trainer Kit. Connect Veo and ground to respective pins of IC Trainer Kit. Colanect the inputs to the input switches provided in the IC Trainer Kit. Connect the outputs to the switches of O/P LEDs, ‘Apply various combinations of inputs according to the truth table and observe condition of LEDs. Disconnect output from the LEDs and note down the corresponding multimeter voltage readings for various combinations of inputs. RESULT:- Successfully verify the truth table of logic gate. PRECAUTIONS: - 1) All the connection should be tight. 2) It should be care that the values of the components of the circuit is does not exceed to their ratings (maximum value). 3) Before the circuit connection it should be check out working condition of all the ‘Component. Digital Electronics Lab Manual:3 semester (ET&T, CSE) Scanned with CamScannerEXPERIMENT Ni OBJECTIVE: - Design Basic Gates Using NAND gates. EQUIPMENT REQUIRED: - NAND gate, connecting wires etc THEORY:- NANO GATE is a universal gale tis 50 called as because by using ofthis gale we reer yey gate like ol, of, and elc. by help of tis gate we can also make multiplexers and de mux, NAND gate equivalents _The table below shows the NAND gate equivalents of NOT, AND, OR and NOR gates: _ Gate Equivalent in NAND gates a io. >| Daa e 2 5 Digital Electronics Lab ‘Manual:3” semester (ET&T, CSE) 4 Scanned with CamScannerPROCEDURE: a ar 3 Place the IC on IC Trainer Kit. Connect Veo and ground to respective pins of IC Trainer Kit. Cohnect the inputs to the input switches provided in the IC Trainer Kit, Connect the outputs to the switches of O/P LEDs, Apply various combinations of inputs according to the truth table and observe condition of LEDs. Disconnect output from the LEDs and note down the corresponding multimeter voltage readings for various combinations of inputs. RESULT:- Designing of basic gates by using of NAND gate is successfully done . PRECAUTIONS: - 1) All the connection should be tight. 2) It should be care that the values of the components of the circuit is does not exceed to their ratings (maximum value). 3) Before the circuit connection it should be check out working condition of all the Component. Digital Electronics Lab Manual:3“ semester (ET&T, CSE) Scanned with CamScannerEXPERIMENT No- 3 OBJECTIVE: - Design Basic Gates Using NOR gates. EQUIPMENT REQUIRED:- NOR gate, connecting wires ete ‘THEORY:- Like NAND gates, NOR gates are so-called mmbined to form any other kind of logic gate. For example, the first embedded system, ‘Apollo Guidance Computer, was built exclusively from NOR gates, about 5,600 in total for the later versions. Today, integrated circuits are not constructed exclusively from single type of gate. Instead, EDA tools are used to convert the description of a logical Cireuit to a netlist of complex gates (standard cells) or transistors (full custom approach). iniversal gates" that ca OR GATE [ANOR gate is logically an inverted OR gate. By itself has the following truth table: og Truth Table Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 rt 0 Making other gates by using NOR gates [ANOR gate is a universal gate, meaning that any other gate ean be represented as @ combination of NOR gates. NOT Truth Table Input Output A Q Digital Electronics Lab Manual: 3 semester (ET&T, CSE) Scanned with CamScannerThis is made by joining the inputs of a NOR gate, As @ NOR ent is equivalent to an OR gate leading to NOT gat, t ised vtematically sees to the "OR" part of the NOR gate eliminating it from consideratio » and leaving only the NOT part. Desired Gate NOR Construction ‘The OR gate is simply a NOR gate followed by a NOT gate. Desired Gate NOR Construction “D> ve ‘Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 r 1 1 1 AND [An AND gate gives a | output when both inputs are 1; aNOR gate gives a ! output only ‘ghen both inputs are 0. Therefore, an AND gate is made by inverting the inputs to a NOR gate. Desired Gate NOR Construction A A B Digital Electronics Lab Manual:3" semester (ET&T, CSE) a Scanned with CamScannerTruth Table Input A Input B Output Q 0 0 0 0 1 0 1 0 0 1 1 1 NAND A NAND gate is made using an AND gate in series with a NOT gate: Desired G: NOR Construction ‘ Q B B ‘Truth Table Input A Input B Output Q 0 0 1 0 1 1 1 0 1 1 1 0 OR ‘An XOR gate is made by connecting the output of 3 NOR gates (connected as an AND gate) and the output of a NOR gate tothe respective inputs of a NOR gate. This expresses the logical formula (A AND B) NOR (A NOR B). This construction entails a propagation delay three times that of a single NOR gate. Desired Gate NOR Construction Truth Table Digital Electronics Lab Manual:3" semester (ET&T, CSE) 8 Scanned with CamScannerTruth Table Input Input Output A B Q er Input A Input B Output Q 0 0 0 1 1 1 1 0 Heo XNOR ‘An XNOR gate can be constructed from four NOR gates implementing the expression "(A NOR N) NOR (B NOR N) where N = A NOR B".This construction has a propagation delay three times that of a single NOR gate, and uses more gates. Desired Gate NOR Construction > pep RESULT: - Designing of basic gates by using of NOR gate is successfully done PRECAUTIONS: inals should be checked before going 4) The continuity of the connecting ter 2) It should be care that the values of the components of the circuit is does not exceed to their ratings (maximum value). 3) Before the circuit connection it should be check out working condition of all the Component. Digital Electronics Lab Manual:3 semester (ET&T, CSE) Scanned with CamScannerEXPERIMENT No: 4 OBJECTIVE: - Verify Demorgan’s theorem. EQUIPMENT REQUIRED: - All the basic gate mention in the fig. THEORY: - The law is named after Augustus De Morgan (1806-1871) who introduced a formal Version of the laws to classical propositional logic. De Morgan's formulation was influenced by algebraization of logic undertaker George Boole, which later cemented De Morgan's claim to the find, Although a similar observation was made by Aristotle and was known to Greek and Medieval logicians (in the 14th century William of Ockham wrote down the words that would result by reading the laws out), De Morgan is given credit for stating the laws formally and incorporating them in to the language of logic. De Morgan's Laws can be proved easily, and may even seem trivial, Nonetheless, these laws are helpful in making valid inferences in proofs and deductive arguments, A.B=A+B A+B=A.B Thus, aa es is equivalent to ie is equivalent to ae ‘These can be generalized to more than two. variables: to Digital Electronics Lab Manual:3" semester (ET&T, CSE) 10 Scanned with CamScanner‘Synthesis of logic circuits: Many problems of logic design can be specified using a truth table, Give such a table, can you design the logiccircuit? Design a logic circuit with three inputs A, B, C and one output F such that F=1 only when a majority of the inputs is equal to 1 [A |B |c F | Sum of product form 0/0 |0 |O 4 = pe) fo 10 11 10 | F=AB.C+AB.C +AB.C + AB.C 0 {1 [0 [0 | GG 1 |0 |O \0 1 |0 |1 |1 me Osh Tala Simplification of Boolean functions: Using the theorems of Boolean Algebra, the algebraic forms of functions can often be simplified, which leads to simpler (and cheaper) implementations. RESULT: - Verification of Demorgan’s theorem Is successfully done. PRECAUTIONS: - 1) The continuity ofthe connecting terminals should be checked before going Fy ishould be care that the values ofthe components of the crcutis does not exceed to their ratings (maximum value). 43) Before the circuit connection it should be check out working condition of all the ‘Component. I Digital Electronics Lab Manual:3" semester (ET&T, CSE) Scanned with CamScannerEXPERIMENT No- § OBJECTIVE: - Design Half Adder. (a) Using AND/ORINOT Gates. (b) Using NANDINOR Gates. EQUIPMENT REQUIRED: - All the basic gate mention in the fig, IC 7486, 1C 7432 Ic 7408, 1C 7400, etc. THEORY:: Half adder is a digital device by using of this device we can able to add two Biase. By addition of this two digit we gate add & carry. n electronics, an adder OF Summer isa digital circuit that performs addition of numbers. In modern computers Saeere rose in the arithmetic logic unit (ALU) where other operations are performed. ‘though adders can be constructed for many numerical representations, such as Binaryccoded ‘decimal or excess-3, the most common adders operate on, Binary aan eee tn cases where two's complement or one’s complement is being used ‘0 represent negative numbers, itis trivial to modify an adder into an adder-subtractor. Other signed number representations require a more complex adder. PROCEDURI 1. Verify the gates. 2. Make the connections as per the circuit diagram. 3, Switch on V CC and apply various combinations of input according to the truth table dings for hatffull adder and halffull subtractor 4, Note down the output rea‘ alfifu ‘Sumldifference and the carryborrow bit for different combination of input. Adder using basic gates:: $= AB+ AB S=A@B C= AB onl Half Adder using NAND semester (ET&T, CSE) 12 Digital Electronics Lab Manual Scanned with CamScannerA|B|s]c| sw) cw) | [ [ofolo o[1j1fo re 1[o|ilo 1/1 {ola io RESULT:- The designing of half adder is successfully done.. PRECAUTIONS: - 1) The continuity of the connecting terminals should be checked before going 2) It should be care that the values of the components of the circult is does not exceed to their ratings (maximum value) 3) Before the circuit connection it should be check out working cor ‘Component. dition of all the Scanned with CamScannerEXPERIMENT No- 6 OBJECTIVE: - Design full Adder EQUIPMENT REQUIRED: - Al the basic gate mention in the fig., IC 7486, IC 7432, 7408, IC 7400, etc. THEORY: A full adder adds binary numbers and accounts for values carried in as well ‘as out, A one-bit full adder adds three one- bit numbers, often written as A, B, and Cini A ‘and B are the operands, and Cig is a bit carried in (in theory from a past addition). The Circuit produces a two-bit output sum typically represented by the signals Cou. and S, where SUM Cout + 5. The one-bit full adder's truth table is: PROCEDURE: - 1. Verify the gates. 2, Make the connections as per the circuit diagram. 5, Switch on V CC and apply various combinations of input according tothe truth table 4, Note down the output readings for halfull adder and halfful subtractor different combination of input. sumidifference and the carry/borrow bit for Full Adder using basic gates lid 3 AG SAGBOC iagpe} C1 C= (Aen) Cr) + AB ABBR, = s-n006e ae Teen Ds Ce ABHenA(A68) 4 Digital Electronics Lab ‘Manual:3" semester (ET&T, CSE) Scanned with CamScannerFull Adder B]Cn-1]s[c| sv) | ow) o}| o jofo| o{ 1 |1[o | 1{ 0 [2/0 1{ 1 [ola| o{ o filo | of 2 folal 1] 0 [ola 1f1 fla RESULT:- The designing of Full adder is successfully done... of the connecting terminals should be checked before PRECAUTIONS: -. 1) The continui going . 2) It should be care that the values ofthe components of the circuit is does not exceed to their ratings (maximum value). 3) Before the circuit connection it should be check out working conciion of all the ‘Component. sant 4 ETRT CSE ¥ Scanned with CamScanner