VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Goals of This Lecture

 Present intuitive understanding of device

operation
Volkan Kursun
 Introduction of basic device equations

The Devices  Introduction of models for manual analysis

Adapted from Digital Integrated Circuits, Second Edition,

Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright, 2003, Prentice Hall/Pearson

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MOSFETs Silicon
 MOSFETs are built on a silicon substrate Si Si Si

Idea of a field-effect transistor: Julius  Silicon is a Group IV material

Si Si Si

Edgar Lilienfeld in 1925  Same group with C and Ge

Si Si Si

MOSFET invented by Atalla and Kahng  Forms diamond crystal structure (repeating pattern of 18 atoms):
each silicon atom is attached with covalent bonds to four nearest
at Bell Labs in 1959 neighbors (forming a tetrahedral structure)

•MOS: Metal Oxide

Semiconductor
•FET: Field Effect Transistor
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Pure (Undoped) Silicon: i-type Extrinsic Silicon: N-type Doping

 Equal concentrations of free electrons and holes:  N-type Silicon: Doped with impurities (donors) from group VA
(such as Phosphorus)
intrinsic (i-type) material  Majority carriers: electrons
 Free electrons and holes are produced by thermal excitation and
their concentrations (intrinsic carrier concentration) are low:
insignificant current produced if an external electric field is applied
to an intrinsic silicon

Si Si Si http://inventors.about.com/libr
ary/inventors/blsolar4.htm

Si Si Si

Si Si Si

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Extrinsic Silicon: P-type Doping 2 Types of MOSFETs

 P-type Silicon: Doped with impurities (acceptors) from group IIIA
(such as Boron) • NMOS: n-channel MOSFET
 Majority carriers: holes
• PMOS: p-channel MOSFET
• CMOS: complementary MOS,
both n-channel and p-channel
devices are used to implement
http://inventors.about.com/libr
ary/inventors/blsolar4.htm

functional circuits
• All modern digital integrated circuits
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use CMOS technology
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CMOS Technology MOS Transistors: Types and Symbols

G
G
S

D
S
NMOS (Enhancement type) PMOS (Enhancement type)

G
G
Cross section of a CMOS integrated circuit

D
S
PMOS transistor is formed in a separate n-type region

B
called n-well
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NMOS with Bulk Contact
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PMOS with Bulk Contact
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12

Switch Model of NMOS Transistor Switch Model of PMOS Transistor

VGS Gate
Gate VGS

Source Drain Source Drain

(of carriers) (of carriers) (of carriers) (of carriers)

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)
Ron Ron

VGS < VT VGS ≥ VT > 0 VGS > VT VGS ≤ VT < 0V

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MOS-Transistor Basic Properties MOSFET Critical Physical Dimension: Length
Gate
CROSS- Gate Oxide Polysilicon
Field-Oxide
SECTION Source
n+
Drain
n+ SiO2
of NMOS e-
p+ stopper
Transistor
p-substrate
Bulk (Body) Contact
 Conduction at surface
There is a minimum limit: Lmin
 Source and drain are physically identical  L (Length): Length of the (transistor) gate
 They can only be distinguished by the relative voltage potentials
 The minimum gate length is the most critical physical parameter
 The gate is physically isolated from the substrate that characterizes the advancement of a CMOS technology
 Capacitive coupling (field-effect transistor)  Smallest horizontal structure that can be defined (fabricated)
 Physical mechanism for current conduction: with photolithography
 Charge-carriers drift through a strongly inverted channel  Example: TSMC 0.18µm CMOS technology: 0.18µm corresponds
to the minimum drawn gate length (Ldrawn_min)
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MOSFET Critical Physical Dimension: Width MOSFET Critical Physical Dimension: tox
There is a minimum limit: Wmin

 W (Width): The (transistor) channel width  Tox: the oxide thickness

 Minimum width is determined by the technology  Fixed by the technology
 Cannot be tuned by the circuit designer
 Transistor width is a parameter that the circuit designers decide
 Determines the strength of capacitive coupling between the gate and
– Adjusted to tune the strength of a transistor
the body of the device
 No limit for maximum  Determines the strength of field-effect
– Use multiple parallel transistors instead of a single very wide
 Stronger field-effect → higher current → faster CMOS circuit
transistor
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The NMOS Transistor Cross Section The NMOS Transistor
W: Device channel width  A four terminal device
n areas have been doped with donor
atoms (arsenic) of concentration ND - Ldiffusion_distance: Distance  Voltage applied to the gate controls the operation of the switch
electrons are the majority carriers between the edges of source  Switch on or off
and drain doping areas  Amount of current flowing between the source and drain
Polysilicon
W Gate Gate oxide Polysilicon Aluminum

Source Drain Field-Oxide

n+ Ldiffusion_distance
n+ (SiO2)

p substrate p+ stopper

Bulk (Body)

p areas have been doped with acceptor

atoms (boron) of concentration NA - holes
are the majority carriers
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Zero VG: No Channel for Current Conduction Apply Small Positive VG: Depletion Region Formation
A small positive voltage applied to the gate: VG > 0
If VGLI = VGRI = 0, two back-to-back diodes • Similar to the plates of a capacitor
• Substrate bias = 0. VGB > 0
exist in the channel area • Oxide electric field is directed towards the substrate
• Mobile holes are repelled deeper into the bulk on the substrate side of the MOS
High resistance between the two diffusion capacitor while positive charges accumulate on the gate terminal
• Negatively charged fixed (immobile) acceptor ions are left behind
areas VG = 0V • A region depleted of mobile carriers is formed underneath the gate

VGLI = 0V VGRI = 0V LI: Left Island + V > 0V

VGLI > 0V
G
VGRI > 0V

(left doping
Gate - Gate

n+ area). VLI = 0V n+ n+ n+

Depletion Region RI: Right Island Depletion Region

p-substrate
(right doping p-substrate Repelled
Immobile acceptor
ions left behind
area). VRI = 0V
B B
holes
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Apply Small Positive VG: Depletion Region Formation Further Increase In VG: Surface Inversion
• Mobile holes are repelled deeper into the bulk As the gate voltage is further increased, a thin layer of n-type material emerges
• A region depleted of mobile carriers is formed underneath the gate close to the surface
2ε Si | φ | 2ε Si | φ s − φ bulk | • Within this thin layer, electron concentration is LARGER than the hole density
W depletion = = • Additional minority carriers attracted from the bulk to the surface → SURFACE
qN A qN A INVERSION by FIELD-EFFECT VG > 0V

Q depletion = − 2 qN Aε Si | φ | = − 2 qN Aε Si | φ s − φ bulk | VT >VGLI > 0V VT >VGRI > 0V

Φ: voltage across the depletion layer + V > 0V

G Gate
Φs: Surface Fermi potential VGLI > 0V VGRI > 0V
- Gate
Φbulk: Bulk Fermi potential
Qdepletion: Depletion region charge n+ n+
density n+ n+
Fermi potential: potential Depletion Region

difference between the Fermi

Depletion Region Immobile ions
level (EF) and the intrinsic Fermi Repelled
level (Ei) left behind
EF − Ei Immobile ions holes
φF = p-substrate Repelled
holes
left behind p-substrate
q B Body
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Further Increase In VG Boundary (Threshold) of Strong Surface Inversion?
• When exactly is the surface strongly inverted?
STRONG Surface Inversion at VGLI = VGRI = VT • What is the threshold of minority carrier concentration that needs to be induced at the
• A thin channel of n-type material with abundance of electrons close to the surface surface for the surface to be called “inverted”?
• At VGLI = VGRI = VT: electron concentration in the inverted layer at the surface • Several definitions exist
becomes equal to the hole density deeper in the body of the device → • Classical definition: The surface is strongly inverted when the density of mobile
STRONG SURFACE (CHANNEL) INVERSION electrons in the channel becomes equal to the density of holes deeper in the
Gate bulk (for a p-type substrate: NMOS transistor)
+
Surface _ Fermi _ potential = − Bulk _ Fermi _ potential
VGLI = VT VGRI = VT Gate
n
NMOS - φbulk _ p = φT ln( i )
NA
+
VGLI = VT VGRI = VT
n+ n+
transistor ( p − type bulk : NMOS )
φbulk _ p < 0 ( negative )
-
n+ n+
Depletion Region
is turned n-channel with an abundance of free
ɸT: Thermal Voltage
ɸT =
௞்
26mV at room temperature
Depletion Region

ON by
௤
(mobile) electrons k: Boltzmann constant n-channel with an abundance of free
k=1.38*10-23J/K (mobile) electrons
p-substrate
field-effect Body
T: absolute temperature (300K at room
temperature)
q: charge of an electron
p-substrate
Body
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Channel Formation with VGLI = VGRI > VT NMOS Channel Formation with VGS ≥ VT
• After the surface is inverted, if the gate voltage is further increased (VGLI > VT) Physical structure of an NMOSFET is symmetrical. Source and drain terminals are
• The depletion layer width and the depletion charge density do not change distinguished by the relative voltages applied to the left and right diffusion islands
• More mobile carriers are attracted to the channel area from the source and In an NMOS transistor:
drain, thereby enhancing the conductivity of the channel •Diffusion island with a lower voltage acts as the source of (-) charge carriers
•Diffusion island with a higher voltage acts as the drain of (-) charge carriers
Maximum depletion width Gate
+ VG ≥ VT
2ε Si | −2φbulk | VGLI > VT VGRI > VT Source + Drain
VDD How to
Wdepletion = - VGS ≥ VT Gate
qN A n+ n+ -
distinguish the
QB 0 = − 2qN Aε Si | −2φbulk | Depletion Region
n+ n+ source and drain
Φ: voltage across the depletion layer
Φ = -2 Φbulk
n-channel with an abundance of free
(mobile) electrons Depletion Region terminals in a
QB0: The charge stored in the
depletion region when there is an p-substrate
Body
n-channel with an abundance of free symmetrical
inversion layer (mobile) electrons
After the formation of the channel, the transistor still cannot conduct current with NMOSFET
the voltage bias conditions that are shown in the figure p-substrate
A (nonzero) voltage differential needs to be produced between the two diffusion areas to
distinguish source and drain and to observe current flow between these two terminals Body structure?
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VGS = 0: Device is Cut-off by Field-Effect How About a PMOS Transistor?

Gate voltage reduced to 0V: surface area under the gate is If VGLI = VGRI = 0V, two diodes pointing at
no longer inverted (channel is eliminated by field-effect)
VGS = 0: two back-to-back diodes exist between the diffusion
each other exist in the channel area
islands. High resistance between the source and drain: small High resistance between the two diffusion
(ideally zero) current flow from the drain to the source areas VG = VDD
VSource = 0V VDrain = VDD
VGate = 0V VGLI = 0V VGRI = 0V
VDD VDD
Gate

p+ p+

Depletion Region

n-well
VDD B
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PMOS Transistor: Reduce VG Further Decrease In VG: Surface Inversion
Gate voltage is reduced below VDD: VG< VDD As the gate voltage is further decreased, a thin layer of p-type material emerges
• Similar to the plates of a capacitor close to the surface
• Substrate (n-well) bias = VDD • Within this thin layer, hole concentration is LARGER than the electron density
• Oxide electric field is directed towards the gate (VGB < 0) • Additional minority carriers attracted from the bulk to the surface → SURFACE
• Mobile electrons are repelled deeper into the bulk on the substrate side of the INVERSION by FIELD-EFFECT
MOS capacitor while negative charges accumulate on the gate terminal VG < VDD
• Positively charged fixed (immobile) donor ions are left behind -
VDD + VT< VGRI < 0V VDD
• A region depleted of mobile carriers is formed underneath the gate VT< VGLI < 0V
VG < VDD Gate
-
VDD VGLI < 0V VGRI < 0V VDD
Gate
+
p+ p+
p+ p+ Depletion Region

Depletion Region Immobile donor

Repelled ions left behind
electrons
Immobile donor
n-well Repelled ions left behind n-well
electrons
VDD B VDD Body
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Further Decrease In VG Bilkent University VOLKAN KURSUN

Boundary (Threshold) of Strong Surface Inversion?

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Strong Surface Inversion at VGLI = VGRI = VT • When exactly is the surface strongly inverted?
• A thin channel of p-type material with abundance of holes close to the surface • What is the threshold of minority carrier concentration that needs to be induced at the
• At VGLI = VGRI = VT: hole concentration in the inverted layer at the surface surface for the surface to be called “strongly inverted”?
becomes equal to the electron density deeper in the body of the device → • Classical definition: The surface is strongly inverted when the density of mobile
STRONG SURFACE (CHANNEL) INVERSION holes in the channel becomes equal to the density of electrons deeper in the
V =V +V G DD T
VDD VDD bulk (for an n-type substrate/well: PMOS transistor)

PMOS +
VGLI = VT
-
VGRI = VT
Gate
Surface _ Fermi _ potential = − Bulk _ Fermi _ potential
N VDD
VG = VDD + VT
VDD
φbulk _ n = φT ln( D ) -

transistor ni +
VGLI = VT VGRI = VT
Gate
p+ p+ ( n − type bulk : PMOS )

turned ON Depletion Region

φbulk _ n > 0 ( positive )
ɸT: Thermal Voltage
ɸT =
௞்
26mV at room temperature
p+
Depletion Region
p+

p-channel with an abundance of free ௤

by field- (mobile) holes

k: Boltzmann constant
k=1.38*10-23J/K
T: absolute temperature (300K at room
p-channel with an abundance of free
(mobile) holes
n-well temperature)

effect
n-well
q: charge of an electron
VDD Body q=1.602*10-19C VDD Body
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PMOS Channel Formation with VGS ≤ VT Threshold Voltage for Strong Channel Inversion
Physical structure of a PMOSFET is symmetrical. Source and drain terminals are
distinguished by the relative voltages applied to the left and right diffusion islands • Has three components
In a PMOS transistor: 1. Gate voltage component to offset the fixed (immobile) parasitic
•Diffusion island with a lower voltage acts as the drain of (+) charge carriers charge in the gate-oxide and in the silicon/silicon-dioxide
•Diffusion island with a higher voltage acts as the source of (+) charge carriers interface
Source VG ≤ VDD + VT Drain • Oxide-semiconductor interface defects
VDD +
-
0V How to • Charge acquired due to radiation
VGS ≤ VT • Contamination during fabrication
Gate distinguish the • Modeled by a fixed (typically positive for both NMOS and PMOS) charge
density at the oxide-silicon interface: Qox
p+ p+ source and drain 2. Gate voltage to offset the depletion region charge (formation of a
depletion layer)
Depletion Region
terminals in a • QB0 (without body bias) or QB (with body bias)

p-channel with an abundance of free symmetrical • Additional term QI can be included to model ion implantation for VT
adjustment
(mobile) holes
PMOSFET 3. Gate voltage component to invert the surface (strong channel
inversion)
n-well
VDD
structure? • - 2φbulk + φGC
Voltage across the depletion layer
Body
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Threshold Voltage Expression Effect of Body Bias Voltage (Body-Effect)

Work function: energy required for an electron to move from the Fermi • So far we have assumed that the source and the body are at the same
level to the free space voltage level (VBS = 0)
Assuming uniform doping concentration in the substrate:
• What would happen if VBS ≠ 0V?
(-) (+) NMOS (+) NMOS (-) VG ≥ VT Source VG ≤ VDD + VT Drain
(-) PMOS
Source + Drain -
(-) PMOS VDD VDD + 0V
VGS ≥ VT Gate VGS ≤ VT
Q ox QB - Gate
VT = − − − 2 φ bulk + φ GC n+ n+
C ox C ox p+ p+
Depletion Region Depletion Region
WFsubstrate − WFgate Built-in potential difference between the gate
φGC = and the channel due to the workfunction n-channel with an abundance of free p-channel with an abundance of free
q difference of the gate and the semiconductor (mobile) electrons (mobile) holes
ε ox oxide ௢௫ Permittivity (F/m) p-substrate
Cox =Unit ௢௫
n-well
tox
capacitance (F/m2) ௢௫ Gate-oxide thickness (m) Body VDD Body
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Effect of Body Bias Voltage Bilkent University VOLKAN KURSUN

The Body Effect (NMOS Transistor)

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• Formation of a channel (strong surface inversion) not only depends on

VBS = VBody – VSource
the VGS but also on the VBS
Body: p substrate Source: n+ doping area
• Body bias effects the depletion layer charge density
[ Positive VBS (VBS > 0V): VBody > Vsource ] → Forward body bias
Q B = − 2 qN Aε Si | − 2φ bulk − V BS | [ Negative VBS (VBS < 0V): VBody < Vsource ] → Reverse body bias
0 .9

VG ≥ VT
Depletion region charge Source + Drain D 0 .8 5

density depends on the body- VDD 0 .8

VGS ≥ VT Gate
to-source voltage difference -
0 .7 5

(VBS)
0 .7

V (V)
1. If VBS is nonzero: QB n+ n+ G B 0 .6 5

T
0 .6
changes Depletion Region 0 .5 5
2. If QB changes: VT
changes n-channel with an abundance of free S 0 .5
VBS < 0V → Reverse body bias
(mobile) electrons 0 .4 5
Body-effect strongly
0 .4
influences the threshold p-substrate -2 .5 -2 -1 .5
V (V )
-1 -0 .5 0

voltage of a MOSFET Body

BS

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Threshold Voltage and Body Bias Current-Voltage Relationship

Zero body bias in Long Channel MOSFETs
threshold voltage Body effect coefficient
An -4
Assume VDD = 2.5V
x 10
approximately 6
VGS= 2.5 V
linear
Vt = Vt 0 + γ ( − 2φF − VBS − 2φF )
5
relationship
between IDS Resistive Saturation
4

IDS (A)
and VDS VGS= 2.0 V

2qN Aε Si 2qN Dε Si D 3 Quadratic

γ NMOS = , γ PMOS = −
VDS = VGS - VT Relationship
with VGS
Cox Cox
2
VGS= 1.5 V

Bulk Fermi Potential Bulk Fermi Potential 1

for NMOS for PMOS G B
kT n kT N D VGS= 1.0 V

φF _ NMOS = ln i , φF _ PMOS = ln 0
0 0.5 1 1.5 2 2.5

q NA q ni S
VDS (V)
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Transistor in Linear Mode Voltage-Current Relation: Linear Mode

Assuming VGS > VT For long-channel devices (L > 1 micrometer)
VGS
VDS  When VDS ≤ VGS – VT Equation is valid for |VGS| > |VT|
S G
D ID
IDS = μnCoxW/L [(VGS – VT)VDS – VDS2/2]
n+ - V(x) + n+ where

L: diffusion distance (which is also the channel length)

x
k’n = μnCox = μnεox/tox = is the process transconductance
B parameter [μn is the electron carrier mobility (m2/Vsec) and
Channel extends all the way from the edge of source diffusion to the edge of drain εox is the oxide permittivity (F/m)]
diffusion
Channel length is equal to the distance between the edges of source and drain
kn = k’n W/L is the gain factor of the device
diffusion areas: Lchannel = Ldiffusion_distance
For small VDS, there is an approximately linear
Current is approximately relationship between VDS and ID, hence the name
a linear function of VDS in the linear region resistive or linear region
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Transistor in Saturation Mode Saturation Current at Channel Pinch-off

For long channel devices
Assuming VGS > VT Equation is valid for |VGS| > |VT|
 When VDS = VGS – VT

VGS VDS = VGS - VT IDS’ = 1/2μnCoxW/L [(VGS – VT) 2]

VDS
S G
D
ID
the voltage difference over the induced channel
(from the pinch-off point to the source) remains
n+ n+
- V -V +
GS T fixed at VGS – VT and the current saturates
 Current remains constant (saturates)
Pinch-off
 Square dependence of saturation current on gate
B overdrive
The current remains constant (saturates)  According to this simple model a saturated
in this mode MOSFET acts as an ideal current source
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What Happens if We Continue to Increase VDS After Weak Dependence of IDS on VDS in Saturation
Pinch-off? Channel Length Modulation
The length of the conductive channel is modulated by the applied (Channel Length Modulation)
X 10-4
6
diffusion_distance
VDS in saturation: Lchannel < Ldiffusion_distance ( channel )
V஽ௌ 5
VDS = VGS - VT VGS = 2.5V

IDS = 1/2μnCoxW/Ldiffusion_distance(VGS – VT) (1 + λVDS)

2
for VDS > (VGS – VT). λ is the channel-length modulation coefficient 4
VGS = 2.0V
Equation is valid for |VGS| > |VT| 3
VDS > VGS - VT Linear Saturation
G
2 VGS = 1.5V
D
S 1 VGS = 1.0V
n+ - (VGS – VT) + n+ 0
Lchannel 0 0.5 1 1.5 2 2.5
cut-off
VDS (V)
As VDS is further increased the pinch-off point moves
NMOS transistor, 0.25μm, L = 10μm, W/L = 1.5, VDD = 2.5V, VT0 = 0.4V
towards the source → channel length modulation
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Current-Voltage Relations Summary A Model for Manual Analysis

Saturation
Long-Channel Device
Equation is valid for |VGS| > |VT| Linear Region for PMOS:
VGD <= VT < 0
NMOS ≤ Linear region
Replace kn with kp for
PMOS

Equations are valid for |VGS| > |VT|

> CAUTION 1: In current equations, L is the diffusion distance (which is

NMOS also the channel length in linear region): Ldiffusion_distance
Saturation for PMOS: The distance between the edges of source and drain doping areas
VGD > VT
Equation is valid for |VGS| > |VT| Note the difference between drawn gate length and Ldiffusion_distance
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The Gate-Source/Drain Overlaps A Model for Manual Analysis
Equations are valid for |VGS| > |VT|
Polysilicon gate
L diffusion _ dis tan ce
=L drawn
− 2x d Saturation
Top view Ldrawn: drawn gate length
Source Drain Ldiffusion_distance: distance
W between the two
xd xd diffusion areas
≤ Linear region
n+ n+
Self-aligned gate: the
Ldrawn gate is self-aligned
Gate oxide with respect to the
edges of source and CAUTION 2: In the current
t drain by using the gate equations, use the correct
ox VT considering the body-
as a buffer zone
(physical mask) during bias conditions
n+ Ldiffusion_distance n+
the doping of source Note the
Cross section and drain islands difference
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A Model for Manual Analysis Transistor Model

BEWARE of the Replace kn with kp for for Manual Analysis
polarity of PMOS
parameters and Body-effect coefficient Channel length modulation coefficient
the direction of
current flow in ≤
NMOS and PMOS
transistors VTO: zero body bias threshold voltage
Replace kn with kp for γ: body effect coefficient (note that the actual VT is different
CAUTION 3: The equations PMOS than VTO if VBS is nonzero: nonzero body bias)
are valid for both NMOS VDSAT: Drain-to-source saturation voltage
and PMOS if you write IDS k’ = μCox = μ*εox/tox = is the process transconductance
for NMOS and ISD for parameter
Equations are valid for |VGS| > |VT|
PMOS transistors λ: the channel-length modulation coefficient
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MOSFET Current Summary nMOSFET Operation 6 ID

 Vdrain (t = 0-) = VDD
 IDS is a function of
5 VGS = VDD

 Vgs = 0 4
Assume VDD > VTNMOS

10-4 A
 VGS (> VT) 3

 Cut-off
 VDS 2 VDS = VGS - VT

 Vgs = VDD 1

 channel length: L VDS

0
Vdrain
 channel width: W
 Vgs – Vds = Vgd < VTNMOS 0 0.5 1 1.5 2 2.5

 threshold voltage: VT  Saturation

 thickness of the gate oxide: tox
– Transistor starts 0
conduction in the
 permittivity of the gate insulator (SiO2): εox
saturation mode VDD
 carrier mobility
 Vdrain <= VDD - VTNMOS
 for nfets: μn = 500 cm2/V-sec
 Vgd > VTNMOS
 for pfets: μp = 180 cm2/V-sec
 Linear
– Transistor later moves into the linear region
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pMOSFET Operation Examples

5V 5V 5V
 Vdrain(t = 0-) = 0 Assume VDD > |VTPMOS|
VDD
 Vgs = 0 p1 p2 p3
5V 2.5V
0V 2.5V
 Cut-off 5V 2.5V
VDD
 Vgs = -VDD n1 n2 n3
0
 Vgs – Vds = Vgd > VTPMOS
 Saturation -VDD
5V 2V
VDS
 Vdrain >= |VTPMOS| - Vdrain
VDS = VGS-VTPMOS - p4
 Vgd < VTPMOS -
n4

 Linear - 2V
Assume Vtn1 = Vtn2 = Vtn3 = 0.5V and Vtn4 = 0.8V
VGS = -VDD - What modes are the transistors in?
Vtp1 = Vtp2 = Vtp3 = -0.6V and Vtp4 = -1V
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Example 1 Example 2
VGSPMOS = 0V > Vtp1 5V VGSPMOS = 0V > Vtp2
5V
PMOS CUT-OFF p2 PMOS CUT-OFF
p1 5V
0V 2.5V
5V VGSNMOS = 5V > Vtn1 VGSNMOS = 5V > Vtn2
n2
n1
VGDNMOS = 5V > Vtn1 VGDNMOS = 2.5V > Vtn2
NMOS Linear NMOS Linear

Assume Vtn1 = Vtn2 = Vtn3 = 0.5V and Vtn4 = 0.8V Assume Vtn1 = Vtn2 = Vtn3 = 0.5V and Vtn4 = 0.8V
Vtp1 = Vtp2 = Vtp3 = -0.6V and Vtp4 = -1V Vtp1 = Vtp2 = Vtp3 = -0.6V and Vtp4 = -1V
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Example 3 Examples 4 and 5
VGSPMOS = -2.5V < Vtp3
5V 2V VGS = -2V < Vtp4
VGDPMOS = 0V > Vtp3 p4
p3 VGD = 0V > Vtp4
2.5V PMOS Saturation
2.5V PMOS Saturation
n3
VGSNMOS = 2.5V > Vtn3
5V
VGS = 3V > Vtn4
VGDNMOS = 0V < Vtn3
n4 VGD = 0V < Vtn4
NMOS Saturation
2V NMOS Saturation
Assume Vtn1 = Vtn2 = Vtn3 = 0.5V and Vtn4 = 0.8V
Vtp1 = Vtp2 = Vtp3 = -0.6V and Vtp4 = -1V Assume Vtn4 = 0.8V and Vtp4 = -1V
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