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TD 4 VHDL Correction

This document contains VHDL code for 4 exercises: 1. A D flip-flop with set/clear inputs 2. A JK flip-flop with set/clear and clock inputs 3. An RS flip-flop with set/reset and clock inputs 4. A 4-bit shift register that can shift left, right, or pass the input depending on a 2-bit shift control input

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30 views3 pages

TD 4 VHDL Correction

This document contains VHDL code for 4 exercises: 1. A D flip-flop with set/clear inputs 2. A JK flip-flop with set/clear and clock inputs 3. An RS flip-flop with set/reset and clock inputs 4. A 4-bit shift register that can shift left, right, or pass the input depending on a 2-bit shift control input

Uploaded by

benazizaaya8
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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AU : 2020/2021

Synthèse VHDL Filière : LSE2

Travaux Dirigés n°4


Exercice 1 : Bascule D

entity basculed is
Port ( setclear : in STD_LOGIC_VECTOR (1 downto 0);
Clk,d: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (1 downto 0));
end basculed;
architecture Behavioral of basculed is
begin
process (setclear ,clk)
begin
case setclear is
when "01" => Q<="01";
when "10" => Q<="10";
when "11" => Q<="XX";
when "00" =>
if clk’event and clk=’1’ then
Q<=d;
end if;
end case;
end process;
end Behavioral;

Exercice 2 : Bascule JK

entity basculejk is
Port ( setclear ,jk : in STD_LOGIC_VECTOR (1 downto 0);
Clk: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (1 downto 0));
end basculejk;
architecture Behavioral of basculejk is
signal a,b: STD_LOGIC;
begin
process (setclear ,clk)
begin
case setclear is
when "01" => a<=’0’; b<=’1’;
when "10" => a<=’1’; b<=’0’;
when "00" => a<=’1’; b<=’1’;
when "11" =>
if clk’event and clk=’0’ then
case jk is
when "00" => a<=a; b<=b;
when "01" => a<=’0’; b<=’1’;
when "10" => a<=b; b<=a;
when "11" =>

end if;
end case;
end process;
Q(0)<=a;
Q(1)<=b;
end Behavioral;

Exercice 3 : Bascule RS

entity basculers is
Port (rs : in STD_LOGIC_VECTOR (1 downto 0);
Clk: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (1 downto 0));
end basculers;
architecture Behavioral of basculers is
signal a,b: STD_LOGIC;
begin
process (clk)
begin
if clk’event and clk=’1’ then
case rs is
when "00" => a<=a; b<=b;
when "01" => a<=’0’; b<=’1’;
when "10" => a<=’1’; b<=’0’;
when "11" =>
a<=’X’; b<=’X’;
end if;
end case;
end process;
Q(0)<=a;
Q(1)<=b;
end Behavioral;

Exercice 4 : N2décalage

entity decal is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
clk: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3downto 0));
end decal;
architecture Behavioral of decal is
signal a : std_logic_vector(3 downto 0);
begin
process (b)
begin
if clk =’1’ then clk’event then
if S=”01” then
a<=I;
elsif S=”10” then
a(0)<=a(3);
a(1)<=a(0);
a(2)<=a(1);
a(3)<=a(2);
elsif S=”11” then
a(0)<=a(1);
a(1)<=a(2);
a(2)<=a(3);
a(3)<=a(0);
end if;
end if;
end process;
Q<=a;
end Behavioral;

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