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NOC design methodology

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 2B1457 Special Topics in SoC KTH, Stockholm, Sweden

NOC design methodology

Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Outline

• Part 1: Introduction

• Part 2: Design methodologies

• Part 3: Design flows

• Part 4: Network-on-a-Chip design methodology

Special Topics in System-on-Chip 2

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Part 1: Introduction

• Why system design is difficult?

• What is design methodology?

• Why networks on chip?

Special Topics in System-on-Chip 3

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Part 2: Design methodologies

• What kind of products should be developed?

• Business strategies

• Organization of work and design processes

• Quality issues

Special Topics in System-on-Chip 4

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Part 3: Design flows

• Algorithm on Chip (AoC) design flow

• Computer system design design flow

• System on Chip (SoC) design flow

• Codesign flow

• Platform based design flow

Special Topics in System-on-Chip 5

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Part 4: NOC Methodology

• Requirements for NOC Methodology

• NOC quality criteria

• NOC design views

• NOC layers
• NOC domains
• NOC design phases

Special Topics in System-on-Chip 6

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 NOC design methodology
Part I: Introduction

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Network on Chip

SOC
SOC SOC
NOC - a chip with several
SOC integrated computer systems
SOC that communicate with each
SOC SOC other via network.
SOC

SOC
SOC
SOC

Special Topics in System-on-Chip 8

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Network on Chip Design Methodology?

• No real NOC systems exists yet

• no real case examples of NOC development exists
• we do not know exact applications for NOC systems
• we do not know exactly how NOC systems will look like

• NOC can not be designed using existing tools and methods

• complexity problems
• interoperability problems
• solutions to some design problems are missing
• no implementations of design methodologies exist

Special Topics in System-on-Chip 9

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

What do we know then?

• Trends in technology development

• How companies operate and what are their targets
• Basic laws of industrial product development
• Principles of design methodologies
• How development processes evolve
• Capabilities of current methods and tools

• …so we can predict and make educated guesses what will happen
• …and we can set up requirements for researchers and developers

Special Topics in System-on-Chip 10

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Outline

• Why system development is difficult?

• Product lifecycles, complexity issues, required skills and communication
• Effects of decisions, couplings, abstraction levels
• What is design methodology?
• Purpose
• Quality and success factors
• Processes, methods and tools
• Why networks on chip?
• Technological motivation
• Design productivity motivation
• complexity
• management

Special Topics in System-on-Chip 11

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Typical product development trend

Information More
access to complex
anyone More protocols
mobile
users
More information
More computation
with less channel
capacity
Information
More transfer
access at
capacity needed More
anytime
More complex complex
More mobility algorithms products
for appliances
Mobile data
Information processing
access from applications More data for
everywhere each user More storage
capacity

Information
access to More reality-
like user
everything interfaces

Special Topics in System-on-Chip 12

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Complexity scenarios

Complexity
User needs

Theories & Algorithm requirements

Science
Manufacturing
technology &
physics Technology capabality
Design
practices
Tools
and Design productivity
methods

Verification capability

Time

Special Topics in System-on-Chip 13

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

What we must know?

Manufacturing
design
System
design Production
design
Business Project Mechanical
analyses design design
Design

Conceptual
design
Requirement System Computation
IDEA Structure
analyses Functional resource
design design
design
Architecture
Algorithm design
Feasibility design Functional
analyses Software HW
architecture design
Physical requirements
Architectural requirements
Software
Functional requirements
design
Special Topics in System-on-Chip 14
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Minimisation of alternatives

It is important to see, where our

design choices lead to, and is the
target the right one.

Conceptual Algorithm Architecture Implementation

design design design design

Product

Possible
design
Product space
Concepts
Product Each design decision removes
Idea possible (good) implementations
from design space.
Special Topics in System-on-Chip 15
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Quality at different abstraction levels

bit/s/Hz/m3
System level number of users, mobility, etc.

Operation time,
Product level physical characteristics,
set of services, usability

Service level QoS, information transfer speed,

access times, etc.

Functional level BER, through put,

response times, etc

Architecture level Operations per second per Joule

Technology level IPC, fclk

tr,tf,

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Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Criteria of Quality

• For product
• market success (customer satisfaction)
• For algorithm
• performance (functional)
• implementation complexity (cost, energy)
• mappability (components, communication)
• For architecture
• performance (computational, efficiency)
• modularity (components, communication)
• For implementation
• performance (environmental, manufacturability)

• Criteria for subsystems or abstraction levels

must be sacrificed for the criteria of product
Special Topics in System-on-Chip 17
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Coupling effects

Channel Analogue/RF Baseband Network Applications

Mathematical Standards Specifications

Mathematical formulaes
abstractions
of
Channel componetns Algorithms Protocols
model

Simulation models Software

Simulation
models of
components
Hardware model of computer system

Implementation of a telecom product

Physical Physical
channel components

Coupling in real product

Determines the quality

Special Topics in System-on-Chip 18
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

What is a design methodology?

• A design process - a sequence of steps necessary to build a system

• Important issues in methodologies:

• product metrics (what are we trying to achieve)
• models
• abstraction levels
• description languages (models of computation)
• design flows
• design activities
• milestones
• verification and validation
• organizing the work and communication

Special Topics in System-on-Chip 19

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Factors that effect on the design methodology?

Product Safety
Product type issues
complexity
Product
Technologies purpose Security
Design
issues
Methodology

Methods Cultural
Available issues
tools Business
issues
Strategic
decisions
Special Topics in System-on-Chip 20
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Product development activities

Define Validate Estimate
Analyse
product user market
user needs
concept satisfaction success

Define
Analyse Validate Estimate
functionality
requirements performance complexity
(algorithms)

Define
Analyse Validate Estimate
structure
workload capacity costs
(architecture)

Analyse Design/Reuse Validate Estimate

characteristics objects functionality feasibility

Analyse Estimate
Design Validate
physical production
product quality
requirements costs

Analyse Measure
production Implement Test&Sell market
flows success
Special Topics in System-on-Chip 21
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Design Processes and Flows

Requirements Applications Architecture

Specification
Design
Implementation
Testing Mapping

Sequential model
Function on
micro-architecture

Implementation
Specification
Specification
oriented model Partitioning Mapping oriented
Design
model

Integration
Special Topics in System-on-Chip 22
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Generic design activity

What will be the eventual

Are we still developing the right
outcome?
system? Validate/
Verify/ Does it fulfil the initial criteria?
Was the abstraction level Test
change done correctly? Estimate

Development support Decision support

Previous
phase Analyse Define/
Design/
Refine/ Next
Implement phase

What was done in previous step?

What must be done now?
What are the criteria for success? Change of abstraction
level
Special Topics in System-on-Chip 23
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Roles and communication

Algorithm
developer

Architecture developer
Functional
design
Concept
creation Architecture
Business design
developer
Hardware
System design
Architect
Software Hardware designer
design
Production
designer Implementation
Software designer

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Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Problems with complex system design

• Each domain (behavioural, structural, physical) has its own unique

problems that requires special expertise. Nobody can do everything.
• The activities of each domain have their own predecessors and
successors both inside and outside domains. But each product type has
unique flows. Single, generic design flow is impossible.
• Understanding coupling of different parts of system and making trade-
offs between different domains of designs is difficult.
• Work should be supported by tools that predict what are the
consequences of design decisions to whole product.

Special Topics in System-on-Chip 25

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Why networks on chip?

• Alternatives for extremely big chips:

• Parallel computer system
• network between computers
• parallel programming model
• One processor chip
• network inside the processor
• uniform programming model
• NOC (integrated distributed computing system)
• distributed computing model
• encapsulation of different types of subsystems

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Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Complexity of Chip

Future SoC capacity exceeds 1 billion

transistors within next 5 years

If average design time of 1 million

transistors (=1 SOC) would be 10 person
years then average design time of 1 billion
transistors would be >1000 person years…!

We need
STRUCTURING
ENCAPSULATION
REUSE

= Network on Chip

Special Topics in System-on-Chip 27

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Complexity of System

Mask cost of current ASIC is approaching

1M$ mark

Design time of ASIC is one the critical path

of system design

We need to reuse the ASIC design effort

We need
FLEXIBILITY
PROGRAMMABILITY
RECONFIGURABILITY

=> Network on Chip

Special Topics in System-on-Chip 28

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Why do we need NOC design methodology?

• Nothing else works…

• We need to combine
• ASIC design (physical aspects) with
• SOC design (computer system aspects) with
• Embedded system design (software aspects) with
• Networked system design (communication aspects) and

• we have to understand testability issues, parallel system design,

configuration design, low power design, programming principles,
etc. while doing it.

Special Topics in System-on-Chip 29

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Summary

• System (product) design needs knowledge from many different sources

• Basic elements of design methodology

• processes
• flows
• methods
• tools
• practices
• Networks on chip are needed
• to manage complexity of HW design
• to reuse the hardware in products

Special Topics in System-on-Chip 30

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 Part2: Design Methodologies

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Outline

• Purpose of the product

• customer satisfaction
• economics
• How companies operate?
• Operation principles
• Competitive strategies
• Product platforms
• Development processes
• Quality

Special Topics in System-on-Chip 32

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Why products are developed?

• Answer: to make money ...

• Question: Why do we want to make money?
• Answer: to buy “things”...
• Question: Why do we want to buy “things”?
• Answer: to make our life easier...
• Question: Why do we want to make our life easier?
• Answer : so, we can do what we want to do…
• Question: Why do want to do things that we want to do?
• Answer: to feel better…

• Products are developed to increase our welfare

Special Topics in System-on-Chip 33

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

What kind of products should be developed?

• Products that do what they are meant to do

• we are buying services - not things

• Products that do ONLY what they are meant to do

• paying for a feature you do not need is waste
• safety issues, environmental issues

• Products that serve for their whole lifecycle

• from manufacturing to disposal

Special Topics in System-on-Chip 34

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Model of a company
Knowledge

Legal maters
Research

Management
Design
Money
EDA tools Accounting

Purchase

Materials
and components Products

Manufacturing Sales Maintenance

Marketing

Manufacturing tools Market needs © Hannu Heusala, University of Oulu

Special Topics in System-on-Chip 35

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Value chain

Infrastructure
Supporting
Personnel
Pr

functions
of
it

Technology development
Purchase
Maintenance
Operations

Sales and
marketing

Basic
logistics

logistics

it
Output

of

functions
Input

Pr

Special Topics in System-on-Chip 36

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Money flow

Incomes

TTP
Money flow

TTM Profit

Time

Complexity Competition
Market window
Investments
Special Topics in System-on-Chip 37
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Strategy and design methodology

• Strategy = Plan how to succeed

• Strategy for
• business (competitive advantages) +
• product (e.g. product range, product families) +
• processes (e.g. design methodologies)

• Strategic plan
• should consider strengths, weaknesses, opportunities and threads
(SWOT analysis)
• should position yourself with respect to others
• should say where to proceed and how to start

Special Topics in System-on-Chip 38

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Definition of Business Strategies 1/3

Purpose of product
Functions included
into a product

Target customers

Chosen Customer
implementation segments
technologies

Technology

Special Topics in System-on-Chip 39

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Definition of Business Strategies - 2/3

Incremental development, search

Maturity of markets of technology limits

Dominant product
concept, focus in
production optimization
Specialized
New cycle with
Product changes, new Transitional new innovations
ideas, new concepts Emerging

Time

Special Topics in System-on-Chip 40

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Definition of Business Strategies - 3/3

Maturity of industry
New products are replacing
the products

Mature Declining
Lot of small companies,
new technologies, Growing
easy to set up a company
Fragmented
Time

Special Topics in System-on-Chip 41

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Competitive advantages
CUSTOMER BASIC

Broad Cost leadership Differentiation

Custom-
Narrow Focusing ization

COMPETITIVE
ADVANTAGES

Special Topics in System-on-Chip 42

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Customization alternatives

• Customization of services in standardized platforms (Telephone

services, SW with training packages)
• Design customizable products (Built in configurability)
• Customize the product when sold (Configure by user specifications)
• Manufacture by specifications only (Cars, Power Plants)
• Combine customized products from modular components
• Share components
• Change components
• Scale components
• Combine components to new components
• Attach components to standard interfaces
• Have standardized interfaces between components

Special Topics in System-on-Chip 43

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Product Family Classes

Products based
Amplifier A100
on same technology
Different products
XLPD-4002 Amplifier A200 for different user
for same purpose
Amplifier A300
XLPD-4025
XLPD-4001

Technology Family Version Family

Device Family Generation Family

New versions of
CD-Player same product
Products form
desired functionality
together

Tube Radio Transistor Radio

Tape Deck
IC Radio
Amplifier
Special Topics in System-on-Chip 44
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Product platforms & platform products

• Product platform
• generic product or core product from which new versions are
instantiated
• also a product by itself
• typical in software (for example embedded RT-OS)

• Platform product
• kernel (or core) of a product family
• not a product by itself
• products are developed by adding components and features to the
kernel

Special Topics in System-on-Chip 45

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Platform products -Kodak example

Funsaver II
Funsaver I Portrait
Flash
Platform
change Weekender Eagle
Stretch Weekender II

Stretch II

1988 1993

© S.C. Wheelwright, Harvard Business School

Special Topics in System-on-Chip 46

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Platform Chips

Platform chip concept

Application area
specific engine
Product
generations

Product
variants

Implements
processing
requirements

Special Topics in System-on-Chip 47

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Development processes

• Waterfall process
Organization • Spiral process
of work • Successive refinement
• SW/HW codesign
• Function/Architecture codesign
• Platform based design

• Total quality management

Product Quality • ISO9001
characteristics assurance • CMM
• Quality function deployment
• Taguchi method
Special Topics in System-on-Chip
• QC 48
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Organization of work

Design steps

Requirement analysis
Support Quality assurance

Languages Specification Validation Infrastructure

Users
Models Architecture design Verification Resources
Technologies
Methods Testing Processes
Implementation
Tools Measuring
Integration

Manufacturing

Special Topics in System-on-Chip 49

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Structure of activities
Define Validate Estimate
Analyse
product user market
user needs
concept satisfaction success
In real company:
Define
Analyse Validate Estimate
functionality
requirements performance complexity
(algorithms) Number of activities is large.
Define Difficult to plan beforehand.
Analyse Validate Estimate
structure
workload capacity costs Must be adjustable (be ready to
(architecture)
respond to changes).
Analyse Design/Reuse Validate Estimate
Must be stable (do not create
characteristics objects functionality feasibility
new problems with unnecessary
changes).
Analyse Estimate
Design Validate
physical production
product quality
requirements costs

Analyse Measure
production Implement Test&Sell market
flows success

Special Topics in System-on-Chip 50

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
 VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Ordering of activities

Requirements
Specification Parallel model
Design
Implementation
Testing

Sequential
model

Applications Architecture Mapping

Specification
Specification oriented
oriented model model
Partitioning
Mapping

Design
Function on
micro-architecture
Integration
Implementation
Special Topics in System-on-Chip 51
Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

People and processes

No one knows everything!

Functional
design
Concept
Architecture Teamwork and responsibility
creation
design
Hardware
System design Cumulative knowledge
Architect
Software
design
Intellectual capital management
Implementation

Special Topics in System-on-Chip 52

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Concurrent engineering

• Objective to optimize the complete product development process

• Basic elements:
• cross-functional teams
• concurrent product realization
• incremental information sharing
• integrated project management
• early supplier involvement
• customer focus

Special Topics in System-on-Chip 53

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Quality

• Definitions
• Conformance to specification
• Loss caused by defects
• Properties with respect to competitors
• performance
• features
• cost
• Customer satisfaction
• basic quality - if not met, product fails
• expected quality - better implementation increases satisfaction
• exciting quality - surprises the customers positively (sales
point)

Special Topics in System-on-Chip 54

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Quality assurance

• Process level techniques

• Total Quality Management
• ISO 9001
• Capability Maturity Model
• Specification level techniques
• Quality Function Deployment
• Taguchi Method
• Design level techniques
• Validation, verification, prototyping, etc.
• Quality control techniques
• Design reviews, measurement techniques, etc.

Special Topics in System-on-Chip 55

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Total Quality Management

• Final check
• fix defects
ACT PLAN
• Quality control
• monitor process
• collect statistics
• Quality assurance
• create quality during the design
• Total quality control CHECK DO
• improve company’s operation
• customer focus
Continuous improvement
• Total quality management process
• measure and develop processes

Special Topics in System-on-Chip 56

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

ISO 9000

• Origin in British car industry

• Concentrate on processes
• Important issues
• Processes must be documented
• Documents are important for sharing information
• Communication is necessary to understand the quality process

• Gives an overall view to the development

Special Topics in System-on-Chip 57

Networks-on-a-Chip & High Performance Analog Design in SoC
17.5.2002 Juha-Pekka Soininen

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Measuring a development process

CMM Capability Maturity Model

(measuring the quality of software development process)
Optimizing
Managed Continuous
improvement
Defined
Detailed
Repeatable measurements
Documented
Initial methods
Basic tracking

Individual efforts

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Summary

• BUSINESS ISSUES
• competitive strategy
• business situation
• PRODUCT TYPES
• mass productions Design
Effects on
• customization methodology
• sales points
• PROCESSES
• how work is organized
• design flows (in next part)
• quality issues

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Part 3: Design flows

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Extremely short introduction to

existing design flows

• Algorithm on Chip (AoC)

• Algorithm design
• ASIC design flow
• FPGA design flow
• Computer system design
• ASIP design flow
• Software design flow
• System on Chip (SoC)
• Codesign flows
• generic flow
• VCC, SystemC, Coware
• Platform based design flow

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SoC design process

3rd party
suppliers
Software
Development Validation &
RT-OS Process Verification
SoC T1 50km

SW design
SoC T1 50km

Database Software SW/HW

design system Codesign Implementation
Specification Process DSP software design Process
Process Data storage SoC T1 50km
SoC T1 50km SoC T1 50km

System
SoC T1 50km Testing
User SoC T1 50km
Integration SoC
Control Architecture Computer
Needs Design
Manufacturing Product
system PCB design
Data flow Process Hardware
system Application FPGA design
Algorithm specific SoC T1 50km

design hardware
ASIC
Hardware Design
Development Process
Analysis & Process
Estimation
Intellectual
Property
suppliers
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Design Flow Space

profiling simulation synthesis emulation System exists

monitoring

workload design
Function development

analysis cosimulation
prototyping
mappability
complexity estimation
analysis
estimation
capacity
mathematical estimation
analyses
performance performance
modelling analysis simulation
benchmarking
System
does
Resource development
not exist
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AoC Design Flow

Algorithms profiling simulation synthesis emulation Chip
exists exists
HW design
Function development

Algorithm changes into

design functionality
complexity
analysis
feasibility
studies
mathematical
analyses

modelling
System
does
Resource development
not exist
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Algorithm development (in AoC)

Algorithm Matlab
model
Analytical
validation
Block Floating point Cossap
library model System Studio
Stream
driven
Fixed point simulation Cossap
Block library
model System Studio

VHDL/C-
model

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Specification
Development Synthesis
scripts
generation
ASIC Design Flow RTL-code
development
Synthesis

Functional
verification
Scan insertion

Synthesis

ATPG

Pre-layout
timing
verification Functional
timing
verification

Place and
route
Manufacturing
test timing
Post-layout verification
timing
verification

Chip testing

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FPGA based systems

profiling simulation synthesis emulation

Algorithms HW design
exists
Control functions
Mapping to
Function development

FPGA
Algorithm
resources
design
complexity
analysis

mathematical
analyses

modelling
System
does
Resource development
not exist
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Computer design
System
exists
Function development

performance
analysis
performance
simulation

modelling Computer design benchmarking

System Computer
does exists
Resource development
not exist
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ASIP design flow

System
exists

Software Basic Final SW

Function development

model architecture

Computer
exists
Initial SW IS design
performance estimation
analysis
performance
simulation

modelling benchmarking
System
does
Resource development
not exist
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Software Design
System
exists

monitoring
Function development

prototyping
SW design

estimation
System RTOS
model services +
Mapping to computer computer
modelling benchmarking
System
does
Resource development
not exist
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SOFTWARE ARCHITECTURE
Logical view Development
- What is the functional decomposition Algorithms
view
- Components: control objects, algorithms etc.
- How the system is
realised with todays's

Functional entities,
complexities
software platforms
and technologies
- Components:
application module,
driver, operating
system etc.
Physical view
- How the system is mapped to hardware platform Hardware drivers
- What is the hardware/software partition
- Components: processors, ASICs etc.
Objects mapped to

resource usage
HW platforms,

Process view Processes,

communication
- How the system works in runtime environment methods
- Components: processes, threads, data stores etc.

Execution view

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Relationships to the other research topics

HW Architecture
Algorithms

Logical view Physical view

SW Architecture

Development
Process view
view

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SW Architecture Development Process

ANALYSE
REQUIREMENTS

SELECTION

DEFINE DEFINE DESIGN

DEFINE DEFINE MODEL DESIGN Architecture
DEFINE
PROBLEMS STRATEGIES
DEFINE MODEL RATIONALE
DESIGN
PROBLEMS
DEFINE STRATEGIES
DEFINE MODEL RATIONALE
DESIGN specification
PROBLEMS STRATEGIES MODEL RATIONALE
PROBLEMS STRATEGIES RATIONALE

Refine

OK
EVALUATION

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Logical view (UML)

Use cases
Class models Transceiver::Controller

Monitor inputs Code uses

Transmit 1 1
uses messages
messages

uses Owns
uses uses
Network
1 *
Control
resources Transceiver::Configurator
1 * Transceiver::Connection
uses uses 1
Specifies
Execute Control Control 1
applications uses connections uses transmission
Transceiver::Configuration data 1
Scenarios
User

uses uses uses

uses myController myConnection myConfigurator Configures
Description :Controller :Connection :Configurator
Maps Consists of
Transceiver::Mapping data
Radiolink
Message to a connection RL-SETUP
Generate
If not found create Connection Decode
outputs uses create
uses Receive
messages messages
Forward event RL-SETUP
* * *
If not all services call Configurator configure
Handle original event Transceiver::Algorithm* 1 Transceiver::Service
init
{Abstract} {Abstract}
When ready send CONFIRMATION CONFIRMATION Realizes

Data flow descriptions

Pulse Channel
Modulation Spreading
shaping encoding

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Physical view

<<HW Component>>
DeSpreade r

Physical model

HARDWARE
ARCHITECTURE <<Exte rnal SW>>
<<Proce s sor>>
Code c
<<Processor>>
S ync
<<HW Component>>
FrontEnd
Protoc ols

- definition of HW
components
- logical components <<HW Component>> <<Sh a red memory>>

mapped to HW CodecAc c CommonAreaForAllNodes

components

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Process view
Mapping tables
Process Logical components

Pipeline manager Controller, Connection, Services Design rationale

Resource manager Configurator, Configuration data, Mapping table Problem Selected solution Explanation Alternative solutions

How data processing Pipes and filters style Strategy: Allow dynamic Blackboard style, if system
WcdmaTxBit CRC attachment, convolutional coding, turbo coding, interleaving
Transceive r tasks are arranged addition and deletion of has to be able to select
algorithms connections. between different

Metamodel 1
WlanTxBit 1 1
1
Scrambling, convolutional encoding, interleaving, sub-carrier
modulation algorithms
alternative
implementations to a
service during run-time.

WcdmaRxSoftbit Deinterleaving algorithms One filter/node in one Strategies: 1. Proposed:

pipeline. - Separate uplink and WcdmaCrcAttachment,
WcdmaRxBit CRC checking algorithms Synchronisation downlink connections. WcdmaTurboCoding and
1..* 0.. * 1 processes separated - Critical functionality is Wcdma Interleaving to
1
WlanRxBit +controls
Descrambling algorithms mapped to a separate separate processes
Nod e +assigns re sourc es from +assigns resource s to process.
Resource Manage r Pipeline PipelineMa nager
- Hardware functionality 2. Proposed:
GsmTxBit Channel coding, interleaving, ciphering algorithms WlanFrequencyErrorCorre
in the middle of data
0..* processing chain. ction, WlanFft and
GsmRxBit 0..* Deciphering, deinterleaving, channel decoding algorithms - Avoid context switches. WlanFrequencyDomainEq
+a ssigne d to ualisation to separate
processes.
1.. *
1..* How control of data Pipeline manager for Strategy: Use separation of Removed solution: one
+uses +u ses processing is control and Resource concerns Controller for everything
Filter P ipe

0.. *
IP C
Scenarios arranged manager for resource
management
because it would have
been too complex to
maintain.

All processes are Proposed: inactive

active all the time processes could be
<<P roc e ss >> / wc dma TxBitR1
: W c dma TxBit
/ wc dma RxBitR 1
: W c d ma R xBit
/ wc dma R xS oftbitR1
: W c dma RxS oftbit
/ wla nRxBitR 1
: W la nRxBit
/ wla nRxSymb olR 1
: W la nR xS ymbol
/ de S pre a de rDrive rR 1
: De S pre a de rDriv e r
removed but
/ c ode c Ac c Drive rR 1 this
: Code c Ac c Drive r
/ froncauses
tEn dDriv e rR1
: Fro ntEndDrive r
W c d ma S ync hronisa tion too much complexity
0.. * compared to benefits.

Collaboration
DataP roce ss HWComponent Driver
/ protoc ols R1
: P ro toc o ls
1 .1 Resources controlled
1.2
by Resource manager
Strategy: Allow shutdown
of unused resources. 1.3
/ d e S pre a de rR 1
: De Sp re a de r

<<Proce ss> >

diagrams GsmR xS ymbo l One HW driver/HW

node 2.2
Centralised control of HW
nodes.
2.3
1. Removed solution: One
2.1
driver/processor/HW node
2.4
+IP C 2. Proposed: One 2.5
+IP C
2.6 driver/HW component.
2.7

<<Proc e ss >>
<<Drive r>> 3.1
Gs mTxS ymbol
FrontEndDrive r 3.2

3.3
+ IPC 3.4
FrontEnd 3.5
3.6
Cod e c
<<P roc e s s>> 3.7
W la nTxSymb ol

<<P roc e s s>>

W la nR xS ymbol

<<P roc e s s>>

W la nS ync hronis a tion

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Development view
Design rationale
Module structure Problem Selected solution Explanation Alternative
solutions

How the complexity of A separate layer hides Strategy: Use Addition: Two
Applic a tion hardware is hidden from the HW. separate layer for sublayers: one for
the application hiding HW driver-processes
programmer accelerators and one for low-
level driver-
functions.

How control and data Algorithms are in Strategies:

processing is separated separate layer from - Use separate layer
process modules. APIs for algorithms
are used for - Put components in
communication between different abstraction
components. level to different
layers
- Create general
Support APIs for
Algorithms communicating
between layers

De vic e s

Mapping tables
Module Logical component

Pipeline manager process Controller

Resource manager process Configurator

Data process One or more Services

Algorithm Algorithm

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IEEE P1471 Conceptual Framework

Mission
fulfills 1..*

influences has an
Environment System Architecture
inhabits

has 1..* described by 1

identifies Architectural provides
Stakeholder Rationale
1..* Description
1..* 1..*
is important to is addressed to
participates in
has
1..* identifies 1..* selects 1..* organised by
1..*
conforms to
Concern Viewpoint View
1..* 1 1
used to cover 1..*
has source 0..1 participates in
Library consists of
Viewpoint
1..* 1..* 1..* aggregates
establishes methods for
Model

By IEEE Computer Society Architecture Working Group

form Introducing P1471 Recommended Practice for Architectural Description, 30 March 1999

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General High-Level HW/SW Co-design Flow

System
Specification

Architecture
Design

HW/SW
Partitioning

Hardware
flow

Simulation

Software
flow

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CoDesign Flow
profiling simulation synthesis emulation System exists

monitoring

workload
Function development

analysis cosimulation
SW/HW prototyping
partitioning mappability
estimation

capacity
mathematical estimation
analyses

modelling
System
does
Resource development
not exist
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SpecC design flow

Specification driven flow

Modeling engine
Refinement engine
Exploration engine
Synthesis engine

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IP Based Design
emulation System exists

monitoring

workload
Function development

analysis cosimulation
prototyping
mappability
estimation

capacity estimation
mathematical estimation
analyses Architecture
template
IP block
modelling integration
System
does
Resource development
not exist
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SystemC design flow

IP blocks in SystemC Algorithms in SystemC

Architecture SystemC Functional

model model

SW/HW
System C cosimulation
performance evaluation
TLM simulation

Physical
System C synthesis
design
and compilation to C/C++

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Open SystemC Language

SystemC 1.0 SystemC 2.0

• A C++ class library for RTL modeling • Superset of SystemC 1.0

• Modules • Events and dynamic sensitivity

• Processes • Interfaces
• Ports and signals • Channels
• Data Types
• Elementary library models (FIFOs,
• Includes simulation kernel timers, semaphores…)

• Targeted for synthesis • Targeted to system-level modeling

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•Algorithm
•Algorithmrefinement
refinement
•Atomicity
•Atomicityrefinement
refinement
•Data
•Datarefinement
refinement
•Communication
•Communication
refinement
refinement

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SystemC based Design Flow (continued)

Pros: Cons:

• Same language for • New language for most designers

• System-level • Still evolving rapidly
• RTL • Software modeling support in its
• SW infancy
• Test-bench reuse • Tool support concentrated to
• Strong commitment from EDA Synopsys (at least for synthesis)
vendors and design community

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SystemC Tools: Synopsys CoCentric System Studio

• Adds SystemC domain in addition to functional domain for architecture

design
• Generates and updates code skeletons of SystemC models
• Graphical editing of hierarchical SystemC models
• Adds an instrumentation support library for instrumentation of
architecture
• Provides macro- and C-level debugging environment
• Provides simulation engine that allows co-simulating architectural and
functional domain models

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VCC Proposed Design Flow

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VCC Proposed Design Flow (continued)

• Input languages and models

• C, C++, Matlab, SDL, SPW,
• Different views for different uses:
• behavior view,
• data type view
• architecture view
• mapping view
• simulation view
• analysis view (performance modeling, software estimation, communication
analysis)
• OMI 4.0 (IEEE Std. 1499) compliant simulator
• Links to Cadence implementation flow
• Cadence halted sale of VCC in March 2002. New product planned for
3Q/2002!
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CoWare N2C-based Design Flow

Functional Graphical editing of blocks,

un-timed functionality described in C

Manual timing of procedures,

BCA Shell bus protocol specification

BCA

C-code with timing,

detailed bus specifications

Implementation
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CoWare N2C-based Design Flow (continued)

• Co-specification -> Co-simulation -> Interface Generation

• Separation of behavior and communication
• Processor Support Package (PSP) capture processor and bus knowledge
• ISP (Instruction set simulator package)
• SSP (software support package)
• BSP (bus support package)
• Interface synthesis
• SW: generation of low-level drivers (memory-mapped registers or interrupt
service routines => headers, code, makefile documentation, library)
• HW: generation of interface logic (protocols, address decoders for complete
memory map, interrupt priority encoders, bus arbiters and bridges
• Also HW-HW IF synthesis
• Works for processor centric architecture (memory-bus and memory/interrupt
mapped architecture)

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SoC design flow in platform based design

Application 1 Application 2 Application 3

Fixed Manufacturing Fixed Manufacturing Fixed Manufacturing
Platform A Platform B Platform C

System Integration System Integration System Integration

Integration Platform A Platform B Platform C
platform layer
Software Software Software Software
hierarchy IP IP IP IP

Hardware Hardware Hardware Hardware Hardware

VC VC VC VC VC

Programmable IP Programmable IP

IC Integration IC Integration
Platform 1 Platform 2

Silicon Design Flows (TDD, BBD, PBD)

VC Access, Qualification, Support and Migration

from Surviving the SOC Revolution by Chang et.al. Kluwer 1999

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Platform based design

Application space

Design flow consists of a

sequence of platforms
Platform
specification
System platform

Platform Upper level objects

design-space are mapped to lower
level objects
exploration

Architectural space

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Metropolis methodology
Design of Design of Design of
function communication architecture
processes media components

Metropolis infrastructure
Model of computation
Design methodology
- abstraction levels
- refinement
Base tools
- design imports
Point - user interface Point
tools - simulation
tools

Synthesis/Refinement Analysis/Verification

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Summary of design flows

• Main phases
• functional modeling and validation
• architecture design and verification
• implementation design and verification
• integration and testing

• Choices
• Functional modeling vs Resource design
• Synthesis vs. Mapping

• Industrial flows depend on tools

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Part 4: NOC design

methodology
VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Background

• Mission:
• How to develop a system that uses 1 billion transistor capacity
effectively in 2007-2010

• Maturity of current NOC design methodology:

• 3rd guess on how NOC based systems should be developed

• Related methodologies:
• distributed systems
• parallel processing systems
• systems on chip and ASIC design

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NOC Methodology outline

• Requirements for NOC Methodology

• NOC methodology challenges
• Capacity considerations
• Possible NOC scenarios
• NOC quality criteria
• Why platform based design approach
• System services
• Architecture design problems
• Application development problems
• NOC design views
• NOC layers
• NOC domains
• NOC phases

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Capacity of Network on Chip

Average SoC design ≈ 1 million gates

1 billion transistors ≈ 250 million gates
1 NoC > 200 SoCs

10 computers
1 GHz clock with RISC computer ⇒
1000 MIPS performance

1 NOC capacity ≈ 100-10000 GIPS

Applicability of capacity is limited by

communication

10 computers

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“Applications” for NOC

Piece of cake
• Multistandard terminal
• Next generation base station
• Simulation of human brain Realistic
applications
• Virtual reality creation
• Telepresence
Maybe not
• Holodeck (Star Trek) even for NOC
• Purpose of Life (Hitch Hikers Guide to Galaxy)
• Simulation of universe Real
• Commercial operating system :-) challenges for
every
archtitecture

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Application characteristics

NOC capacity Control WLAN communication

will be shared
by several Speech recognition
simultaneous
applications
NOC must be
Image processing adaptable to
Different applications different workload
have very different patterns
Stream-
requirement profile based
Storage processing
Computation
tn tn+p
Parallel
processing Real-time
processing
Communication
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Basic concepts

Region:
area that has been isolated from other
network by wrappers
area that can be dedicated to parallel
computer, memory, eFPGA, etc.

Resource:

a SoC with a network interface

a synchronous clock area

Network:

Asynchronous message passing network

Switches with buffers

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Network on Chip alternatives

NOC = Network of computation and

storage resources

NOC parameters:
Number of resources
Types of resources
GPU
SoC
DSP
Memory
RNI CPU Configurable HW
Coprocessors
COP Any combination
Communication capability
RAM DSP

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Network on Chip alternatives

Regions are used to encapsulate

application requirements

Parallel high-performance datapaths

Data compression, encryption,

decompression, decryption

OFDM bit-stream processing

WCDMA bit-stream processing

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Network on Chip alternatives

Memory
management
DATABASE
NOC

Memory area

Applications

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Network on Chip alternatives

Parallel
processing
engine

IO

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NOC design challenges

Physical limits -> Architecture basics ->

GALS -> Communication principles

Application requirements -> Region concepts ->

Heterogenuous resources types -> Multilanguage
and method design flows

Overall complexity -> Architecture reuse ->

Platform type of design flow

Overall complexity -> Basic control

principles -> System services

Manufacturability problems -> Structured approach

NoC SoC

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Figure of Merit for NOC based systems

Scalability
Efficiency
Computation
Energy Utilisation
Storage Fault tolerance
Communication Capacity consumption Result quality (accuracy)
Functionality
Responsiveness

Performance
Materials
Structural
Licensing
Functional
Control System Production

Quality Implementation
Complexity
Variability
Cost
Development
Effort
Time
Flexibility Modifiability
Volume Risk
Applicability Coupling
Lifetime
Configurability Cohesion Manufacturability
Programmability Modularity Usability

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Quality characteristics for NOC

• Communication infrastructure
• delay, bandwidth, power consumption, data transfer reliability
• Goal: reliable application with predictable performance
• Flexibility
• support for variety of products and applications
• support for different traffic types
• safety critical, power efficiency, etc.
• System integration:
• sophisticated means for system analysis
• support for integration of heterogeneous subsystems

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Basic requirements for

NOC design methodology

• Reuse
• of intellectual property blocks
• best performance/energy ratio
• best mapping to application characteristics
• Reuse
• of hardware (and architecture)
• best complexity/cost and performance/cost ratio
• only way to even dream of achieving time-to-profit
requirements
• Reuse
• of design methods and tools
• only way to deal with heterogenuous application set

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NOC Design Methodology

Cores
Communication Memories
structure Accelerators

Optimised Virtual Components

Generic backbone Definition of
NOC platform
“Application area specific IPR”

Processors
and hardware
Algorithms
Applications
Product area specific platform Instantiation Features
of NoC
platform “Product specific IPR”
Code and Optimised Intellectual Property
configuration

NoC system

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Development of NOC based systems

High-perforrmance
communication systems

Baseband platform High-capacity

communication
systems

Personal
assistant
Database platform

Data
BACKBONE collection
systems

Multimedia platform Entertainment

devices
PLATFORMS
SYSTEMS Virtual reality games

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Structural layers of NOC

Product System control, product behaviour

Configuration Network management, allocation, operation modes

Applications Resource management,diagnostics, applications

Functions Execution control, functions

Executables RTOS, code, HW configurations

Hardware units Processors, memories, configurable HW, logic

Resources Resource types, buses, IO

Regions Region types, switches, network interfaces

Communication Channels and protocols

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NOC Layers

• System Product
• Functionality of computation(code, configuration)
Configuration
• Control (OS, NetOS)
• Validation and verification support Applications
Functions
• Platform
• Computation and storage resources Executables
• System services Hardware units
• Application design methods and tools Resources
• Backbone Regions
• Communication resources Communication
• Platform services
• Architecture design methods and tools

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Platform Services

• Purpose to hide physical details from platform

developer
• Communication services
• Switches
NOC Platform Chip
• Channels
• Netwrok interfaces
Platform Services
• Physical and data link layer protocols
• Power and testability services
NOC Backbone
• Power wiring
• Clocking
• Testing structures
• Design services
• Hardware development platform

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System Services
• Purpose to hide implementation details from Applications
application developer
• Execution services
System Services
• Communication, resource
allocation and conversion services
NOC Platform Chip
• Control services
• Power management,
reconfiguration, load migration,
fault detection and recovery, data ASIC
Performance

collection and analysis

• Development support services
SW
• Language interfacing, compilers,
libraries, optimisations, debugging,
testing, validation, etc.
Thickness of service layers
• System services are part of backbone and
platform
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Design Space for NOC

Communication Non-configurable NOC System
channels hardware
Function development

Application Product differentiation

mapping

Architecture
design Platform
Backbone System Services

Operation principles

Product area specialisation

System
does
Resource development
not exist
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NOC domains

• NOC consists of deeply embedded systems (SOCs in a NOC)

• Types of the systems may vary
• we need to support different design methodologies for them
• Constraints for SOCs
• implementable with backbone technology
• must implement platform services
• must implement system services

• NOC domains = hierarchy of domain specific design methodologies

• lower levels are used to implement higher levels
• higher levels set constraints to lower levels

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Hierarchy of NOC domains

VC reuse

Parallel Computer
Computer System
Design Design
Hardware
Design

Embedded
NoC
System
Design
Design
Software
Reuse
Software
Platform
System
Reuse
Design
Software
Design

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Example of NOC domains

NOC design flow

Embedded
system Parallel computer
design flow design flow

General purpose
SW flow
Configurable
HW design Memory
flow subsystem
design flow

Embedded computer
design flow ASIC flow

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NOC phases

• Each design step consists of phases that must be done

• Phases in NOC methodology
• Analysis
• what is the input for decision
• Estimation
• what are possible consequences of the decision
• Decision
• generation of the new model
• Validation
• measurement of the effects of the decision

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Concerns at different layers

Backbone layer Platform layer System layer

Analysis Silicon Application System behavior

characteristics workload

Estimation Yield Capacity Feasibility

Power Efficiency Utilization
Area Performance Performance
Decision Channels Resources Mapping
Switches Services Implementation
Protocols
Validation Performance Performance Functionality
Cost Complexity Performance
Cost Cost

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NOC Platform development problems

• Scaling problem
• How big NOC is needed? What are the application area
requirements?
• Region definition problem
• What kind of regions are needed? What kind of interfaces between
regions? What are the capacity requirements for the regions?
• Resource design problem
• What is needed inside resources? Internal computation type and
internal communication?
• Application mapping flow problem
• What kind of languages, models and tools must be supported? How
to validate and test the final products?

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NOC Application development problems

• Mapping problem
• How to partition applications for NOC resources? How to allocate
functionality effectively? Is the performance adequate? Is the
resource usage in balance?
• Optimisation problem
• How to perform global optimisation of heterogenuous applications?
How to define right optimisation targets? How to utilise
application/resource type specific tools?
• Validation problem
• Are the contraints met? Are the communication bottlenecks or
power consumption hot spots? How to simulate 10000 GIPS
system? How to test all applications?

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Estimation methods for NOC

• Complexity and capacity

• how much is needed
• for sizing and scaling
• Mappability
• what kind of is needed
• for selection
• Workload and performance
• how effective is needed
• for allocation and validation
• Cost and quality
• how expensive and good it is
• for feasibility

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NOC quality validation

Network-level

Workload
modeling Architecture
modeling Decision
support
Simulation

SoC-level

Workload
modeling and
mapping Architecture
modeling

Simulation

Processor-level
Requirements
and
restrictions Software
Architecture
development
modeling

Simulation

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VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Methods & Tools

• Analysis of applications • Estimation of quality characteristics

(characterisation) • global vs. local optimisation of
• analysis of complexity, the system
computation type, • SW architecture vs. HW
communication requirement, architecture
storage, etc. • computation vs. engine
• for scaling, region and resource
type selection, and application
• Development support
mapping
• virtual execution platforms for
• Different abstraction levels:
application developers
workload model, application
model, execution model • integration of existing design
tools for resource level design

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Summary

• Development of NOC systems will be a huge effort

• reuse in all levels is a must
• reuse of architecture, hardware and software in product
• reuse of different languages, methods, tools and practices
during development
• Backbone, platform, system based design methodology apporach
• provides variability and performance
• Encapsulation of different design methodologies
• allows the development of heterogeneous systems
• Analysis, decision, estimation and validation methods are the
cornerstones of NOC development
• complexity, functionality, workload vs. capacity, performance,
efficiency
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Further reading

• Keutzer, K. et al, “System Level Design: Orthogonalization of Concerns and Platform-Based

Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Volume 19, Issue 12, December 2000. pages 1523 –1543
• Sangiovanni-Vincentelli, A. & Martin, G., “Platform-Based Design and Software Design
Methodology for Embedded Systems”, IEEE Design and Test of Computers, November-
December, 2001, pp. 23-33.
• MacMillen, D. et al, “An Industrial View of Electronic Design Automation”, IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, Volume 19, Issue 12,
December 2000. pages 1428–1448
• Edwards, S. et al, “Design of Embedded Systems: Formal Models, Validation and Synthesis”,
Proceedings of IEEE, Vol. 85, No. 3, March 1997, pp. 366-390
• Mai, K. et al, “Smart Memories: a modular reconfigurable architecture”, Proceedings of
International Symposium on Computer Architecture, 2000, pp. 161-171

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Books

• Design methods:
• Chang, H. et al, Surviving the SOC revolution - A Guide to Platform Based
Design, Kluwer, Boston, MA, 1999, 235 p.
• Wolf, W. Computers as Components: Principles of Embedded Computing
System Design, Morgan Kaufmann Publishers, San Francisco, CA, 2001,
662 p.

• Business strategies:
• Porter, M. E. Competitive Strategy, Free Press, NY, 1980, 396 p.
• Wheelwright, S.C. et al, Revolutionizing Product Development, Free Press,
NY, 1992, 364 p.
• Pine II, B.J., Mass Customization - The New Frontier in Business
Competition, Harvard, Business School Press, Boston, MA, 1993, 333 p.

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