1732 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

4, APRIL 2012

Towards a 99% Efficient Three-Phase Buck-Type

PFC Rectifier for 400-V DC Distribution Systems
Andrija Stupar, Student Member, IEEE, Thomas Friedli, Member, IEEE, Johann Miniböck,
and Johann W. Kolar, Fellow, IEEE

Abstract—In telecom applications, the vision for a total power

conversion efficiency from the mains to the output of point-of-load
(PoL) converters of 95% demands optimization of every conver-
sion step, i.e., the power factor correction (PFC) rectifier front-
end should show an outstanding efficiency in the range of 99%.
For recently discussed 400-V dc distribution bus voltages, a buck-
type PFC rectifier is a logical solution. In this paper, an efficiency-
optimized, 98.8% efficient, 5-kW three-phase buck-type PFC recti-
fier with 400-V output is presented. Methods for calculating losses
of all components are described and are used to optimize the con-
verter design for efficiency at full load. Special attention is paid to
semiconductor losses, which are shown to be dominant, with the
parasitic device capacitance losses being a significant component.
The calculation of these parasitic capacitance losses is treated in Fig. 1. Possible 400-V dc distribution architecture [11] for telecom and/or
detail, and the charge-balance approach used is verified. A pro- data center applications. The dc/dc converter shown in light gray can be omitted
if the PFC rectifier is buck type with 400-V output and if no isolation is required.
totype of the proposed rectifier is constructed which verifies the
accuracy of the models used for loss calculation and optimization.
Index Terms—AC-DC power converters, energy efficiency, mod- be increased by 1%–2%. A challenging aspect of the design of
eling, optimization, three-phase electric power. such higher voltage dc distribution architectures is providing
adequate overcurrent protection, as discussed, with a proposed
I. INTRODUCTION solution, in [13].
HREE-PHASE power factor correction (PFC) rectifier A 400-V distribution architecture for telecom or data center
T systems are frequently employed as active front-ends in
utility interfaced systems such as power supplies in telecommu-
applications is shown in Fig. 1. For such a system, a buck-type
PFC rectifier is preferred since boost-type three-phase rectifiers
nications and process technology. Broadly, two approaches to produce an output voltage too high (typically 700–800 V) to
the design of these rectifiers are possible: a boost-type topology directly feed a 400-V dc bus, necessitating a step-down dc/dc
(as considered in [1]–[4]), or a buck-type topology (as con- converter at their output. The usage of a buck-type PFC recti-
sidered in [5]–[9]). Buck-boost-type topologies have also been fier then allows potentially the removal of the dc/dc converter
investigated, as in [10]. Compared to the boost-type topolo- between the PFC and the distribution bus (see Fig. 1, if iso-
gies, the three-phase buck-type rectifiers (3ph-BRs) provide a lation at that point is not required), increasing efficiency and
wide output-voltage control range down to low voltages while reducing costs. In order to achieve an overall efficiency from
maintaining PFC capability at the input, and allow for current the mains to the chip (i.e., output of point-of-load converters)
limitation in the case of an output short circuit [5]. Recent dis- of 90%–95% (whereas today it is typically below 80% [11]),
cussion on power distribution architectures for telecom and data all converter stages in the distribution system must be realized
centres has shown [11], [12] the advantages that facility-wide with highest possible efficiency—starting with 99% at the PFC
400-V dc distribution systems would have over traditional 48– rectifier stage. Currently, commercially available three-phase
54 V dc distribution architectures, especially when dealing with rectifier systems with an isolated dc/dc output converter offer
loads that are tens to hundreds of kilowatts. The main advan- peak efficiencies ranging from 93% [14] for “true” three-phase
tage are lower load currents on the bus, meaning less cable is systems to 97% [15] for systems built from three single-phase
required for transmission, and/or the overall efficiency could rectifier modules. Recent publications similarly report efficien-
cies of 94% for a “true” three-phase PFC rectifier [16], 95% for
an unspecified design [17], and 97% for a modular three-phase
Manuscript received March 4, 2011; revised May 31, 2011; accepted July 30, PFC rectifier [18].
2011. Date of current version February 20, 2012. Recommended for publication A different application of the buck-type PFC rectifier could
by Associate Editor U. K. Madawala. be the charging of the battery of hybrid or electric vehicles
The authors are with the Power Electronic Systems Laboratory, Swiss Fed-
eral Institute of Technology (ETH) Zurich, Zurich 8092, Switzerland (e-mail: (EVs), where 400-V dc is a good approach [19] for the voltage
stupar@lem.ee.ethz.ch; friedli@lem.ee.ethz.ch; miniboeck@mpec.at; kolar@ level of the connection among the battery, motor, and charger.
lem.ee.ethz.ch). Here again the use of a 3ph-BR operating from the 230 V mains
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. would allow direct supply of the dc bus. If in either the telecom
Digital Object Identifier 10.1109/TPEL.2011.2166406 or EV application isolation of the PFC output from the bus is
0885-8993/$26.00 © 2011 IEEE
STUPAR et al.: TOWARDS A 99% EFFICIENT THREE-PHASE BUCK-TYPE PFC RECTIFIER FOR 400-V DC DISTRIBUTION SYSTEMS 1733

Fig. 3. Mains phase voltages and/or input capacitor voltages over one mains
period, showing the division into 12 equal 30◦ -wide sectors for the purpose of
the switching-loss optimized (SLO) modulation scheme (see Fig. 4).

TABLE I
APPLIED DUTY RATIOS BY INPUT VOLTAGE SECTOR
Fig. 2. Power circuit schematic of the 3ph-BR. The full electromagnetic in-
terference (EMI) input filter structure is shown in Fig. 9.

desired due to safety reasons, this can be accomplished with

an isolated 400 V/400 V dc/dc converter (e.g., [20]) with very
narrow voltage control range, which could also be optimized
for 99% efficiency using the approach presented in [21]. Other
applications for the 3ph-BR, where isolation at the output is not
required, include the power supplies of lamps or heaters [22]
and inverters of variable speed ac drives [23].
In this paper, the design of an ultrahigh efficiency, i.e., 98.8% junction Si-MOSFETs and 1200-V silicon carbide (SiC) diodes.
efficient, 5-kW, 400-V output, three-phase buck-type PFC rec- The electromagnetic interference (EMI) filter for the converter
tifier (3ph-BR) is presented, optimized for nominal 230 V ± can be designed using the approach of [27]. Note also that the
10% ac input phase voltage at 50 Hz and peak efficiency at full converter inductance is split evenly (L = L1 = L2 ) between the
load. The topology of this system is presented in Section II. positive and negative output rail in order to provide symmet-
In Section III, the methods for calculating the losses of all the ric attenuation impedances for conducted common-mode (CM)
components, semiconductors and passives, are given along with noise currents.
a detailed loss breakdown for the converter by component type.
Special attention is paid to all types of semiconductor losses A. Modulation Scheme
since many switches must be paralleled in order to achieve a
Modulation schemes for the topology of Fig. 2 have been de-
high efficiency. Section IV presents the prototype with measure-
veloped [24], [25], which guarantee minimum switching losses
ment results. An alternative implementation and conclusions are
as well as minimum input filter capacitor voltage ripple and
discussed in Sections V and VI, respectively.
minimum dc current ripple. This was further improved in [5]
and [26] to eliminate sliding intersections of the input ca-
II. CONVERTER TOPOLOGY pacitor voltages and the resulting distortions. This results in
The converter topology of the 3ph-BR is given in Fig. 2. the switching-loss optimized (SLO) modulation scheme, which
This topology, and its derivation and principle of operation have contains only a short interval td during which switch ON-times
been described previously in detail in [5], and [24]–[26]. It is overlap, where the duty ratios for the three bridge legs are set
designed to provide the necessary 400-V dc output while guaran- according to [5], [25], and [26]
teeing sinusoidal input current and maintaining high efficiency. Vo,ref
The topology presented here is slightly modified. Instead of δi =  |vC F ,i | . (1)
j =R ,S,T vC2 F ,j
insulated gate bipolar transistors (IGBTs) (see Fig. 1 in [26]),
high-voltage MOSFETs are used as switches, due to their better where Vo,ref is the required rectifier output voltage and i =
switching performance and lower forward voltage when paral- R, S, T . To apply (1), the input voltage mains period is divided
leled to increase efficiency. A line-to-line mains voltage ampli- into 12 equal 30◦ -wide sectors, as shown in Fig. 3. The effective
tude of 566 V (for rated mains rms voltage, i.e., 400-V line-to- duty ratio δeff ,i applied to each bridge leg is then calculated ac-
line) allows the realization of the converter with 900-V super- cording to the present sector, as shown in Table I. A switching
1734 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

 
1 3 ˆ
ID F ,rm s = − IN (5)
M π

1 3 ˆ
ID F ,rm s = − IN (6)
M2 Mπ
where IN is the input phase current. The total conduction losses
Fig. 4. SLO modulation scheme. (a) Switching actions during a switching in the converter Pc,S and Pc,D S of the MOSFETs and diodes,
period T S in sector 1, showing overlapping time td and the switching states. respectively, are then
(b) Freewheeling diode voltage v D F during the switching states.
2 RD S,ON
Pc,S = 6IS,rm s (7)
nS
 
2 RD
sequence in sector 1 is depicted in Fig. 4(a). The output volt- Pc,D S = 6 ID S,rm s + ID S,avg V D (8)
age generation can be characterized by the modulation index nD
 
M [26] 2 RD
Pc,D F = ID F ,rm s + ID F ,avg VD (9)
√ nD F
2 Vo 2 Vo
M= = (2) where RD S,ON is the MOSFET ON-resistance, nS the num-
3 V̂N 3 VN ,rm s
ber of transistors paralleled for each switch Si , RD the diode
ranging from 0 to 1, where V̂N is the input phase voltage ampli- ON-resistance, nD the number of devices paralleled for each
tude and Vo the converter output voltage. The resulting wave- diode Di , and VD the diode forward voltage. To reduce con-
form of the voltage across freewheeling diode DF is depicted in duction losses, each device (Si , Di , and DF ) is implemented
Fig. 4(b), showing that the SLO modulation scheme results in with several MOSFETs or diodes in parallel. This, however,
the minimum possible and staircase-shaped voltage steps dur- increases switching losses, especially that portion of switching
ing state transitions for this circuit, therefore, minimizing the losses occurring due to the parasitic output capacitances of the
switching losses. devices. Therefore, the transitions between the switching states
The same duty ratio is applied always to both the switches in in a pulse period (Fig. 4) must be analyzed for all sectors (Fig. 3)
a bridge leg, for example, a single gate signal is connected to to determine where losses occur.
the gate drives of, for instance, SR + and SR − . Accordingly, the Fig. 5 shows the approximate switching behavior of the MOS-
half of the leg and the diode, which conducts, is determined by FETs in the circuit. In each sector, there is always one MOSFET,
the input voltage conditions. Although this slightly decreases which is always switched at zero voltage (e.g., SS − in sector 1
efficiency as the gates of all six MOSFETs are charged and since due to the SLO modulation, the voltage in the S− branch
discharged while only three are conducting current within one is blocked by DS − in sector 1). Fig. 5 refers to the switching
sector and pulse period, it allows the use of only three gating behavior of the remaining two MOSFETs switched in a sector
signals and a simple software implementation of the control (e.g., SR + and ST − in sector 1).
algorithm on a DSP. The switching losses consist of two main portions. The first is
due to the overlapping of voltage and current during MOSFET
transitions, as shown with the overlapping of ION and VD S,ON
III. CONVERTER DESIGN AND LOSS CALCULATIONS
in Fig. 5. The second is due to the charging and discharging of
In order to achieve the highest possible efficiency, losses of the parasitic capacitances of the MOSFETs and diodes.
all components must be calculated as precisely as possible and Consider the transitions in sector 1 (Figs. 4 and Fig. 6). The
minimized during the design stage. The losses can be divided first transition is from state (101) to (110). There, first SS − is
broadly into two categories: losses of the semiconductors and turned on at zero voltage, causing no losses, then ST − is turned
losses of the passive components. off. As seen from Fig. 5, the MOSFET turn-OFF produces neg-
ligible losses since the overlapping of voltage and current is
A. Semiconductor Losses extremely small during this transition. It remains then to an-
alyze losses due to the parasitic capacitances. Refer to Fig. 6
As the topology employs a large number of semiconductor for the equivalent circuits of the two states. The input volt-
devices, their losses are considered first and are the main focus ages are considered constant over one switching period and are
of the efficiency optimization for the converter. The rms and therefore represented as voltage sources VR −S and VS −T . Con-
average values of the series diode current ID S , MOSFET current ducting MOSFETs are represented by their ON-resistances, and
IS , and freewheeling diode current ID F can be calculated by blocking MOSFETs and diodes are represented by their para-
(3)–(6) [5] as follows: sitic output capacitances. Conducting diodes are neglected with
a through connection since their forward voltage is very low
IˆN
ID S,avg = IS,avg = (3) compared to the input and blocking voltages in the circuit. The
π inductor current IL is taken as constant and initially [i.e. in
IˆN state (101)] flowing entirely through the R+ and T − branches.
ID S,rm s = IS,rm s =√ (4)
Mπ The parasitic output capacitance (typically given in datasheets
STUPAR et al.: TOWARDS A 99% EFFICIENT THREE-PHASE BUCK-TYPE PFC RECTIFIER FOR 400-V DC DISTRIBUTION SYSTEMS 1735

IL flows through these capacitors as well. Therefore, for a brief

duration, IL splits between five branches: R+, R−, S−, T −,
and the freewheeling diode branch. This continues until the ca-
pacitors are charged/discharged fully and finally all of IL is
flowing through the S− and R+ branches. The switching in-
terval is very short compared to the pulse period, and therefore,
due to the splitting of IL to four branches, the losses, which oc-
cur during this interval in the ON-resistances of the turned-ON
switches RON,S R − , RON,S R + , RON,S S − [and also the printed
circuit board (PCB) trace resistances, etc.] are lower than al-
ready accounted by the conduction loss calculations, in which
the current flow is always taken to be via two branches only
and is assumed to commutate only from one branch to another
(e.g., in this case immediately from T − to S−). For this reason,
the losses occurring during this transition are not counted in
addition to the already calculated conduction losses.
Consider now the reverse transition, from state (110) to (101),
the equivalent circuit of which is also shown in Fig. 6. In this
transition, ST − is turned on, then SS − is turned off, and DS −
becomes reverse biased. Accordingly, SS − is turned off at zero
voltage and produces no switching losses. However, switching
losses PON occur at the turn-ON of ST − due to the gate–drain
and gate–source capacitance causing a finite transition time ttr
at turn-ON, producing the behavior shown in the ON-transition
in Fig. 5. Whereas the conduction loss is calculated using av-
erage currents assuming an ideal transition, here the MOSFET
conducts a portion of the load current while still carrying a por-
Fig. 5. (a) Simplified equivalent circuit depicting a MOSFET turn-ON transi-
tion. The current IO N commutates from the freewheeling diode branch (dashed tion of the blocking voltage. Therefore, this must be accounted
line) to the MOSFET branch (solid line) as the switch is turned on. Other for and added into the total losses. Taking VD S,ON as the drain–
branches, which are not switching, contain parasitic capacitances C p a r , which source voltage prior to turn-ON and ION as the drain–source
are charged during the transition as the voltage across them changes. V in repre-
sents an input phase-to-phase voltage. (b) MOSFET switching behavior. For the current after turn-ON [Fig. 5(b)], this power loss can then be
turn-ON, also the current IC o ss occurring due to the discharge of the parasitic approximated by the following:
capacitance (here with an assumed constant capacitance at higher voltages) is
shown, which is not measurable as it occurs internally within the MOSFET. VD S,ON ION
There is also a current Ich a rg e through the MOSFET due to the charging of the PON = ttr fsw . (10)
parasitic capacitors of other semiconductors (Fig. 6). For turn-OFF, as C o ss is 2
very high at low voltage, IL charges this parasitic output capacitor, therefore, Not captured by this equation are the losses occurring due to dis-
different from the turn-ON transition, the overlapping of voltage and current is
negligible. (c) Instantaneous power P in st dissipated in the MOSFET during the charging the parasitic output capacitance switched to zero from
transitions, with energy loss components shaded. E O N results from the over- blocking voltage VS −T . This switching also forces the blocking
lapping of IO N and V D S , O N and when multiplied by transition time ttr gives voltage VS −T to occur across DS − and causes a charging of
the power P O N dissipated due to this effect as given by (10). E ch a rg e is only
a portion of the energy losses due to the charging of other parasitic capacitors CO ,D S − . Diode reverse recovery losses are avoided by using
since losses due to this occur also in MOSFETs, which are already conducting SiC diodes. Also note that while DF and DR − do not switch
(i.e., not switching during this transition). For this reason, E ch a rg e and E C o ss in this transition, the voltage across them changes from VR −S
are calculated together using a comprehensive circuit analysis, as in (16).
to VR −T , partially charging their parasitic capacitors. Voltages
across the remaining switches and diodes do not change for this
as Coss ) is voltage dependent and nonlinear, with a relatively transition.
high value at low drain–source voltage VD S and then decreas- This hard-switched transition occurs too quickly to allow en-
ing sharply as VD S increases (Fig. 17). As ST − is turned off, ergy exchange with the converter output, and therefore, CO ,D S −
its capacitance CO ,S T − must be charged as the blocking volt- is charged from source VS −T causing an additional current to
age builds up until diode DS − is forward biased and takes over flow via RON,S T − , causing a loss. Similarly, CO ,D R − and CO ,D F
IL . Therefore, simultaneous to the charging of CO ,S T − , CO ,D S − are charged from sources VR −S and VS −T , which are connected
is discharged. As CO ,S T − is uncharged and large when ST − in series giving one source VR −T . The charging of CO ,D F causes
becomes high ohmic, IL flows via CO ,S T − until it is charged an additional current to flow from VR −T to it via RON,S R +
and ST − displays the behavior of the OFF-transition depicted and RON,S T − , producing losses. For the charging of CO ,D R − ,
in Fig. 5. Similarly, IL flows via CO ,D S − until it is discharged. an additional current flows from VR −T to it via RON,S R − and
Note that also in this transition, the voltage across blocking RON,S T − .
diodes DR − and DF − decreases, meaning CO ,D R − and CO ,D F Solving the circuit for power losses by considering these cur-
must be partially discharged. To accomplish this, a portion of rents would require solving differential equations and knowing
1736 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

Fig. 6. Current paths (a) and equivalent circuits (b) for the switching states within a pulse period in sector 1 (Fig. 4). Current path in each state is shown in black.
Voltages that change as that state is entered are also shown in black. (c) Equivalent circuits of the transitions between the states. For the transitions from state
(101) to (110) and from (110) to (010), the blue dashed line shows the path of the inductor current IL as it splits among the branches of the circuit to charge and
discharge the parasitic capacitors during the transitions. For the transitions from state (010) to (110) and from (110) to (101), the red dotted lines show the paths
of the currents drawn from the sources to charge the capacitors during the transitions. Losses occur along the current paths, mostly in the transistor initiating the
transition.
STUPAR et al.: TOWARDS A 99% EFFICIENT THREE-PHASE BUCK-TYPE PFC RECTIFIER FOR 400-V DC DISTRIBUTION SYSTEMS 1737

quite precisely parasitics such as the PCB resistance. How- in one switching cycle in sector 1 is therefore given by
ever, as in a first step the average power loss over a switching 1 1
period, which is of constant duration for a particular switching ESec1 = CO ,S R + VR −S 2 + CO ,S T − VS −T 2
2 2
frequency, is of interest, it suffices to find the total energy loss
in a transition. The total energy loss due to capacitor charging 1 1
+ CO ,D F VR −S 2 + CO ,D S − VS −T 2
and discharging in an RC circuit does not depend on the value 2 2
of the resistance (for details, see the Appendix). Therefore, the 1 1
+ CO ,D F VS −T 2 + CO ,D R − VS −T 2
energy balance in the circuit is considered. 2 2
For many switching devices, the Coss (v) characteristic be- 1 1
comes flat or nearly flat above a certain VD S . If the blocking + CO ,D S + VR −S 2 + CO ,D T + VR −S 2 . (16)
2 2
voltage is always or most of the time above this value, the output
Over the entire sector, the voltages are not constant but a func-
capacitor of a device can be approximated by a constant value
tion of angle ϕN (Fig. 3). Inserting vR −S (ϕN ) and vS −T (ϕN )
equal to the flat portion of its Coss (v) curve. Hence, a constant
for the appropriate voltage terms in (16) and averaging, i.e., in-
capacitance is taken for the following analysis. In (11) and (12),
tegrating the total losses over sector 1, i.e., over 30◦ , gives the
the energy present in the circuit before and after the transition
total power loss due to the parasitic device output capacitances
from (110) to (101) is given. There, only those capacitors, which
since all 12 sectors are symmetric in terms of switching behavior
change their voltage during the transition, are considered. The
and voltages. This total power loss PC o,tot is then given by
energy exchanged with the sources is determined considering
the changes of the charging levels of the parasitic capacitors, as   √ 
6 2 1 3 14π − 9 3
shown in (13) and (14). The charge flow is considered positive if PC o,tot ≈ V̂N nS CO ,S + nD CO ,D fsw .
π 2 2 32
it flows away from the source positive terminal. The total energy
(17)
loss ΔE(110)−(101) occurring in this transition is then calculated
Note that this is an approximation since, as mentioned previ-
by (15).
ously, the parasitic capacitances are approximated by constant
capacitors for this analysis. For some semiconductor devices,
1 1
E(110) = CO ,D R − VR −S 2 + CO ,S T − VS −T 2 the Coss (v) characteristic is such that it cannot be well approxi-
2 2
mated by a constant value (Fig. 17). In this case, the energy and
1 charge in the capacitors must be determined by integrating the
+ CO ,D F VR −S 2 (11)
2 nonlinear capacitance. This is shown in detail in the Appendix.
1 1 Taking into account as above the varying blocking voltages
E(101) = CO ,D R − VR −T 2 + CO ,D S − VS −T 2
2 2 across MOSFETs SR + and ST − in sector 1, (10) must also be
1 integrated to calculate the total MOSFET turn-ON power losses
+ CO ,D F VR −T 2 (12) due to the overlapping of voltage and current. Knowing the
2
voltages from the previous analysis and that in this case ION =
ΔEV S −T = ΔQO ,D S − VS −T = CO ,D S − VS −T 2 (13) IL /nS , the total turn-ON losses due to overlapping of voltage
ΔEV R −T = ΔQO ,D R − VR −T + ΔQO ,D F VR −T and current PON,tot in the system can be calculated as follows:
√
= CO ,D R − (VR −T − VR −S )VR −T 6 3
PON,tot = V̂N IL ttr fsw (18)
+ CO ,D F (VR −T − VR −S )VR −T (14) π 4
where IL is the dc inductor (output) current.
ΔE(110)−(101) = E(110) + ΔEV S −T + ΔEV R −T − E(101)
1 1 B. Optimization of the Number of Paralleled Semiconductors
= CO ,S T − VS −T 2 + CO ,D S − VS −T 2
2 2 With these loss components defined, it is possible to vary nD
1 and nS to find an optimum number of devices to place in parallel
+ CO ,D F (VR −T − VR −S )2
2 for each switch and diode in Fig. 2. Superjunction power MOS-
1 FETs with 900-V blocking capability (IPW90R120C3 from In-
+ CO ,D R − (VR −T − VR −S )2 . (15) fineon) were chosen for the implementation, with an average
2
ttr = 20 ns (estimated from previous measurements of the switch
The remaining transitions can be similarly analyzed: no behavior) and a Coss (v) characteristic requiring the use of in-
switching losses are counted at the transition from (110) to tegration approach shown in the Appendix to calculate losses.
(010), analogously to the transition from (101) to (110), while The diodes chosen were SiC 1200 V C2D10120A from Cree.
losses occur in the transition from (010) to (110) due to the dis- A switching frequency of fsw = 18 kHz at the edge of au-
charging of CO ,S R + (turn-ON of SR + ), charging of CO ,D F (due dible range was chosen to keep switching losses low. Fig. 7
to building up the blocking voltage VR −S across DF ), charg- shows the resulting total losses for the MOSFETs and series
ing of CO ,D S + (blocking voltage changes from approximately diodes for different numbers of devices used in parallel for each
0 to VR −S ), and partial charging of CO ,D T + (blocking voltage switch and diode. The minimum losses occur with nS = 8 and
changes from VS −T to VR −T ). The total capacitive energy loss nD = 12; however, as can be seen, the curves are nearly flat
1738 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

The inductor dc resistance RL ,dc is therefore

ρN lT
RL ,dc = (19)
Aw
where N is the number of turns, lT the average length of a turn,
Aw the wire cross-sectional area, and ρ its resistivity. The core
losses can be calculated using the modified Steinmetz equa-
tion [28]. The losses Pcore for the triangular current (switching
ripple) present in L1 and L2 are
 α −1
2
Pcore = kfsw · 4fsw B̂ β Vcore (20)
Fig. 7. Total losses of switches S i and series diodes D i depending on the
π2
number of devices in parallel to construct each. For example, n S = 7, n D = 4, where k, α, and β are Steinmetz parameters, given or extractable
total losses are 11 W + 26.8 W = 37.8 W. Marked on the curves are the optimal
n S and n D according to the calculations, and the selected n S and n D for the from core material datasheets, Vcore the total core volume, and
prototype. B̂ the peak magnetic flux density, which can be calculated by
L(0.5ΔIL )
B̂ = (21)
N Ae
where IL is the average inductor current, ΔIL the inductor
current ripple, and Ae the inductor core cross-sectional area. For
the HF losses, the rectangular wire used can be approximated
closely as a conductor with a square cross section, and the ac
winding resistance RL ,ac,n due to skin and proximity effect
resulting from the nth harmonic of the inductor current ripple
can be calculated using the Ferreira method [29]
ξ(η) sinh ξ(η) + sin ξ(η)
RL ,ac,n = RL ,dc
2 cosh ξ(η) − cos ξ(η)
Fig. 8. Breakdown of total semiconductor losses by component and by loss 
m tot
RL ,dc ξ(η) 2 sinh ξ(η) − sin ξ(η)
type. Turn-ON losses shown in the figure are the losses resulting from the + η (2m − 1)
overlapping of voltage and current as calculated by (18). Capacitive losses are m =1
mtot 2 cosh ξ(η) + cos ξ(η)
those occurring due to the charging and discharging of parasitic capacitances.
(22)
for an inductor with mtot layers of windings with porosity factor
for 6 ≤ nS ≤ 11 and 7 ≤ nD ≤ 15. The losses saved by going η and skin depth related term ξ(η)
from 6 MOSFETs in parallel to 8 are not even 1 W. Setting nD = aNm
12 would have resulted in an overly expensive prototype, and η= (23)
b
moreover, the difference between nD = 6 and nD = 12 is less
than 2 W, which is less than the measuring error of the equip- ξ(η) = Aw πμ0 σnfsw η (24)
ment that was available for measuring efficiency. Therefore, for where a is the side length of the square conductor, b the width of
the implementation, nS = nD = 6 was set in order to save costs. a layer, Nm the number of turns in a layer, and σ the conductivity
Fig. 8 gives a breakdown of the total semiconductor losses in of the wire. Taking into account inductor current harmonics [21],
the converter. Out of a total 39 W of losses, diode conduction the total losses PL ,tot for a dc choke with triangular current then
losses are dominant with 21.2 W. Also note that the capacitive are
losses of the MOSFETs alone are larger than half the conduction 
ntot
2 ΔIL ,n 2
losses and that for the MOSFETs the switching losses in total PL ,tot = IL RL ,D C + RL ,ac,n + Pcore (25)
are almost equal to the conduction losses. This underlines the n =1
3
need to consider the switching, and in particular, the capacitive where ΔIL ,n is the amplitude of the nth harmonic. Knowing
losses, carefully. that at full load IL = 12.5 A and selecting an inductor current
peak-to-peak ripple of 25%, the inductance value L1 = L2 =
650 μH is obtained (for details see [5]). Using Ferroxcube E64
C. Losses of the Output Inductors 3C91 cores with N = 18 (Nm = 2, mtot = 9), copper wire with
Inductor losses can be divided into three groups: losses due Aw = 4.1 mm × 2.1 mm = 8.6 mm2 and assuming an inductor
to dc winding resistance, core losses, and high-frequency (HF) temperature of 50 ◦ C, the total dc losses for the chokes L1 and
losses due to skin and proximity effect. The configuration chosen L2 given by (19) are 5.7 W, and the total HF losses given by
for output inductors L = L1 = L2 consists of three pairs of (25) are approximately 0.9 W. Core losses calculated by (20) do
ferrite E-cores wound with solid rectangular wire [Fig. 11(b)]. not take into account dc magnetic bias, which has been shown
STUPAR et al.: TOWARDS A 99% EFFICIENT THREE-PHASE BUCK-TYPE PFC RECTIFIER FOR 400-V DC DISTRIBUTION SYSTEMS 1739

in [30] to have a nonnegligible influence. Therefore, for higher

accuracy, the core losses were measured and confirmed to be
approximately 0.5 W.

D. Losses of Output Capacitor

Losses in the capacitors are caused by their equivalent series
resistance (ESR) and by leakage current. The ESR value is given
in capacitor datasheets or can be calculated using the loss factor
tan(δ) also given in datasheets as [21] Fig. 9. EMI filtering concept and topology of the input filter.

tan(δ)
ESR = (26)
2πfsw C
where C is the capacitance of the capacitor in question. The
leakage current Ileak is determined using characteristic equa-
tions given in the capacitor datasheet. The total power losses
PC of a capacitor can then be calculated by
PC = IC2 ,rm s ESR + Ileak VC (27)
where IC ,rm s is the rms current through the capacitor and VC
the average capacitor voltage. The output capacitor is selected
to be C1 = 376 μF to keep output voltage ripple below 100 mV Fig. 10. Summary of loss components.
(for details see [5]) and implemented with 8 parallel 47 μF KXJ
electrolytic capacitors from Nippon-Chemicon. As VC = VO =
400 V, losses due to leakage current are about 1.3 W (Ileak = The FR-4 thickness is approximately 0.5 m, and considering a
3.3 mA). With the paralleling of these low-ESR capacitors and maximum trace area of 375 mm2 and taking a relative permit-
with IC ,rm s = 0.9 A, resistive losses of the output capacitors tivity of 4.7, this adds another 0.5 W of losses. As will be seen
were found to be negligible. in Section IV, no heat sink or fan is needed to cool the system,
and therefore any losses due to a cooling fan are avoided.
E. Other Losses
F. Total Losses
In order to make the rectifier prototype compliant to existing
Total losses calculated for the converter were 53.7 W, giv-
EMI norms, the EMI input filter depicted in Fig. 9 is used. From
ing an efficiency of 98.94%. A breakdown of the total losses
circuit simulations of the rectifier system, the expected differen-
is depicted in Fig. 10. As can be seen, semiconductor losses
tial mode (DM) and CM noise are calculated, as well as the nec-
dominate and account for over 70% of the total. Clearly, for
essary attenuation based on the limits for Comité International
the 3ph-BR topology examined in this paper, semiconductor
Spécial des Perturbations Radioélectriques (CISPR) Class B.
technology is the most significant barrier to achieving 99% effi-
Following the approach of [27], the EMI filter is designed with
ciency. Therefore, not the optimization of inductors [21] and/or
Creturn = 200 nF, CF ,i = 13.2 μF, CC M ,i = CD M 1,i = 4.7 nF,
power passives, but the improvement of the properties of the
CD M 2,i = 2 μF, LF ,i = 50 μH, LC M 1 = 900 μH, and LC M 2 =
semiconductors, either through decreased RD S,ON or Coss , i.e.,
800 μH. EPCOS film capacitors having a negligible leakage
an improved Figure of Merit—would be the only practical way
current are used producing 0.7 W of losses due to ESR. Each
to further significantly decrease losses.
LF ,i is implemented with a pair of EPCOS ETD49 cores with 10
turns of solid copper wire, a Vacuumschmelze VAC6123X240
IV. EXPERIMENTAL RESULTS
CM choke is used for LC M 1 , and LC M 2 is implemented with
three 8-turn windings around a Vacuumschmelze 500F W423 A prototype of the proposed 3ph-BR was constructed with
core. This gives in total 2 W of losses due to the dc resistance, the EMI filter implemented on a separate board. The prototype
with HF and core losses in the milliwatt range. is shown in Fig. 11. In total, 36 CoolMOS and 42 SiC diodes
An auxiliary power supply, a flyback converter, is used to were mounted concentric on the top of the converter, minimizing
power the TI TMS320F2808 DSP system used for the control commutation inductances. The dc choke and output capacitors
and the gate drives. This supply was also analyzed and found to were mounted on the bottom of the converter. Infrared camera
operate at an efficiency of 77.6% consuming a total of 3.1 W. measurements after 30 min of operation at full load showed
Finally, the FR-4 PCB material sandwiched between copper a maximum temperature of 71.7 ◦ C, which confirms that the
layers, i.e., the relatively wide tracks for the positive and nega- operation without heat sink was unproblematic and tempera-
tive rail of the converter, is considered, which creates essentially ture was uniformly distributed across the semiconductors. The
a plate capacitor in parallel to DF , charged and discharged in inductors reached 51.5 ◦ C. Fig. 12 shows the achieved sinu-
the same manner as the capacitance of DF . The PCB, being soidal input currents. EMI measurements were also performed
multilayered, basically creates several plate capacitors in series. (Fig. 13) confirming that the converter fulfills CISPR 22 Class B.
1740 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

Fig. 14. Calculated efficiencies at different load levels for the 3ph-BR at 230-V
AC input compared to calorimetric measurements of efficiency at different load
points and the calculated efficiency for a 3ph-BR where the CoolMOS switches
are replaced by SiC JFETs. Calculated efficiencies for the 10% load point are
not shown as at this load the converter operates in discontinuous conduction
mode, which is not modeled in this paper.

A. Efficiency Measurements
Fig. 11. Constructed prototype of the converter (right) and EMI filter on sep- Results of calorimetric measurements of the converter proto-
arate board (left). (a) Top view and (b) bottom view. The power stage measures type efficiency at different load points with a precision calorime-
283 × 155 × 31 mm3 and the EMI filter board 135 × 155 × 42 mm3 resulting ter with an accuracy of ±2 W [31] are given in Fig. 14. As can
in a total power density of 2.2 kW/dm3 .
be seen, with 230-V nominal input voltage and at full load, an
efficiency of 98.8% was measured, giving good agreement with
the calculations in Section III. The difference between the calcu-
lation according to the models in Section III and the calorimetric
efficiency measurement (which gives 61.6 W of losses at full
load) is about 8 W or 15%. Considering the full output power of
5000 W, this is an error of 0.16% of efficiency. Possible sources
of error are the polynomial fits used for the parasitic capacitance
characteristics, losses in the PCB tracks (not considered in this
paper), and tolerances of the components, i.e., variation of the
actual component characteristics from given datasheet values.
It should be noted that down to 10% rated load and across
the rated input voltage range, a high efficiency of over 97%
is always maintained. The lower efficiency at low loads can
be partly explained by the significant voltage-dependent loss
Fig. 12. Measurement of the input currents iN , R , iN , S , and iN , T of the components, which are constant over the load range, i.e., the
rectifier for rated load (P O = 5 kW) and for input voltage V N , rm s = 230 V.
Scale: 5 A/div. Timescale: 2 ms/div. losses due to the parasitic capacitors.

V. ALTERNATIVE IMPLEMENTATIONS
In order to achieve a higher blocking voltage of the switches,
one possibility is to replace the MOSFETs in the converter with
1200-V IGBTs. A preliminary investigation was carried out
where the losses of the CoolMOS calculated in Section III were
replaced by the losses that 1200 V Infineon IGW40T120 IGBTs,
available in the same package as the MOSFETs, would have
under the same operating conditions. Conduction and switch-
ing losses of the IGBTs were estimated based on the output
characteristic and switching energy curves given in the device
Fig. 13. EMI measurements of the converter using an average detector show- datasheet. The optimum design yielded only one device for each
ing the CISPR Class B standard limit (red) and conducted EMI (blue).
switch, with total switch losses of approximately 80 W, giving a
STUPAR et al.: TOWARDS A 99% EFFICIENT THREE-PHASE BUCK-TYPE PFC RECTIFIER FOR 400-V DC DISTRIBUTION SYSTEMS 1741

total of approximately 122 W of losses for the entire converter,

i.e., an efficiency of only 97.6% at full load. The optimized
IGBT-based converter suffers from higher switching losses than
the MOSFET-based converter due to much higher switching en-
ergies of the IGBTs compared to the Superjunction MOSFETs
and also from higher conduction losses, as the ON-state voltage
drop of the IGBTs does not scale down linearly as extra devices
Fig. 15. Equivalent circuit for the charging of the parasitic capacitor of D S −
are added in parallel, as is the case with the MOSFETs. There- to voltage level V S −T from zero.
fore, an IGBT-based system appears not to be a viable solution
for a converter targeting 99% efficiency.
Another possibility, which achieves a higher blocking voltage
of the switches while maintaining high efficiency at full load, is
to replace the MOSFETs with 1200-V SiC JFETs from SiCED
(RD S,ON = 80 mΩ at a junction temperature of 25 ◦ C). Again,
the losses of the MOSFETs calculated in Section III were re-
placed by the losses that SiC JFETs would have under the same
operating conditions. Four JFETs, the optimal configuration for
efficiency, were used in parallel for each switch, with the rest Fig. 16. Equivalent circuit for the charging of the parasitic capacitor of D F
to voltage level V R −T from an initial voltage V R −S .
of the circuit unchanged, i.e., nD = 6, and the losses were cal-
culated based on a characterization from earlier experimental
conduction and switching loss measurements. The results are (31) the energy loss due to charging
shown in Fig. 14. According to calculations an efficiency of
98.9% would be achieved at full load and fsw = 18 kHz making E(110),D S − = 0 (28)
an all SiC 3ph-BR a viable design. 1
E(101),D S − = CO ,D S − VS −T 2 (29)
2
ΔEV S −T = ΔQO ,D S − VS −T = CO ,D S − VS −T 2 (30)
VI. CONCLUSION
ΔE(110)−(101),D S − = E(110),D S − + ΔEV S −T − E(101),D S −
A three-phase buck-type PFC rectifier was presented with
measured 98.8% efficiency suitable for supplying 400-V dc dis- 1
= CO ,D S − VS −T 2 − CO ,D S − VS −T 2
tribution systems. Models for calculating losses of all compo- 2
nents were discussed and verified by experimental measurement 1
of the converter’s efficiency. The dominance of semiconduc- = CO ,D S − VS −T 2 (31)
2
tor losses indicates that the achieved efficiency is a limit for
the presented topology obtainable with currently commercially The energy loss in this circuit occurs in the resistor RON,S T − .
available power semiconductors, and that further improvements Note that (31) holds true whether RON,S T − is constant or
in semiconductor components are the key to reaching the 99% whether it is varying with time (e.g., as the ON-resistance of
efficiency target. If a higher blocking voltage than is available a MOSFET varies during its transition from its OFF-state to
with MOSFETs is to be targeted, IGBTs are not a suitable re- its ON-state). Therefore, the above analysis is valid for any
placement as they suffer from significantly higher switching RON,S T − (t). The characteristics of RON,S T − , e.g., its actual
and conduction losses. On the other hand, replacing MOSFETs change from a high-ohmic OFF-state value to the ON-state does
with higher blocking voltage SiC JFETs results in the same not influence the energy losses occurring due to charging of the
calculated efficiency of 98.9%. capacitor.
The same analysis can be applied to a case where the capacitor
is charged or discharged from one voltage level to another.
Consider for example the change of voltage of CO ,D F from
APPENDIX VR −S to VR −T during the transition from state (110) to (101)
CALCULATING ENERGY LOSSES IN RC CIRCUITS in sector 1 (Fig. 16). The energy in CO ,D F before the transition
is given in (32), the energy after in (33), the energy exchanged
Here, the calculation of losses due to the charging and dis-
with the source in (34), and the energy loss in (35)
charging of parasitic capacitors (Section III) are shown in more
detail. Consider first the case of a constant capacitor, e.g., 1
E(110),D F = CO ,D F VR −S 2 (32)
CO ,D S − , charged from zero to a voltage VS −T from a volt- 2
age source, as occurring during the transition from state (110) 1
to (101) in sector 1, (Fig. 15). Considering the charge delivered E(101),D F = CO ,D F VR −T 2 (33)
2
to the capacitor, the loss ΔE(110)−(101),D S − is calculated, with
ΔEV S −T = ΔQO ,D F VR −T
(28) giving the energy in the capacitor before the transition, (29)
the energy after, (30) the energy exchanged with the source, and = CO ,D F (VR −T − VR −S ) VS −T (34)
1742 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

defined as follows:
dqoss
Coss (v) = . (36)
dv
In this case, the energy EC o (V ) stored in the output capacitor
of a device at a voltage V must be calculated by [32]
Q V
EC o (V ) = vdqoss = vCoss (v)dv. (37)
0 0

Fig. 17. Possible shapes of C o ss curves of semiconductor devices. (a) A In some cases, an Eoss (v) curve is already given in the
case where the capacitance becomes constant or nearly constant after a certain datasheet. The charge QC o (V ) stored in the output capacitor
voltage. In this case, for example, if the blocking voltage in the circuit is mainly
above 200 V (marked by the dashed line), the C o ss value may be approximated of a device at a voltage V is then determined by
by the flat portion of the curve and the equations [e.g., (17)] derived from the
Q V
constant capacitor model may be used to calculate losses. (b) A case where
C o ss cannot be approximated by a constant and the equations where the C o ss QC o (V ) = dqoss = Coss (v)dv. (38)
curve is integrated [e.g., (43)] must be used to calculate losses. For both cases, 0 0
the resulting energy (E o ss ) curve is shown by the dotted lines. For the previously considered case, where the capacitor is
charged from zero, this then allows (31) to be rewritten as
follows:
ΔE(110)−(101),D S − = E110,D S − + ΔEV S −T − E110,D S −
= QO ,D S − (VS −T )VS −T − EO ,D S − (VS −T )
(39)
where the charge and energy terms are calculated using (38)
and (37), respectively. To then get the average power loss in a
switching period due to this energy loss, the following integra-
tion is performed taking into account the dependence of VS −T
on angle ϕN
Fig. 18. Capacitor charge Q resulting from a capacitor voltage V for (a) a
constant capacitor and (b) a nonlinear capacitor with varying voltage-dependent
 π /6
6
capacitance. Shown also is the resulting loss E lo ss, R (area shaded in light gray) PC o,D S − = fsw nD vS −T (ϕN )QC o,D (vS −T (ϕN ))dϕN
in the circuit resistance as the capacitor is charged from zero to a voltage V C and π 0
charge Q C by a voltage source, as well as the resulting energy E C (area shaded
π /6 
in dark gray) stored in the capacitor at voltage V C . With the linear constant
capacitor, when charging from zero, the energy loss due to charging is equal − EC o,D (vS −T (ϕN ))dϕN . (40)
to the energy stored in the capacitor after the charging is completed, as shown, 0
e.g., by (31). For the nonlinear capacitor, this is not the case and the energy loss Similarly, for the considered case, where a capacitor is
must be determined via integration.
charged from one voltage level to another, (35) can be rewritten
as follows:
ΔE(110)−(101),D F = E110,D F + ΔEV R −T − E101,D F
ΔE(110)−(101),D F = E110,D F + ΔEV R −T − E110,D F
1
= CO ,D F VR −S 2 = EO ,D F (VR −S )
2
+ CO ,D F (VR −T − VR −S ) VR −T + (QO ,D F (VR −T )−QO ,D F (VR −S))VR −T
1
− CO ,D F VR −T 2 − EO ,D F (VR −T ) (41)
2
and then integrated as above to obtain the power loss.
1
= CO ,D F (VR −T − VR −S )2 . (35)  π /6
2 6
PC o,D F = fsw nD EC o,D (vR −S (ϕN ))dϕN
Again, the result is valid regardless of the varying resistance in π 0
the circuit. π /6
For some semiconductors, the voltage-dependent parasitic + vR −T (ϕN )QC o,D (vR −T (ϕN ))dϕN
output capacitor cannot be effectively approximated with a con- 0
stant value (Fig. 17). For nonlinear capacitors, the energy loss π /6
due to charging cannot be calculated as shown previously, as − vR −T (ϕN )QC o,D (vR −S (ϕN ))dϕN
0
it depends on the nonlinear capacitance characteristic, which 
π /6
varies with voltage (Fig. 18). In these cases, the charge and
− EC o,D (vR −T (ϕN ))dϕN . (42)
the energy must be determined by integrating the Coss (v) curve 0
given in device datasheets. Coss (v) is a differential capacitance
STUPAR et al.: TOWARDS A 99% EFFICIENT THREE-PHASE BUCK-TYPE PFC RECTIFIER FOR 400-V DC DISTRIBUTION SYSTEMS 1743

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1744 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

Andrija Stupar (S’02) was born in Belgrade, Serbia, Johann W. Kolar (F’10) received the Ph.D. degree
in 1984. He received the Bachelor and the Master of (summa cum laude/promotio sub auspiciis praesiden-
Applied Science degrees from the Faculty of Applied tis rei publicae) from the University of Technology
Science and Engineering of the University of Toronto, Vienna, Austria.
Toronto, Canada. He is currently working toward the Since 1984, he has been an independent inter-
Ph.D. degree at the Power Electronic Systems Labo- national consultant in close collaboration with the
ratory, Swiss Federal Institute of Technology (ETH) University of Technology Vienna, in the fields of
Zürich, Zurich, Switzerland. His Ph.D. thesis focuses power electronics, industrial electronics, and high-
on modeling, simulation, and optimization of power performance drives. He has proposed numerous novel
converters. PWM converter topologies, and modulation and con-
While at the University of Toronto, he worked on trol concepts, including the VIENNA rectifier and
the design and implementation of digital controllers for low-power switch-mode the three-phase ac–ac sparse matrix converter. He was appointed Professor
power supplies. and Head of the Power Electronic Systems Laboratory, Swiss Federal Insti-
tute of Technology (ETH) Zurich on February 1, 2001. He initiated and/or
is the founder/cofounder of 4 spin-off companies targeting ultrahigh speed
Thomas Friedli (M’09) received the M.Sc. degree drives, multidomain/level simulation, ultracompact/efficient converter systems,
in electrical engineering and information technol- and pulsed power/electronic energy processing. He is the author or coauthor of
ogy (with distinction) and the Ph.D. degree from the more than 350 scientific papers in international journals and conference pro-
Swiss Federal Institute of Technology (ETH) Zurich, ceedings and has filed 75 patents. His current research interests include ac–ac
Zurich, Switzerland, in 2005 and 2010, respectively. and ac–dc converter topologies with low effects on the mains, for example,
His Ph.D. thesis focused on the further development for power supply of data centers, more electric aircraft and distributed renew-
of current source and matrix converter topologies able energy systems, the realization of ultracompact and ultraefficient converter
in collaboration with industry using silicon carbide modules employing the latest power semiconductor technology (silicon car-
JFETs and diodes and a comparative evaluation of bide), novel concepts for cooling and electromagnetic interference filtering,
three-phase ac–ac converter systems. He is contin- multidomain/multiscale modeling/simulation and multiobjective optimization,
uing research into these areas as a post-doctoral re- physical-model-based lifetime prediction, pulsed power, bearingless motors,
searcher at the Power Electronic Systems Laboratory at ETH Zurich. From 2003 and power microelectromechanical systems.
to 2004, he was a trainee for Power-One in the R&D center for telecom power Dr. Kolar received the Best Transactions Paper Award of the IEEE Industrial
supplies. Electronics Society in 2005, the Best Paper Award of the International Con-
Dr. Friedli received the 1st Prize Paper Award of the IEEE Industry Appli- ference on Power Electronics in 2007, the 1st Prize Paper Award of the IEEE
cations Society (IAS) Industrial Power Converter Committee in 2008 and the Industry Applications Society Industrial Power Converter Committee in 2008,
IEEE IAS Transactions Prize Paper Award in 2009. and the Annual Conference of the IEEE Industrial Electronics Society Best Paper
Award of the Industrial Electronics Society Power Electronics Technical Com-
mittee in 2009. He also received an Erskine Fellowship from the University of
Johann Miniböck was born in Horn, Austria, in Canterbury, Christchurch, New Zealand, in 2003. In 2006, the European Power
1973. He studied Industrial Electronics at the Uni- Supplies Manufacturers Association named the Power Electronics Systems Lab-
versity of Technology Vienna, Austria, and received oratory of the Swiss Federal Institute of Technology (ETH) Zurich the leading
the Dipl.-Ing. (M.Sc.) and the Ph.D. degrees from academic research institution in Power Electronics in Europe. Dr. Kolar is a
the Swiss Federal Institute of Technology (ETH) Member of the Institute of Electrical Engineers of Japan (IEEJ) and of Interna-
Zurich, Zurich, Switzerland, in 1998 and 2008, tional Steering Committees and Technical Program Committees of numerous
respectively. international conferences in the field (for example, he is the Director of the
He is currently engaged in teaching electrical ma- Power Quality Branch of the International Conference on Power Conversion
chines, drives, and power electronics at the Power and Intelligent Motion). He is the founding Chairman of the IEEE Power Elec-
Electronic Systems Laboratory, (ETH) Zurich. He is tronics Society Austria and Switzerland Chapter and Chairman of the Education
also the owner of a company on consultancy in power Chapter of the European Power Electronics and Drives Association. From 1997
electronics. He has performed various research projects in the field of single- and through 2000, he was an Associate Editor of the IEEE TRANSACTIONS ON IN-
three-phase power factor correction, switch-mode power supplies for various DUSTRIAL ELECTRONICS. Since 2001, he has been an Associate Editor of the
applications, and has developed laboratory setups for teaching power electronics IEEE TRANSACTIONS ON POWER ELECTRONICS. Since 2002, he has also been
and drives. He is the author or coauthor of 36 scientific papers and patents. His an Associate Editor of the Journal of Power Electronics of the Korean Institute
current research interests include the realization of single- and three-phase elec- of Power Electronics and a member of the Editorial Advisory Board of the IEEJ
tric vehicle chargers as well as ultra efficient power factor correction circuits. Transactions on Electrical and Electronic Engineering.