2020 International Conference on Computer Communication and Informatics (ICCCI -2020), Jan.

22 – 24, 2020, Coimbatore, INDIA

Metastability Influenced PUF for Cryptographic Key

Generation: A FPGA Approach

Poorna Sai Meka1, Sivaraman R2 Amirtharajan Rengarajan3, Sundararaman

Student1, Research Scholar2 Rajagopalan3
School of EEE, SASTRA Deemed to be University Faculty3, School of EEE
Tamilnadu, India - 13401 SASTRA Deemed to be University
Tamilnadu, India - 613401
raman@ece.sastra.edu

Abstract— This paper presents a true random key generation machine cycle, on – chip and other off – chip capabilities [3].
using Physically Unclonable Function (PUF). PUFs are In FPGA, clock jitters and metastability are the available
considered as “physical fingerprint” of anys Integrated Circuit sources for generating true randomness. One such approach is
(IC) through which they can be differentiated from others. They proposed by Martin and Sunar, where Ring Oscillators (ROs)
offer a plenty of applications namely Hardware authentication,
have been preferred as entropy source through which jitter
Identification, Anti – counterfeiting to safeguard the hardware as
well as the sensitive data being processed or stored in the clocks have been generated. The design has 110 rings of 3
hardware. A deeper insight is required into the design and inverters in each ring. XOR operation has been adopted
implementation of hardware efficient FPGA based PUF with a between the jitter clocks to extract the true randomness. In this
focus on low area overhead. In this work, PUF architecture for work, resilient function has been chosen as post processor
key generation on Intel Cyclone II FPGA using Verilog HDL and through which the TRNG has been furnished [4]. Ning et al.,
Quartus II 13.0 Electronic Design Automation (EDA) tool has have suggested a non – identical structure of RO based TRNG
been proposed. SR latch based metastability is the main concern design to achieve more true randomness. To enhance the
of PUF generation. Metastability on SR latch act as entropy statistical properties of TRNG, Von Neumann Corrector
source to generate true randomness. This design requires only
(VNC) post processing has been used. The TRNG has been
four SR latches to produce adequate true randomness. Further,
true randomness is extracted through harvesting mechanism evaluated through DIEHARD test suite [5].
where Meta beat counting and De - synchronization techniques Varchola and Drutarovsky have focused on generating
have been investigated with respect to equidistribution property. high-entropy TRNG by combining metastability with clock
Post processing unit has been incorporated to enhance the jitters through Transition Effect Ring Oscillator (TERO)
statistical properties of PUF. This design consumes 881 logic structure on FPGA. This approach requires a high knowledge
elements and dissipates 4.41 mW of power for implementing the on place and route strategies to yield better results [6].
PUF architecture on Cyclone II EP2C3F484C7 FPGA. Entropy, Wieczorek experimented dual metastability on flip-flops to
restart experiment and NIST SP 800 – 22 tests have been generate true randomness. Through this technique time
performed to evidence the true randomness.
difference with the response by a pair of metastability flip-flop
Keywords: Authentication, Digital fingerprint, FPGA and PUF is used for TRNG and the response has been evaluated with the
standard statistical analyses [7]. Justin et al., worked on LUT-
I. INTRODUCTION SR RNG which gives more irregularity, quality and least asset
PUFs are the predominant source of key generation which usage than the existing LUT-SR generator. In order to improve
produces random key on dynamic fashion. It takes the physical the arbitrariness, quadratic buildup strategy is utilized and
existence of uniqueness of each IC and converts the attributes achieved adequate true randomness with minimum resource
to random bits result in keys [1]. It has two major utilization [8]. Hisashi and Shuichi, proposed a TRNG using
functionalities such as cryptographic key generation and device clock as influencing agent to induce metastability in SR latches
authentication. The PUF responses are irreducible in terms of which have then XORed to extract the true randomness and the
key generation where true randomness has been exploited from TRNG has been verified through NIST SP 800 – 22 tests [9].
a device to generate random keys. True Random Number Bilal et al., suggested a TRNG architecture using PUF where
Generators (TRNGs) are a variant of PUFs which generate true two set of 256 SR latches have been used as source of
random numbers [2]. randomness. The output is extracted from preselected latches
Reconfigurable hardware such as Field Programmable using multiplexers and it can be observed that the logic
Gate Array (FPGA) has been chosen as a fruitful platform for consumption of this mechanism is more [10].
exploiting the true randomness due to its inherent In this proposed work, SR latch has been chosen as source
characteristics such as reconfigurability, reusability, easy of true randomness due to its simplicity and ease of
prototyping, algorithm agility, faster time to market, no fixed implementation. In this work, metastability from SR latches

978-1-5386-8260-9/19/$31.00 ©2020 IEEE

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 2020 International Conference on Computer Communication and Informatics (ICCCI -2020), Jan. 22 – 24, 2020, Coimbatore, INDIA

has been extracted using harvesting mechanism and post random sequences. Further, random numbers were generated
processed through Linear Feedback Shift Register (LFSR) to through sampling with 27 MHz of clock.
enhance the statistical properties. Two different harvesting
C. Post Processing
mechanism techniques have been used in this work and the
experimentation results have been presented. It is used for enhancing the results of TRNG that have
been produced by harvesting mechanism. In this work, LFSR
II. PROPOSED METHODOLOGY has been used for enhancing the statistical properties of keys.
Generation of true random number mainly consists of three LFSR is a shift register where the input it is obtained through
basic blocks such as entropy source, harvesting mechanism the feedback of previous state as a linear function. The most
and post processing and the generic block diagram of TRNG commonly used linear function of single bits is XOR. Hence an
has been shown in Fig 1. LFSR is most often a shift register whose input bit is driven by
the XOR of bits of the overall shift register value.

Figure 1. Generic block diagram of TRNG.

A. Entropy Source
The source for generation of true random number is
obtained from the entropy source which can be generated by
using clock jitter or metastability. In this work, SR latch is the Figure 2. Entropy source with meta beat counting.
important circuit that produces metastability. The SR latch
consists of two D-Flip-flops which takes clock as input and In order to drive the LFSR, initial value should be given
feeds to cross coupled NAND gates as shown Fig 2. to it which is known as seed, and it must start with a non-zero
Metastability has been induced in SR latch by state. LFSR with a well-chosen feedback function can produce
providing50MHz of clock inputs simultaneously. Whenever a sequence of bits that appears random. It can be implemented
the clock is in rising edge, logic ‘1’ will be loaded to the SR through flip-flops presented in Fig 3. The number of flip - flops
latches. According to the test condition of SR latch, logic ‘1’ that should be used in LFSRs is determined by polynomial
on both S and R inputs generate a indeterminate state which is expression. The maximum length of an LFSR sequence is
known as metastability. Further, during the falling edge of the given by 2n-1. In this work, 128 bit LFSR has been used and
clock, logic ‘0’ will be loaded to SR latches to retain the the polynomial is expressed as X127 + X125 + X100 + X98 + 1.
previous value to extract it. In this work totally 4 SR latches The seed value is
have only been used for the generation of true randomness. 11110011111010101001111111111000011110000000011111111111
11111111111100111110101010011111111110000111100000000111
B. Harvesting Mechanism 1111111111111111.
After applying post processing, the data have been
In this project two harvesting mechanisms have been used sampled to generate 128 bit true random keys. In this work,
namely Meta – beat counting and De – synchronization. In totally 1, 31, 072 bits have been generated and stored in
Meta beat counting technique, two 2:1 multiplexers have been BRAM (128 × 1024). The RTL view of the proposed method
used for arbitrarily selecting the Meta – beats where the input and the BRAM snapshot of generated keys have been shown in
to the multiplexers is the beat frequency generated by the pair Fig 4 and 5 respectively.
of counters which runs on different clock frequencies. Totally
eight beat frequencies have been generated by 4 SR Latches III. RESULTS AND DISCUSSION
and each multiplexer is given by 4 set of inputs and the Quartus 13.0 EDA tool has been used for the
selection line is common for both the multiplexers. The output implementation of PUF on Intel Cyclone II EP2C20F484C7
from the multiplexers is used to extract the true randomness. In FPGA. 128 bit true random number has been generated from
De – synchronization technique, the eight beat frequencies the proposed PUF architecture. The results from two different
from the D Flip-Flops were XORed to generate diffused true harvesting mechanisms have been taken with and without post
processing and have been evaluated with various statistical

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 2020 International Conference on Computer Communication and Informatics (ICCCI -2020), Jan. 22 – 24, 2020, Coimbatore, INDIA

analyses. Further, hardware analyses have been performed to TABLE I. Entropy analysis: Meta – beat counting PUF.
ensure the architectural efficiency of proposed PUF.
Set Raw TRNG Post-Processed TRNG

Set-1 0.984834 0.999947

Set-2 0.982734 0.999996

Set-3 0.984744 1

Set-4 0.985204 1

Set-5 0.983519 0.999997

TABLE II. Entropy analysis: De – synchronization PUF.

Figure 3. 128 bit LFSR architecture.
Set Raw TRNG Post-Processed TRNG

Set-1 0.999683 1

Set-2 0.999765 0.999998

Set-3 0.999658 0.999964

Set-4 0.999743 0.999997

Set-5 0.999556 0.999991

It is observed that entropy analysis from De –

synchronization mechanism yields better results than Meta beat
counting even without post processing.
b) Hamming Distance Calculation
Figure 4. RTL diagram of proposed PUF design.
Hamming Distance is another parameter that can be used
to evaluate how random the data is compared with other data .It
tells us by how many bits the data is differ from other [11]. It
can simply calculated using EXOR operation between two 128
bit numbers
HD(x1,x2…….xn)=
f ( xi ( x i1 , x i 2 ,.....x iM ) ⊕ xi +1 ( x ( i+1)1 , x ,.....x ))
( i +1) 2 ( i +1) M

Where 0 < i < N. Here x1, x2…….xn are the random

values, the function f computes the sum of the bits in resulting
XOR operation between xi and xi+1. The hamming distance for
PUF generated true random sequences has been calculated and
depicted in table 3 and 4.

TABLE III. Hamming distance calculation: Meta – beat counting PUF.

Figure 5. BRAM snapshot of PUF generated keys. Set Raw TRNG Post-Processed TRNG

A. Statistical Analyses Set-1 62.5703125 63.85546875

a) Entropy Analysis Set-2 62.614383338756916 63.91929710380735

It is a fundamental measure of randomness. It describes Set-3 62.64128843338214 64.01008622092077
the probability of ones and zeros in a set of true random data to
ensure its equidistribution [11]. For an ideal case, the entropy Set-4 62.650009759906304 64.06382978723404
should be 1 but approximation values nearer to it prove that the Set-5 62.6484059856864 64.06779440468445
generated sequence is random in nature. Entropy analysis has
been performed for PUF generated true random sequences and
the results have been presented in Table 1.

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 2020 International Conference on Computer Communication and Informatics (ICCCI -2020), Jan. 22 – 24, 2020, Coimbatore, INDIA

TABLE IV. Hamming distance calculation: De – synchronization PUF. TABLE V. NIST test results: Meta beat counting PUF.

Set Raw TRNG Post-Processed TRNG

Set-1 64.1552734375 64.04296875

Set-2 64.20175724048161 64.00715912788806

Set-3 64.16024076785423 64.00065072393038

Set-4 64.09018153425727 64.01542065196175

Set-5 64.07033181522446 64.03018867924528

From the Tables, it is evidenced that hamming distance

calculated from De – synchronization produces better
switching activity results than Meta beta counting method
which ensure the superiority of the De – synchronization
scheme.
c) Restart Experiment
TABLE VI. NIST test results: De – synchronization PUF.
Restart experiment is a key examination to separate
genuine irregularity and pseudo arbitrariness [12]. TRNG
produces new set of data during every restart cycle whereas
PRNG creates same random sequences for every restart cycle.
Figure 6 depicts the restart experiment results of proposed
PUF.

Figure 6. Restart experiment.

d) NIST SP 800 – 22 Batteris of Test e) Data Distribution Analysis

NIST stands for National Institute of Standards and Bit distribution and scatter plots provide the data
Technology released a test suite to evaluate the statistical distribution of true random sequences. Figure 7 and 8 exhibit
characteristics of any random number generator [13]. It takes the random distribution of true random sequences to validate
binary data as input and validates the TRNG in terms of three the unbiased nature of proposed PUF keys.
basic properties such as (i) Equidistribution of zeros and ones,
(ii) Unpredictability of sequences and (iii) No pattern on the B. Hardware Analyses
data set. Hardware Analyses for evaluating 128 bit TRNG has been
In this work, NIST SP 800 – 22 tests have been performed through evaluating the logic elements consumption
performed for 1, 00, 000 true random with the following test and power dissipation. Logic elements consist of Look Up
parameters and presented in Table 5 and 6. Tables (LUTs), MUX, Latches and Flip-flops to accommodate
Block frequency Test – Block length (M) = 128 the design on targeted FPGA whereas power dissipation
Non-overlapping Template – Block length (m) = 9 analysis exhibits the total power dissipated by the FPGA in
Overlapping Template – Block length (m) = 9 terms of static, dynamic and IO power. Tables (7 – 10) express
Approximate Entropy Test – Block length (m) = 8 the architectural efficiency of proposed PUF architectures.
Serial Test – Block length (m) = 10
Linear Complexity Test – Block length (M) = 500
P Value should be greater than 0.01to pass the test.

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 2020 International Conference on Computer Communication and Informatics (ICCCI -2020), Jan. 22 – 24, 2020, Coimbatore, INDIA

Logic Elements Combinational Functions 881

Consumption Logic Registers 891
Static Power 47.40
Power Dissipation (mW) Dynamic Power 4.41
IO Power 44.81
Memory Bits
1, 31, 072
(No. of Keys = 1024)

IV. CONCLUSION
Metastability influenced PUF architecture has been
proposed in this work to generate random keys for
Figure 7. Scatter plot: XOR PUF. cryptographic applications. Entropy source consists of only 4
SR latches where two post processing mechanism have been
suggested and its performance has been analyzed through
statistical and hardware analyses. To improve the statistical
properties of PUF generated keys, LFSR post processing has
been adopted. From the observations, it has been evidenced
that De- synchronization technique effectively extracts the true
randomness from the entropy source with less area overhead.
Future work will be on developing an authentication scheme
by exploiting the features of proposed PUF architecture.
Figure 8. Bit distribution plot: XOR PUF.
TABLE VII. Hardware analysis: Meta beat counting PUF without post
ACKNOWLEDGMENT
processing. The authors wish to thank SASTRA University for
Parameters 128 bit providing infrastructure through the Research &
(Target Platform – Altera Cyclone II EP2C20F484C7 TRNG Modernization Fund (Ref. No: R&M / 0026 / SEEE – 010 /
FPGA)
Logic Elements Combinational Functions 622 2012 – 13) to carry out the research work.
Consumption Logic Registers 602
Static Power 47.38 REFERENCES
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