LTC1773

Synchronous Step-Down
DC/DC Controller
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FEATURES DESCRIPTIO
■ High Efficiency: Up to 95% The LTC®1773 is a current mode synchronous buck regu-
■ Constant Frequency 550kHz Operation lator controller that drives external complementary power
■ VIN from 2.65V to 8.5V MOSFETs using a fixed frequency architecture. The oper-
■ VOUT from 0.8V to VIN ating supply range is from 2.65V to 8.5V, making it
■ OPTI-LOOP® Compensation Minimizes COUT suitable for 1- or 2-cell lithium-ion battery powered appli-
■ Synchronizable up to 750kHz cations. Burst Mode® operation provides high efficiency at
■ Selectable Burst Mode Operation low load currents. 100% duty cycle provides low dropout
■ Low Quiescent Current: 80µµA operation which extends operating time in battery-oper-
■ Low Dropout Operation: 100% Duty Cycle ated systems.
■ Secondary Winding Regulation The operating frequency is internally set at 550kHz, allow-
■ Soft-Start ing the use of small surface mount inductors. For switch-
■ Current Mode Operation for Excellent Line and ing-noise sensitive applications, it can be synchronized up
Load Transient Response to 750kHz. Peak current limit is user programmable with
■ Low Shutdown IQ = 10µA an external high side sense resistor. A SYNC/FCB control
■ ±1.5% Reference Accuracy pin guarantees regulation of secondary windings regard-
■ Precision 2.5V Undervoltage Lockout less of load on the main output by forcing continuous
■ Available in 10-Lead MSOP operation. Burst Mode operation is inhibited during syn-
U chronization or when the SYNC/FCB pin is pulled low to
APPLICATIO S reduce noise and RF interference. Soft-start is provided by
■ Cellular Telephones an external capacitor.
■ RF PA Supplies Synchronous rectification increases efficiency and elimi-
■ Portable Instruments nates the need for a Schottky diode, saving components
■ Wireless MODEMS and board space. The LTC1773 comes in a 10-lead MSOP
■ Distributed Power Systems package.
■ Notebook and Palm Top Computers, PDAs , LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
■ Single and Dual Cell Lithium-Ion Powered Devices All other trademarks are the property of their respective owners.
OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815.

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TYPICAL APPLICATIO
VIN
2.65V TO 8.5V
High Efficiency
100
+ 95 VIN = 3.3V
SYNC/FCB VIN RSENSE CIN
0.025Ω 68µF 90 VIN = 5V
RUN/SS SENSE–
85
EFFICIENCY (%)

0.1µF L1 VIN = 8V
ITH TG 3µH
VOUT 80
47pF LTC1773
30k SW 2.5V 75
220pF 70
VFB BG
GND
65
Si9801DY + COUT
180µF 60
80.6k L = SUMIDA CDRH6D28-3R0
55
169k 1 10 100 1000 5000
1773 F01
OUTPUT CURRENT (mA)

Figure 1. Step-Down Converter 1773 F1b

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LTC1773
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ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage .............................. –0.3V to 10.0V ORDER PART
ITH Voltage ................................................ –0.3V to 2.5V TOP VIEW NUMBER
RUN/SS, VFB, SENSE– Voltages .................. –0.3V to VIN ITH
RUN/SS
1
2
10
9
SW
SENSE– LTC1773EMS
SYNC/FCB Voltage ...................................... –0.3V to VIN SYNC/FCB
VFB
3
4
8
7
VIN
TG
BG, TG Voltages...........................................–0.3V to VIN GND 5 6 BG MS PART MARKING
SW Voltage ...................................................– 5V to 11V MS PACKAGE
10-LEAD PLASTIC MSOP
Operating Ambient Temperature Range TJMAX = 125°C, θJA = 120°C/W LTMV
(Note 2) ...............................................–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Storage Temperature Range ..................–65°C to 150°C
Lead Free Part Marking: http://www.linear.com/leadfree/
Lead Temperature (Soldering, 10 sec.)................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, TA = 25°C. VIN = 5V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IVFB Feedback Current (Note 4) 20 60 nA
VFB Regulated Feedback Voltage (Note 4) ● 0.788 0.80 0.812 V
∆VOVL ∆Output Overvoltage Lockout ∆VOVL = VOVL – VFB 40 60 80 mV
∆VFB Reference Voltage Line Regulation VIN = 2.7V to 8.5V (Note 4) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation ITH at 1.0V (Note 4) 0.2 0.8 %
ITH at 0.6V (Note 4) –0.2 –0.8 %
IS Input DC Bias Current (Note 5)
Normal Mode VIN = 5V, VITH = OPEN, VSYNC/MODE = OPEN 400 600 µA
Burst Mode Operation VITH = 0V, VIN = 5V, VSYNC/MODE = OPEN 80 µA
Shutdown VRUN/SS = 0V, 2.7V < VIN < 8.5V 10 30 µA
Shutdown VRUN/SS = 0V, VIN < 2.4V 2 5 µA
VRUN/SS RUN/SS Threshold 0.4 0.7 1.0 V
IRUN/SS Soft-Start Current Source VRUN/SS = 0V 0.75 1.5 2.5 µA
VSYNC/FCB Auxiliary Feedback Threshold VSYNC/FCB Ramping Negative 0.76 0.8 0.84 V
ISYNC/FCB SYNC/FCB Pull-Up Current VSYNC/FCB = 0V 0.1 0.4 1.0 µA
fOSC Oscillator Frequency VFB = 0.8V 500 550 600 kHz
VFB = 0V 55 kHz
VUVLO Undervoltage Lockout VIN Ramping Down from 3V ● 2.35 2.5 2.65 V
VIN Ramping Up from 0V ● 2.65 2.8 V
∆VSENSE(MAX) Maximum Current Sense Voltage ● 85 100 115 mV
TG tr Top Gate Drive Rise Time CLOAD = 3000pF (Note 6) 45 160 ns
TG tf Top Gate Drive Fall Time CLOAD = 3000pF (Note 6) 48 150 ns
BG tr Bottom Gate Drive Rise Time CLOAD = 3000pF (Note 6) 80 180 ns
BG tf Bottom Gate Drive Fall Time CLOAD = 3000pF (Note 6) 45 150 ns

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 LTC1773
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: TJ is calculated from the ambient temperature TA and power dissipation
may cause permanent damage to the device. Exposure to any Absolute PD according to the following formula:
Maximum Rating condition for extended periods may affect device LTC1773: TJ = TA + (PD • 120°C/W)
reliability and lifetime. Note 4: The LTC1773 is tested in a feedback loop which servos VFB to the
Note 2: The LTC1773 is guaranteed to meet performance specifications from balance point for the error amplifier (VITH = 0.8V)
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature Note 5: Dynamic supply current is higher due to the gate charge being
range are assured by design, characterization and correlation with statistical delivered at the switching frequency.
process controls.
Note 6: Rise and fall times are measured using 10% and 90% levels.

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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Input Voltage
100
VIN = 5V VOUT = 2.5V VOUT = 2.5V
100 VOUT = 2.5V 100 SEE FIGURE 1 SEE FIGURE 1
SEE FIGURE 1 VIN = 3.3V 95
90 90
IOUT = 1A

EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)

VIN = 5V
90
80 80
Burst Mode VIN = 8V
OPERATION 85
70 70
SYNC(750kHz) IOUT = 100mA

60 80
60

FORCED CONTINUOUS
50 50 75
1 10 100 1000 5000 1 10 100 1000 10,000 2 4 6 8 10
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) INPUT VOLTAGE (V)
1773 G01 1773 G02 1773 G03

VIN-VOUT Dropout Voltage Input and Shutdown Currents

Load Regulation vs Load Current vs Input Voltage
0 400 500
RSENSE = 0.025Ω RSENSE = 0.025Ω
450
SEE FIGURE 1 350 VOUT = 1.8V
– 0.05 Si9801DY SYNC TO 750kHz
400
300
NORMALIZED VOUT (%)

INPUT CURRENT (µA)

350 VOUT = 1.8V

– 0.10
VIN-VOUT (mV)

250 Si9801DY
300 RSENSE = 0.025Ω
200 250 L = CDRH6D28-3RO
– 0.15
200
150
– 0.20 Burst Mode OPERATION
150
100
100
– 0.25
50 50
SHUTDOWN
– 0.30 0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 500 1000 1500 2000 2500 2 4 6 8 10
LOAD CURRENT (A) LOAD CURRENT (mA) INPUT VOLTAGE (V)
1773 G16 1773 G05 1773 G06

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LTC1773
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TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense Maximum Current Sense Maximum Current Sense
Threshold vs VRUN/SS Threshold vs Temperature Threshold vs VITH
120 120
MAXIMUM CURRENT SENSE THRESHOLD (mV)

105

MAXIMUM CURRENT SENSE THRESHOLD (mV)

MAXIMUM CURRENT SENSE THRESHOLD (mV)

100 100

80 100 80

60 60
Burst Mode
OPERATION
40 95 40

20 20
FORCED
CONTINUOUS
0 85 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 – 60 – 40 – 20 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VRUN/SS (V) TEMPERATURE (°C) VITH (V)
1773 G07 1773 G08 1773 G09

Oscillator Frequency vs RUN/SS Pin Current vs

Temperature Temperature Burst Mode Operation
560 2.5
ILOAD = 100mA
SEE FIGURE 9

VOUT
550 2.0
RUN/SS CURRENT (µA)

20mV/DIV
FREQUENCY (kHz)

540 1.5

IL
500mA/DIV
530 1.0

520 0.5 1773 G12

– 60 –40 –20 0 20 40 60 80 100 120 140 – 60 –40 –20 0 20 40 60 80 100 120 140 VIN = 5V 20µs/DIV
VOUT = 2.5V
TEMPERATURE (°C) TEMPERATURE (°C)
1773 G10 1773 G11

Load Step (Burst Mode Load Step (Continuous

Start-Up Operation) Mode)
SEE FIGURE 9 SEE FIGURE 9 SEE FIGURE 9
VOUT
2V/DIV
VOUT VOUT
100mV/DIV 100mV/DIV

VRUN/SS
1V/DIV

IL IL IL
2A/DIV 2A/DIV 2A/DIV

1773 G14
VIN = 5V 40ms/DIV 1773 G13 VIN = 5V 100µs/DIV VIN = 5V 100µs/DIV 1773 G15

VOUT = 2.5V VOUT = 2.5V VOUT = 2.5V

100mA TO 5A LOAD STEP 100mA TO 5A LOAD STEP

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 LTC1773
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PIN FUNCTIONS
ITH (Pin 1): Error Amplifier Compensation Point. The VFB (Pin 4): Feedback Pin. Receives the feedback voltage
current comparator threshold increases with this control from an external resistive divider across the output. Do not
voltage. Nominal voltage range for this pin is 0V to 1.2V. use more than 0.01µF of feedforward capacitance from FB
Under high duty cycle and nearing current limit, ITH can to the output.
swing up to 2.4V.
GND (Pin 5): Ground Pin.
RUN/SS (Pin 2): Combination of Soft-Start and Run
BG (Pin 6): Bottom Gate Driver of External N-Channel
Control Inputs. A capacitor to ground at this pin sets the
Power MOSFET. This pin swings from 0V to VIN.
ramp time to full current output. The time is approximately
0.8s/µF. Forcing this pin below 0.4V shuts down all the TG (Pin 7): Top Gate Driver of External P-Channel Power
circuitry. MOSFET. This pin swings from 0V to VIN.
SYNC/FCB (Pin 3): Multifunction Pin. This pin performs VIN (Pin 8) : Main Supply Pin. Must be closely decoupled
three functions: 1) secondary winding feedback input, 2) to GND (pin 5).
external clock synchronization and 3) Burst Mode opera- SENSE–(Pin 9): The Negative Input to the Current Com-
tion or forced continuous mode select. For secondary parator. A sense resistor between this pin and VIN sets the
winding applications, connect to a resistive divider from peak current in the top switch. Connect this pin to the
the secondary output. To synchronize with an external source of the external P-Channel power MOSFET.
clock, apply a TTL/CMOS compatible clock with a fre-
quency between 585kHz and 750kHz. To select Burst SW (Pin 10): Switch Node Connection to Inductor. This
Mode operation, tie SYNC/FCB to VIN. Grounding this pin pin connects to the drains of the external main and
forces continuous operation. synchronous power MOSFET switches.

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FUNCTIONAL DIAGRA
BURST Y Y = “0” ONLY WHEN X IS A CONSTANT “1”
DEFEAT
0.4µA
X
SLOPE
8 VIN
COMP
SYNC/FCB 3 OSC
0.4V
9 SENSE –

0.6V –
–
SYNC
DEFEAT EN
VFB 4 + 0.8V + – – +
SLEEP ICOMP
+ 50mV
FREQ
SHIFT EA 0.22V +
BURST
– COMP
1.5µA ITH
0.8V REF 1
S Q
RUN/
RUN/SOFT
2
SOFT-START
START
RUN/SS R Q SWITCHING 7 TG
UVLO LOGIC
TRIP = 2.5V AND
– BLANKING ANTI
CIRCUIT SHOOT-THRU
OVDET
0.86V + 6 BG
SHUTDOWN
+
10 SW
IRCMP
0.8V – –
5 GND
FCB
+
Figure 2. 1773 FD

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LTC1773
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OPERATIO (Refer to Functional Diagram)

Main Control Loop secondary winding regulation as described in Auxiliary

The LTC1773 uses a constant frequency, current mode Winding Control Using SYNC/FCB Pin in the Applications
step- down architecture to drive an external pair of comple- Information section.
mentary power MOSFETs. During normal operation, the When the converter operates in Burst Mode operation the
external top P-channel power MOSFET turns on each cycle peak current of the inductor is set to approximately a third
when the oscillator sets the RS latch, and turns off when of the maximum peak current value during normal opera-
the current comparator ICOMP resets the RS latch. The tion even though the voltage at the ITH pin indicates a lower
peak inductor current at which ICOMP resets the RS latch value. The voltage at the ITH pin drops when the inductor’s
is controlled by the voltage on the ITH pin, which is the average current is greater than the load requirement. As
output of error amplifier EA. The VFB pin, described in the the ITH voltage drops below 0.22V, the BURST compara-
Pin Functions section, allows EA to receive an output tor trips, causing the internal sleep line to go high and turn
feedback voltage from an external resistive divider. When off both power MOSFETs.
the load current increases, it causes a slight decrease in The circuit enters sleep mode with both power MOSFETs
the feedback voltage relative to the 0.8V reference, which turned off. In sleep mode, the internal circuitry is partially
in turn causes the ITH voltage to increase until the average turned off, reducing the quiescent current to about 80µA.
inductor current matches the new load current. While the The load current is now being supplied from the output
top P-channel MOSFET is off, the bottom N-channel capacitor. When the output voltage drops, causing ITH to
MOSFET is turned on until either the inductor current
rise above 0.27V, the internal sleep line goes low, and the
starts to reverse, as indicated by the current reversal
LTC1773 resumes normal operation. The next oscillator
comparator IRCMP, or the beginning of the next cycle.
cycle will turn on the external top MOSFET and the switch-
The main control loop is shut down by pulling the RUN/SS ing cycle repeats.
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge the external soft-start capacitor Short-Circuit Protection
CSS. When CSS reaches 0.7V, the main control loop is When the output is shorted to ground, the frequency of the
enabled with the internal buffered ITH voltage clamped at oscillator is reduced to about 55kHz, 1/10 the nominal
approximately 5% of its maximum value. As CSS contin- frequency. This frequency foldback ensures that the in-
ues to charge, the internal buffered ITH is gradually re- ductor current has more time to decay, thereby preventing
leased allowing normal operation to resume. runaway. The oscillator’s frequency will gradually in-
An overvoltage comparator, 0V, guards against transient crease to 550kHz after VFB rises above 0.4V.
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top Frequency Synchronization
MOSFET is turned off and the bottom MOSFET is turned on The LTC1773 can be synchronized with an external TTL/
until the overvoltage condition is cleared. CMOS compatible clock signal. The frequency range of
this signal must be from 585kHz to 750kHz. Do not
Burst Mode Operation synchronize the LTC1773 below 585kHz as this may cause
The LTC1773 is capable of Burst Mode operation in which abnormal operation and an undesired frequency spec-
the external power MOSFETs operate intermittently based trum. The top MOSFET turn-on follows the rising edge of
on load demand. To enable Burst Mode operation, simply the external source.
allow the SYNC/FCB pin to float or connect it to a logic When the LTC1773 is clocked by an external source, Burst
high. To disable Burst Mode operation and force continu- Mode operation is disabled; the LTC1773 then operates in
ous mode, connect the SYNC/FCB pin to GND. The thresh- PWM pulse skipping mode preventing current reversal. In
old voltage between Burst Mode operation and forced this mode, when the output load is very low, current
continuous mode is 0.8V. This can be used to assist in comparator ICOMP remains tripped for more than one cycle
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 LTC1773
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OPERATIO (Refer to Functional Diagram)

and forces the main switch to stay off for the same number Low Supply Operation
of cycles. Increasing the output load current slightly, The LTC1773 is designed to operate down to a 2.65V
above the minimum required for discontinuous conduc- supply voltage. For proper operation at this low input
tion mode, allows constant frequency PWM. voltage, sub-logic level MOSFETs are required. When the
Frequency synchronization is inhibited when the feedback value of the output voltage is very close to the input
voltage, VFB, is below 0.6V. This prevents the external voltage, the converter is running at high duty cycles or in
clock from interfering with the frequency foldback for dropout where the main switch is on continuously. See
short-circuit protection. Efficiency Considerations in the Applications Information
section.
Dropout Operation
When the input supply voltage decreases toward the Slope Compensation and Inductor Peak Current
output voltage, the duty cycle increases toward the maxi- Slope compensation provides stability by preventing
mum on-time. Further reduction of the supply voltage subharmonic oscillations. It works by internally adding a
forces the main switch to remain on for more than one ramp to the inductor current signal at duty cycles in excess
cycle until it reaches 100% duty cycle. The output voltage of 30%. This causes the internal current comparator to trip
will then be determined by the input voltage minus the IR earlier. The ITH clamp level is also reached earlier than
voltage drop across the external P-channel MOSFET, conditions in which the duty cycle is below 30%. As a
sense resistor, and the inductor. result, the maximum inductor peak current is lower for
VOUT/VIN > 0.3 than when VOUT/VIN < 0.3.
Undervoltage Lockout
To compensate for this loss in maximum inductor peak
A precision undervoltage lockout shuts down the LTC1773 current during high duty cycles, the LTC1773 uses a
when VIN drops below 2.5V, making it ideal for single patent pending scheme that raises the ITH clamp level
lithium-ion battery applications. In shutdown, the LTC1773 (proportional to the amount of slope compensation) when
draws only several microamperes, which is low enough to duty cycle is above 30%.
prevent deep discharge and possible damage to the lithium-
ion battery that’s nearing its end of charge. A 150mV
hysteresis ensures reliable operation with noisy supplies.

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APPLICATIONS INFORMATION
The basic LTC1773 application circuit is shown in average output current IMAX equal to the peak value less
Figure 1. External component selection is driven by the half the peak-to-peak ripple current ∆IL.
load requirement and begins with the selection of RSENSE.
Allowing a margin for variations in the LTC1773 and
Once RSENSE is known, L can be chosen, followed by the
external component values yields:
external power MOSFETs. Finally, CIN and COUT are se-
lected. RSENSE = 70mV/IMAX

RSENSE Selection for Output Current Inductor Value Calculation

RSENSE is chosen based on the required output current. The inductor selection will depend on the operating fre-
The LTC1773 current comparator has a maximum thresh- quency of the LTC1773. The internal preset frequency is
old of 100mV/RSENSE. The current comparator threshold 550kHz, but can be externally synchronized up to 750kHz.
sets the peak of the inductor current, yielding a maximum
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LTC1773
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APPLICATIONS INFORMATION
The operating frequency and inductor selection are inter- inductor ripple current and consequent output voltage
related in that higher operating frequencies allow the use ripple. Do not allow the core to saturate!
of smaller inductor and capacitor values. However, oper-
Molypermalloy (from Magnetics, Inc.) is a very good, low
ating at a higher frequency generally results in lower
loss core material for toroids, but it is more expensive than
efficiency because of external MOSFET gate charge losses.
ferrite. A reasonable compromise from the same manu-
The inductor value has a direct effect on ripple current. The facturer is Kool Mµ. Toroids are very space efficient,
ripple current, ∆IL, decreases with higher inductance or especially when you can use several layers of wire. Be-
frequency and increases with higher VIN or VOUT. cause they generally lack a bobbin, mounting is more
difficult. However, new designs for surface mount are
1 ⎛ V ⎞ available which do not increase the height significantly.
∆IL = VOUT ⎜ 1– OUT ⎟
( )( )
f L ⎝ VIN ⎠ (1)
Power MOSFET and Schottky Diode Selection
Accepting larger values of ∆IL allows the use of lower Two external power MOSFETs must be selected for use
inductances, but results in higher output voltage ripple with the LTC1773: a P-channel MOSFET for the top (main)
and greater core losses. A reasonable starting point for switch, and an N-channel MOSFET for the bottom (syn-
setting ripple current is 30% to 40% of IMAX. Remember, chronous) switch.
the maximum ∆IL occurs at the maximum input voltage. The peak-to-peak gate drive levels are set by the VIN
The inductor value also has an effect on Burst Mode voltage. Therefore, for VIN > 5V, logic-level threshold
operation. The transition to low current operation begins MOSFETs should be used. But, for VIN < 5V, sub-logic
when the inductor current peaks fall to approximately 1/3 level threshold MOSFETs (VGS(TH) < 3V) should be used.
its original value. Lower inductor values (higher ∆IL) will In these applications, make sure that the VIN to the
cause this to occur at lower load currents, which can cause LTC1773 is less than 8V because the absolute maximum
a dip in efficiency in the upper range of low current VGS rating of the majority of these sub-logic threshold
operation. In Burst Mode operation, lower inductance MOSFETs is 8V.
values will cause the burst frequency to increase. Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), reverse transfer capacitance CRSS,
Inductor Core Selection
input voltage, maximum output current, and total gate
Once the value for L is known, the type of inductor must be charge. When the LTC1773 is operating in continuous
selected. High efficiency converters generally cannot af- mode the duty cycles for the top and bottom MOSFETs are
ford the core loss found in low cost powdered iron cores, given by:
forcing the use of more expensive ferrite, molypermalloy,
Main Switch Duty Cycle = VOUT/VIN
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN
inductance selected. As inductance increases, core losses The MOSFET power dissipations at maximum output
go down. Unfortunately, increased inductance requires current are given by:
more turns of wire and therefore copper losses will in-
crease. Ferrite designs have very low core losses and are
VOUT
preferred at high switching frequencies, so design goals PMAIN =
VIN
(IMAX ) (1 + δ )RDSON +
2

can concentrate on copper loss and preventing saturation.

K(VIN ) (IMAX )(C RSS )( f)
Ferrite core material saturates “hard”, which means that 2
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in

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 LTC1773
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APPLICATIONS INFORMATION
VIN – VOUT RMS capacitor current is given by:
PSYNC = (IMAX ) (1 + δ )RDS(ON)
2

[ VOUT (VIN – VOUT )]

VIN 12

where δ is the temperature dependency of RDS(ON) and K CIN required IRMS ≅ IMAX
VIN
is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside P-channel This formula has a maximum at VIN = 2VOUT, where
equation includes an additional term for transition losses, IRMS = IOUT/2. This simple worst-case condition is
which are highest at high input voltages. The synchronous commonly used for design because even significant de-
MOSFET losses are greatest at high input voltage or during viations do not offer much relief. Note that capacitor
a short-circuit when the duty cycle in this switch is nearly manufacturer’s ripple current ratings are often based on
100%. 2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
The term (1 + δ) is generally given for a MOSFET in the temperature than required. Several capacitors may also be
form of a normalized RDS(ON) vs temperature curve, but paralleled to meet size or height requirements in the
δ = 0.005/°C can be used as an approximation for low design. Always consult the manufacturer if there is any
voltage MOSFETs. CRSS is usually specified in the MOSFET question.
characteristics. The constant K = 1.7 can be used to
estimate the contributions of the two terms in the main COUT Selection
switch dissipation equation.
The selection of COUT is driven by the required effective
Typical gate charge for the selected P-channel MOSFET series resistance (ESR). Typically, once the ESR require-
should be less than 30nC (at 4.5VGS) while the turn-off ment is satisfied the capacitance is adequate for filtering.
delay should be less than 150ns. However, due to differ- The output ripple (∆VOUT) is determined by:
ences in test and specification methods of various MOSFET
manufacturers, the P-channel MOSFET ultimately should ⎛ 1 ⎞
be evaluated in the actual LTC1773 application circuit to ∆VOUT ≅ ∆IL ⎜ ESR + ⎟
⎝ 8fC OUT ⎠
ensure proper operation.
A Schottky diode can be placed in parallel with the syn- where f = operating frequency, COUT = output capacitance
chronous MOSFET to improve efficiency. It conducts and ∆IL = ripple current in the inductor. The output ripple
during the dead-time between the conduction of the two is highest at maximum input voltage since ∆IL increases
power MOSFETs. This prevents the body diode of the with input voltage. With ∆IL = 0.4IOUT(MAX) and allowing
bottom MOSFET from turning on and storing charge for 2/3 of the ripple due to ESR, the output ripple will be
during the dead-time, which could cost as much as 1% in less than 50mV at max VIN assuming:
efficiency. A 1A Schottky is generally a good size for 5A to COUT required ESR < 2 RSENSE
8A regulators due to the relatively small average current.
Larger diodes result in additional transition losses due to COUT > 1/(8fRSENSE)
their larger junction capacitance. The diode may be omit- The first condition relates to the ripple current into the ESR
ted if the efficiency loss can be tolerated. of the output capacitance while the second term guaran-
tees that the output voltage does not significantly dis-
CIN Selection charge during the operating frequency period due to ripple
In continuous mode, the source current of the top MOSFET current. The choice of using smaller output capacitance
is a square wave of duty cycle VOUT/VIN. To prevent large increases the ripple voltage due to the discharging term
voltage transients, a low ESR input capacitor sized for the but can be compensated for by using capacitors of very
maximum RMS current must be used. The maximum low ESR to maintain the ripple voltage at or below 50mV.
1773fb

9
LTC1773
U U W U
APPLICATIONS INFORMATION
The ITH pin OPTI-LOOP compensation components can be Run/Soft-Start Function
optimized to provide stable, high performance transient
The RUN/SS pin is a dual purpose pin that provides the
response regardless of the output capacitors selected.
soft-start function and a means to shut down the LTC1773.
Manufacturers such as Nichicon, United Chemicon and Soft-start reduces surge currents from VIN by gradually
Sanyo should be considered for high performance through- increasing the internal current limit. Power supply se-
hole capacitors. The OS-CON semiconductor dielectric quencing can also be accomplished using this pin.
capacitor available from Sanyo has the lowest ESR/size
An internal 1.5µA current source charges up an external
ratio of any aluminum electrolytic at a somewhat higher
capacitor CSS. When the voltage on RUN/SS reaches 0.7V
price. Once the ESR requirement for COUT has been met,
the LTC1773 begins operating. As the voltage on RUN/SS
the RMS current rating generally far exceeds the
continues to ramp from 0.7V to 1.8V, the ITH clamp is also
IRIPPLE(P-P) requirement.
ramped at a proportionally linear rate. Depending on the
In surface mount applications multiple capacitors may external RSENSE used, the peak inductor current, and thus
have to be paralleled to meet the ESR or RMS current the internal current limit, rises with the RUN/SS voltage.
handling requirements of the application. Aluminum elec- The output current thus ramps up slowly, charging the
trolytic and dry tantalum capacitors are both available in output capacitor. If RUN/SS has been pulled all the way to
surface mount configurations. In the case of tantalum, it is ground, there will be a delay before the current starts
critical that the capacitors are surge tested for use in increasing and is given by:
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalum, available in case
heights ranging from 2mm to 4mm. Other capacitor types t DELAY =
0.7 C SS
1.5µA
( )
= 0.47s / µF C SS
include Sanyo OS-CON and POSCAP, Nichicon PL series,
Panisonic SP series and Sprague 593D and 595D series. Pulling the RUN/SS pin below 0.4V puts the LTC1773 into
Consult the manufacturer for other specific recommenda- a low quiescent current shutdown mode (IQ < 10µA). This
tions. pin can be driven directly from logic as shown in Figure 4.
Diode D1 in Figure 4 reduces the start delay but allows CSS
Output Voltage Programming to ramp up slowly providing the soft-start function. This
The output voltage is set by a resistive divider according diode can be deleted if soft-start is not needed.
to the following formula: 3.3V OR 5V RUN/SS RUN/SS

⎛ R2⎞ D1
VOUT = 0.8V⎜ 1 + ⎟ (2)
⎝ R1⎠ CSS
CSS

The external resistive divider is connected to the output as 1773 F04

shown in Figure 3, allowing remote voltage sensing.

Figure 4. RUN/SS Pin Interfacing
0.8V ≤ VOUT ≤ 8.5V

Auxiliary Winding Control Using SYNC/FCB Pin

R2

VFB
The SYNC/FCB pin can be used as a secondary feedback
to provide a means of regulating a flyback winding output.
LTC1773 R1
When this pin drops below its ground referenced 0.8V
GND
threshold, continuous mode operation is forced. In con-
1773 F03
tinuous mode, the P-channel main and N-channel syn-
Figure 3. Setting the LTC1773 Output Voltage
chronous switches are switched continuously regardless
of the load on the main output.
1773fb

10
 LTC1773
U U W U
APPLICATIONS INFORMATION
Synchronous switching removes the normal limitation Although all dissipative elements in the circuit produce
that power must be drawn from the inductor primary losses, four main sources usually account for most of the
winding in order to extract power from auxiliary windings. losses in LTC1773 circuits: VIN quiescent current, external
With continuous synchronous operation, power can be power MOSFET gate charge current, I2R losses, and
drawn from the auxiliary windings without regard to the topside MOSFET transition losses.
primary output load.
1. The VIN quiescent current is due to the DC bias current
The secondary output voltage is set by the turns ratio of the as given in the electrical characteristics, it excludes
transformer in conjunction with a pair of external resistors MOSFET driver and control currents. VIN current results
returned to the SYNC/FCB pin as shown in Figure 5. The in a small loss which increases with VIN.
secondary regulated voltage, VSEC, in Figure 5 is given by:
2. The external MOSFET gate charge current results from
switching the gate capacitance of the external power
⎛ R4 ⎞
VSEC ≅ (N + 1)VOUT − VDIODE > 0.8V⎜ 1 + ⎟ MOSFET switches. Each time the gate is switched from
⎝ R3 ⎠
high to low to high again, a packet of charge dQ moves
where N is the turns ratio of the transformer and VOUT is from VIN to ground. The resulting dQ/dt is the current
the main output voltage sensed by VFB. out of VIN; it is typically larger than the DC bias current.
In continuous mode, IGATECHG = f(QT + QB) where QT
and QB are the gate charges of the external main and
synchronous switches. Both the DC bias and gate
charge losses are proportional to VIN and thus their
effects will be more pronounced at higher supply volt-
VIN VSEC
+ ages.
LTC1773 L1 1µF
R4 TG
1:N
VOUT 3. I2R losses are calculated from the resistances of the
SYNC/FCB external RSENSE, the external power MOSFETs (RSW)
R3 SW and the external inductor (RL). In continuous mode, the
+ average output current flowing through inductor L is
BG COUT “chopped” between the main switch and the synchro-
1773 F05
nous switch. Thus, the series resistance looking into
the SW pin from L is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC), as follows:
Figure 5. Secondary Output Loop Connection
RSW = (RDS(ON)TOP +RSENSE) • DC + RDS(ON)BOT • (1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
Efficiency Considerations be obtained from the MOSFET manufactures’s
The efficiency of a switching regulator is equal to the datasheets. Thus, to obtain I2R losses, simply add RSW
output power divided by the input power times 100%. It is and RL together and multiply their sum by the square of
often useful to analyze individual losses to determine what the average output current.
is limiting the efficiency and which change would produce 4. Transition losses apply to the topside MOSFET and
the most improvement. Efficiency can be expressed as: increase when operating at high input voltages and
Efficiency = 100% – (L1 + L2 + L3 + ...) higher operating frequencies. Transition losses can be
estimated from:
where L1, L2, etc. are the individual losses as a percentage
of input power. Transition Loss = 2(VIN)2IO(MAX)CRSS(f)

1773fb

11
LTC1773
U U W U
APPLICATIONS INFORMATION
Other losses including CIN and COUT ESR dissipative bandwidth of the loop will be increased by decreasing CC.
losses, and inductor core losses, generally account for If RC is increased by the same factor that CC is decreased,
less than 2% total additional loss. the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency
Checking Transient Response range of the feedback loop. The output voltage settling
The regulator loop response can be checked by looking at behavior is related to the stability of the closed-loop
the load transient response. Switching regulators take system and will demonstrate the actual overall supply
several cycles to respond to a step in load current. When performance. For a detailed explanation of optimizing the
a load step occurs, VOUT immediately shifts by an amount compensation components, including a review of control
equal to (∆ILOAD)(ESR), where ESR is the effective series loop theory, refer to Application Note 76.
resistance of COUT. ∆ILOAD also begins to charge or dis- A second, more severe transient is caused by switching in
charge COUT, which generates a feedback error signal. The loads with large (>1µF) supply bypass capacitors. The
regulator loop then returns VOUT to its steady-state value. discharged bypass capacitors are effectively put in parallel
During this recovery time, VOUT can be monitored for with COUT, causing a rapid drop in VOUT. No regulator can
overshoot or ringing. OPTI-LOOP compensation allows deliver enough current to prevent this problem if the load
the transient response to be optimized over a wide range switch resistance is low and it is driven quickly. The only
of output capacitance and ESR values. The availability of solution is to limit the rise time of the switch drive so that
the ITH pin not only allows optimization of control loop the load rise time is limited to approximately (25)(CLOAD).
behavior but also provides a DC coupled and an AC filtered Thus a 10µF capacitor would require a 250µs rise time,
closed-loop response test point. The DC step, rise time limiting the charging current to about 200mA.
and settling at this test point reflects the closed loop
response. Assuming a predominantly second order sys- Minimum On-Time Considerations
tem, phase margin and/or damping factor can be esti- Minimum on-time, tON(MIN), is the smallest amount of
mated using the percentage of overshoot seen at this pin. time that the LTC1773 is capable of turning the top
The bandwidth can also be estimated by examining the MOSFET on and off again. It is determined by internal
rise time at the pin. The ITH external components shown in timing delays and the gate charge required to turn on the
the Figure 1 circuit will provide an adequate starting point top MOSFET. The minimum on-time for the LTC1773 is
for most applications. about 250ns. Low duty cycle and high frequency synchro-
The ITH series RC-CC filter sets the dominant pole-zero nous applications may approach this minimum on-time
loop compensation. The values can be modified slightly limit and care should be taken to ensure that:
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the VOUT
t ON(MIN)<
particular output capacitor type and value have been f • VIN
determined. The output capacitors need to be decided
upon because the various types and values determine the If the duty cycle falls below what can be accommodated by
loop feedback factor gain and phase. An output current the minimum on-time, the LTC1773 will begin to skip
pulse of 20% to 100% of full load current having a rise time cycles. The output voltage will continue to be regulated,
of 1µs to 10µs will produce output voltage and ITH pin but the ripple current and ripple voltage will increase.
waveforms that will give a sense of the overall loop If an application can operate close to the minimum on-
stability without breaking the feedback loop. The initial time limit, an inductor must be chosen that has low
output voltage step may not be within the bandwidth of the enough inductance to provide sufficient ripple amplitude
feedback loop, so the standard second order overshoot/ to meet the minimum on-time requirement. As a general
DC ratio cannot be used to determine phase margin. The rule, keep the inductor ripple current equal or greater than
gain of the loop will be increased by increasing RC, and the 30% of the IOUT(MAX) at VIN(MAX).
1773fb

12
 LTC1773
U U W U
APPLICATIONS INFORMATION
PC Board Layout Checklist Design Example
When laying out the printed circuit board, the following As a design example, assume the LTC1773 is used in a
checklist should be used to ensure proper operation of the single lithium-ion battery powered cellular phone applica-
LTC1773. These items are also illustrated graphically in tion. The VIN will be operating from a maximum of 4.2V
the layout diagram of Figure 6. Check the following in your down to about 2.7V. The load current requirement is a
layout: maximum of 2A but most of the time it will be on standby
mode, requiring only 2mA. Efficiency at both low and high
1) Are the signal and power grounds segregated? The
load currents is important. Output voltage is 2.5V. With
LTC1773 signal ground consists of the resistive divider,
this information we can calculate RSENSE to be around
the compensation network and CSS. The power ground
consists of the (–) plate of CIN, the (–) plate of COUT, the 33mΩ. For the inductor L, using equation (1),
source of the external synchronous NMOS, and Pin 5 of
1 ⎛ V ⎞
the LTC1773. The power ground traces should be kept L= VOUT ⎜ 1 – OUT ⎟
short, direct and wide. Connect the synchronous
MOSFETs source directly to the input capacitor ground.
( )( )
f ∆IL ⎝ VIN ⎠ (3)

Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 800mA and

2) Does the VFB pin connect directly to the feedback
f = 550kHz in equation (3) gives:
resistors? The resistive divider of R1 and R2 must be
connected between the (+) plate of COUT and signal ground.
2.5V ⎛ 2.5V ⎞
Be careful locating the feedback resistors too far away L= ⎜1– ⎟ = 2.3µH
from the LTC1773. The VFB line should not be routed close 550kHz (800mA) ⎝ 4.2V ⎠
to any other nodes with high slew rates.
A 2.5µH inductor works well for this application. For good
3) Does the (+) terminal of CIN connect to VIN as closely as efficiency choose a 4A inductor with less than 0.1Ω series
possible? This capacitor provides the AC current to the resistance.
external power MOSFETs.
CIN will require an RMS current rating of at least 1A at
4) Keep the switching nodes SW, TG and BG away from temperature and COUT will require an ESR of less than
sensitive small-signal nodes, especially from the voltage 0.066Ω. In most applications, the requirements for these
and current sensing feedback pins. capacitors are fairly similar.
CC2

CC1 +
RC
1 10
ITH SW RSENSE
2 9 +
RUN/SS SENSE– CIN
D1 VIN
3 LTC1773 8
CSS
SYNC/FCB VIN Q1
R1 4 7
VFB TG Q2
5 6 –
GND BG
R2
–

BOLD LINES INDICATE COUT VOUT

HIGH CURRENT PATHS + L1

+
1773 F06

Figure 6. LTC1773 Layout Diagram

1773fb

13
LTC1773
U U W U
APPLICATIONS INFORMATION
For the selection of the external MOSFETs, the RDS(ON)
⎛V ⎞
must be guaranteed at 2.5V since the LTC1773 has to R2 = ⎜ OUT – 1⎟ R1 = 171k; use 169k
operate down to 2.7V. This requirement can be met by the ⎝ 0.8 ⎠
Si9801DY.
Figure 7 shows the complete circuit along with its effi-
For the feedback resistors, choose R1 = 80.6k. R2 can then ciency curve.
be calculated from equation (2) to be:

33pF
2.7V ≤ VIN ≤ 4.2V
200pF
30k 1 10
ITH SW RSENSE
0.033Ω
2 – 9
RUN/SS SENSE
LTC1773 VOUT
0.1µF 3 8 2.5V
VIN SYNC/FCB VIN L1 2A
2.5µH
4 7
VFB TG + CIN
5 6 150µF
GND BG 6.3V

Si9801DY
+ COUT
220µF
6.3V
169k
80.6k 1%
1%

CIN: SANYO POSCAP 6TPA150M

COUT: AVX TPSD227M006R0100 1773 F07a

L1: CDRH5D28
RSENSE: IRC LR1206-01-R033-F

Figure 7. Single Lithium-Ion to 2.5V/2A Regulator

Efficiency Curve for Figure 7

100
VOUT = 2.5V

95

VIN = 3.3V
90
EFFICIENCY (%)

85

80

75

70
1 10 100 1000 5000
OUTPUT CURRENT (mA)
1773 F1b

1773fb

14
 LTC1773
U
TYPICAL APPLICATIONS
33pF 2.7V ≤ VIN ≤ 8.4V

200pF LTC1773 MBR0530LT1

30k VOUT2
1 10
ITH SW RSENSE 5V
0.033Ω 100mA
2
RUN/SS SENSE–
9
L1
+ 22µF
5µH 6.2V
0.1µF 3 8
SYNC/FCB VIN 1:1
422k
4 7 VOUT1
VFB TG 2.5V + CIN
2A 100µF
5 6 10V
GND BG
80.6k
169k + COUT
1% Si9801DY 220µF
6.3V
80.6k
1%

CIN: SANYO POSCAP 10TPA100M L1: COILTRONICS CTX5-4/BH ELECTRONICS 511-0033 1773 TA01
COUT: AVX TPSD227M006R0100 RSENSE: IRC LR1206-01-R033-F

Figure 8. Dual Output 2.5V/2A and 5V/100mA Application

33pF
2.7V ≤ VIN ≤ 5.5V
200pF LTC1773
30k
1 10
ITH SW RSENSE
0.015Ω
2 9
RUN/SS SENSE–
Si9803DY VOUT
0.1µF 3 8 2.5V
VIN SYNC/FCB VIN L1 5A
2.8µH
4 7
VFB TG
Si9804DY
+ CIN
150µF
5 6
GND BG 6.3V

+ COUT
220µF
6.3V
169k ×3
80.6k 1%
1%

CIN: SANYO POSCAP 6TPA150M L1: TOKO D104C 919AS-2R8M

COUT: AVX TPSD227M006R0100 RSENSE: DALE WSL-2010 1773 TA02

Figure 9. Single Lithium-Ion to 2.5V/5A Regulator

Efficiency Curve for Figure 9

100

95
VIN = 3.3V
90
VIN = 5V
EFFICIENCY (%)

85

80

75

70

65

60
1 10 100 1000 10000
IOUT (mA)
1773 • G17

1773fb

15
LTC1773
U
TYPICAL APPLICATIONS
33pF
2.7V ≤ VIN ≤ 4.2V
200pF LTC1773
30k
1 10
ITH SW RSENSE
0.025Ω
2 – 9
RUN/SS SENSE
Si9803DY VOUT
0.1µF 3 8 3.3V
VIN SYNC/FCB VIN L1
47µF 1A
2µH
4 7
VFB TG + CIN
+ 150µF
5 6 Si9804DY
GND BG 6.3V

+ COUT
220µF
249k 6.3V
80.6k 1% L1
1% 2µH

CIN: SANYO POSCAP 6TPA150M

COUT: AVX TPSD227M006R0100 1773 TA03

L1: COILTRONICS CTX2-4/BH ELECTRONICS 511-1010

RSENSE: IRC LR1206-01-R033-F

Figure 10. Single Lithium-Ion to 3.3V/1A Synchronous Zeta Converter

Efficiency Curve for Figure 10

100
VOUT = 3.3V VIN = 5V
90 VIN = 4V

80
VIN = 3.3V
EFFICIENCY (%)

70 VIN = 2.7V
60

50

40

30

20
0.001 0.01 0.1 1.0
OUTPUT CURRENT (A)
1773 G18

1773fb

16
 LTC1773
U
TYPICAL APPLICATIONS
2.7V ≤ VIN ≤ 4.2V
47pF
30k LTC1773
1 10
ITH SW RSENSE
0.05Ω
220pF 2 – 9
RUN/SS SENSE
VOUT
750kHz CLK 0.1µF 3 8 2.5V
SYNC/FCB VIN L1 1A + CIN
3µH 47µF
4 7 6.3V
VFB TG
100pF 5 6
GND BG
4.7µF
169k 6.3V
Si6803DQ
1%

100pF + COUT
80.6k 0.1µF 47µF
1% 6.3V

CIN, COUT: SANYO POSCAP 6TPA47M

L1: SUMIDA CDRH5D28 3R0 1773 TA06

RSENSE: IRC LR1206-01-R050-J

Figure 11. 750kHz Single Lithium-Ion to 2.5V/1A Regulator

VOUT3
2.5V
150mA
LT1762-2.5
8 1
IN OUT
2
1µF SENSE 10µF

0.01µF
5 3
SHDN BYP VOUT1
1.8V
GND 6A
VOUT2
3.3V
47pF 1A

3.3V ≤ VIN ≤ 6V
220pF LTC1773
30k
1 10 MBRM120T3
ITH SW RSENSE
0.01Ω
2 9
RUN/SS SENSE– + CSEC
47µF
0.1µF 3 8
SYNC/FCB VIN 6.3V + CIN
150µF
4 7 6.3V
VFB TG
T1 249k
100pF 5 6 2.44µH 1%
GND BG
1:1
100k 0.1µF 80.6k
Si7540DP
1% 1%
COUT
100pF
D2*
+ 680µF
80.6k
1% MBRS340T3 4V
×2

1773 TA07
CIN: PANASONIC SPECIAL POLYMER
COUT: KEMET T510687K004AS
*NOTE: D2 NOT NECESSARY.
T1: BH ELECTRONICS 510-1007
IF REMOVED, EFFICIENCY DROPS BY 1%
RSENSE: IRC LR2512-01-R010-J
CSEC: TAIYO YUDEN LMK432F476ZM

Figure 12. Triple Output 1.8V/6A, 2.5V/150mA,and 3.3V/1A Application

1773fb

17
LTC1773
U
TYPICAL APPLICATIONS

2.7V ≤ VIN ≤ 6V
47pF
30k LTC1773
1 10
ITH SW RSENSE
D1
0.068Ω
220pF 2 9 MMSD914T1
RUN/SS SENSE–
VOUT
0.1µF 3 8 2V
SYNC/FCB VIN L1 800mA + CIN
4.2µH 47µF
4 7 6.3V
VFB TG
100pF 5 6
GND BG
4.7µF
118k 6.3V
Si9801DY
1%

100pF
D2*
+ COUT
80.6k 0.1µF 47µF
1% MBR0530LT1 6.3V

CIN, COUT: SANYO POSCAP 6TPA47M *NOTE: D2 NOT NECESSARY.

L1: SUMIDA CDRH5D28 4R2 IF REMOVED, EFFICIENCY DROPS BY 1% 1773 TA05

RSENSE: IRC LR1206-01-R068-F

Figure 13. Single Lithium-Ion to 2V/800mA Regulator with

Current Foldback

2.7V ≤ VIN ≤ 6V
47pF
30k LTC1773
1 10
ITH SW RSENSE
0.01Ω
220pF 2 9
RUN/SS SENSE–
VOUT
0.1µF 3 8 1.8V
SYNC/FCB VIN L1 7A
+ CIN
1µH 150µF
4 7 6.3V
VFB TG
100pF 5 6
GND BG
4.7µF
100k 6.3V
0.1µF Si7540DP
1%
COUT
100pF + 680µF
80.6k D2*
1% 4V
MBRS340T3 ×2
CIN: PANASONIC SPECIAL POLYMER *NOTE: D2 NOT NECESSARY.
COUT: KEMET T510687K004AS IF REMOVED, EFFICIENCY DROPS BY 1% 1773 TA08

L1: TOKO TYPE D104C 919AS-1RON

RSENSE: IRC LR2512-01-R010-J

Figure 14. 3.3V to 1.8V/7A Regulator

1773fb

18
 LTC1773
U
TYPICAL APPLICATIONS
33pF
4.5V ≤ VIN ≤ 5.5V
200pF LTC1773
30k
1 10
ITH SW RSENSE
0.04Ω
2 – 9
RUN/SS SENSE
VOUT
0.1µF 3 8 1.8V
VIN SYNC/FCB VIN L1 2A
2.5µH
4 7
VFB TG CIN
47µF
5 6
GND BG 10V

COUT
Si9942DY 47µF
10V
100k
80.6k 1%
1%

CIN, COUT: TAIYO YUDEN LMK550BJ476MM

L1: CDRH5D28 1773 TA09

RSENSE: IRC LR1206-01-R040-F

Figure 15. 5V to 1.8V/2A Regulator with Ceramic Capacitors

U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)

0.889 ± 0.127
(.035 ± .005)

5.23
(.206) 3.20 – 3.45
(.126 – .136) 3.00 ± 0.102
MIN
(.118 ± .004) 0.497 ± 0.076
(NOTE 3) (.0196 ± .003)
10 9 8 7 6
REF
0.305 ± 0.038 0.50
(.0120 ± .0015) (.0197)
TYP BSC
4.90 ± 0.152 3.00 ± 0.102
RECOMMENDED SOLDER PAD LAYOUT
(.193 ± .006) (.118 ± .004)
(NOTE 4)

DETAIL “A”
0.254
(.010)
0° – 6° TYP 1 2 3 4 5
GAUGE PLANE
1.10 0.86
(.043) (.034)
0.53 ± 0.152 MAX REF
(.021 ± .006)
DETAIL “A”
SEATING
0.18
PLANE
(.007) 0.17 – 0.27 0.127 ± 0.076
(.007 – .011) (.005 ± .003)
0.50
TYP MSOP (MS) 0603
(.0197)
BSC

NOTE: 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

1. DIMENSIONS IN MILLIMETER/(INCH) INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
2. DRAWING NOT TO SCALE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

1773fb

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1773
U
TYPICAL APPLICATIO

33pF 4.5V ≤ VIN ≤ 5.5V

200pF
30k
1
LTC1773
10 RSENSE
VOUT2 + CIN
ITH SW 3.3V 150µF
0.050Ω 500mA 6.3V
2 9
RUN/SS SENSE– L1 + COUT2
10µH Si2302DS 150µF
0.1µF 3 8 3:1
VIN SYNC/FCB VIN 6.3V
4 7 VOUT1
VFB TG 2.5V
1A
5 6 D1
GND BG
+ COUT1
Si6801DY 47k 150µF
6.3V
40.2k 169k
1% 1% 249k
1% 0.1µF

CIN, COUT1, COUT2: SANYO POSCAP 6TPA150M

1773 TA04
RSENSE: IRC LR1206-01-R050-F
D1: BAS16

Figure 16. Dual Output Synchronous Buck Converter

RELATED PARTS
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LTC1735-1 High Efficiency Synchronous Step-Down Switching Controller Output Fault Protection 16-Pin GN, Burst Mode Operation,
Power Good
LTC1771 Low Quiescent Current Step-Down DC/DC Controller VIN: 2.8V to 18V, 10µA IQ, MS8 Package
LTC1772/B SOT-23 Low Voltage Step-Down Controller 6-Pin SOT-23, 2V ≤ VIN ≤ 10V, 550kHz
LTC1778 Wide Operating Range/Step-Down Controller, No RSENSE VIN up to 36V, Current Mode, Power Good
LTC1779 SOT-23 Current Mode Step-Down Converter 250mA Output Current, 2.5V ≤ VIN ≤ 9.8V, Up to 94% Efficiency
LTC1877 High Efficiency Monolithic Synchronous Step-Down Regulator VIN from 2.65V to 10V, 10µA IQ, 550kHz, IOUT to 600mA,MS8
LTC1878 High Efficiency Monolithic Synchronous Step-Down Regulator VIN from 2.65V to 7V, 10µA IQ, 550kHz, IOUT to 600mA,MS8
LTC3404 1.4MHz Monolithic Synchronous Step-Down Regulator Up to 95% Efficiency, IOUT = 600mA at VIN = 3.3V
No Schottky Diode Required, 8-Lead MSOP

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LT 1106 REV B • PRINTED IN USA
Linear Technology Corporation
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