Module 4:
CMOS Fabrication and Layout
Outline
CMOS Process Technology N-well, P-well process
Stick diagram for Boolean functions using Euler Theorem
Layout Design Rule
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Fabrication
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
Oxidation
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
SiO2
p substrate
n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implantation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps
n well
p substrate
N-well fabrication steps
Start with blank wafer
Build inverter from the
bottom up
First step will be to form
the n-well
Cover wafer with
protective layer of SiO2
(oxide)
Remove layer where n-
well should be built
Implant or diffuse n
dopants into exposed
wafer
Strip off SiO2
Polysilicon
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon
layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon Patterning
Use same lithography process to pattern
polysilicon
Self-Aligned Process
Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-
well contact
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
N-diffusion cont.
Strip off oxide to complete patterning step
P-Diffusion
Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Polysilicon and n-diffusion
P-Diffusion, Contacts and Metal
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
Layout Design Rules
Two metal layers in an n-well process:
Layout Design Rules
Layout Design Rules
Layout Design Rules
Conservative rules to get you started
Inverter Cell Layout
This style consists of four horizontal strips:
Metal ground at the bottom of the cell, n-
diffusion, p-diffusion, and metal power at
the top.
The power and ground lines are often
called supply rails.
Polysilicon lines run vertically to form
transistor gates.
P-substrate and n-well must be tied to
ground and power, respectively.
3-input NAND Cell Layout
Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
Stick Diagram of NOR Gate
Stick Diagrams: Euler Theorem
The node number 1, 2, 3, 4…etc. which you see encircled with yellow are called
vertices and the gate inputs which labels the connections between the vertices
are called edges
Ref: https://www.vlsisystemdesign.com/art-of-layout-eulers-path-and-stick-diagram-part-3/
Stick Diagrams: Euler Theorem
Trace a path in both nmos and pmos network, in such a fashion that each edge is
traversed only once and note the edges.
Ref: https://www.vlsisystemdesign.com/art-of-layout-eulers-path-and-stick-diagram-part-3/
Stick Diagrams: Euler Theorem
Ref: https://www.vlsisystemdesign.com/art-of-layout-eulers-path-and-stick-diagram-part-3/
Stick Diagrams: Euler Theorem
Ref: https://www.vlsisystemdesign.com/art-of-layout-eulers-path-and-stick-diagram-part-3/
Stick Diagrams: Euler Theorem
Ref: https://www.vlsisystemdesign.com/art-of-layout-eulers-path-and-stick-diagram-part-3/
