VESTEL STB

SERVICE MANUAL
SATELLITE STB
MODEL

DVB 530
DVB 630
DVB 710
DVB 710 CI
Schematic Version PCB 16 MB04E3
Artwork Version 1.0
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SATELLITE STB MODELS

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TOC \O "1-2" SATELLITE STB MODELS 2

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28 LDER (128K01)
40005188
R3
RES SMD 1/16W 220R J (0603)
30012868

IC6
IC TS87C52X2-MCB tape&reel
300143429R30
RES SMD 1/16W 10K J
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551002 \H 31
UPLOAD DEFAULT SAT_XPDRS : ............................................................................................................................................... 31
DOWNLOAD DEFAULT SAT_XPDRS : ......................................................................................................................................... 31
RS232 TEST :............................................................................................................................................................................. 32
SOFTWARE UPGRADE THROUGH RS232 ......................................................................................................................... 33
SCHEMATICS .............................................................................................................................................................................. 33
16PW04-5 POWER BOARD SCHEMATIC ........................................................................................................................... 34
16MB04-E3 MAINBOARD SCHEMATIC I........................................................................................................................... 34
16MB04-E3 MAINBOARD SCHEMATIC II ......................................................................................................................... 34
16MB04-E3 MAINBOARD SCHEMATIC III ........................................................................................................................ 34
16MB04-E3 MAINBOARD SCHEMATIC IV........................................................................................................................ 34
16MB04-E3 MAINBOARD SCHEMATIC V ...................................................................ERROR! BOOKMARK NOT DEFINED.
16MB04-E3 MAINBOARD SCHEMATIC VI........................................................................................................................ 34
16FP0X-X FRONT BOARD SCHEMATIC ............................................................................................................................ 34
16SC04-4 SCART SCHEMATIC ...................................................................................... ERROR! BOOKMARK NOT DEFINED.
16UK04-1 REMOTE BOARD SCHEMATIC ......................................................................................................................... 34
BILL OF MATERIALS .................................................................................................................................................................. 35
BOARD LAYOUT ........................................................................................................................................................................ 72
16PW04-5 COMPONENT LAYER:............................................................................................................................................... 72
16PW04-5 BOTTOM LAYER: ..................................................................................................................................................... 72
16MB04-E3 TOP LAYER: .......................................................................................................................................................... 72
16MB04-E3 COMPONENT LAYER: ............................................................................................................................................ 72
16MB04-E3 GND LAYER:........................................................................................................................................................ 72
16MB04-E3 VCC LAYER: ........................................................................................................................................................ 73
16MB04-E3 BOTTOM LAYER:................................................................................................................................................... 73
16FP05-2 COMPONENT LAYER: ................................................................................................................................................ 73
16FP05-2 BOTTOM LAYER:....................................................................................................................................................... 73
16FP06-2 COMPONENT LAYER: ................................................................................................................................................ 73
16FP06-2 BOTTOM LAYER:....................................................................................................................................................... 73
16FP07-4 COMPONENT LAYER: ................................................................................................................................................ 73
16FP07-4 BOTTOM LAYER:....................................................................................................................................................... 73
16SC04-4 COMPONENT LAYER:................................................................................................................................................ 73
16SC04-4 BOTTOM LAYER: ...................................................................................................................................................... 73
16FP04-4 BOTTOM LAYER:.................................................................................................ERROR! BOOKMARK NOT DEFINED.
16UV04-1 TOP LAYER:............................................................................................................................................................. 73
16UV04-1 BOTTOM LAYER: ..................................................................................................................................................... 74
16UV04-1 SOLDER LAYER:....................................................................................................................................................... 74

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REVISION HISTORY
Rev 1.0 02/08/02 Cumhur AKIN Initial Revision
Schematics

GENERAL DESCRIPTION
Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the
document.

STi5512 (IC2)
1. Introduction
The STi5512 is the latest in the OMEGA family of integrated multimedia decoder engines for DVB set top
box systems. Compared to the STi5510, it has an enhanced External Memory Interface which supports SDRAM,
without the need for glue logic. The device has increased performance with a 60MHz CPU clock, a digital YCrCb
output, support for Genlock, and new display modes. The STi5512 can also be used as a replacement part for the
STi5510 as it has the same architecture and is pin-compatible, however, some software modifications are required.
STi5512 mode is selected by setting pin YC0 low, and STi5510 mode is selected by setting pin YC0 high.
The STi5512 is available with any combination of ICAM and Macrovision options, and different part
numbers are used to identify the options as described in the section below. Throughout this manual, where the
information is generic to all Macrovision and ICAM options, the device is referred to as the STi5512 only.
Macrovision/ICAM option Package type ( W=BGA) Functional revision

2. Technical Specification
High performance graphics system
• High resolution chroma mode (4:4:4) for RGB output
• 2 to 8 bits per pixel OSD options
• Link list control
• 4-bit mixing factor by region or 6-bit mixing for each CLUT entry (anti-aliasing)
• 8-bit Y, U and V resolution palette
• Extra YUV plane for background images or graphics
• 2D, paced BLT engine with “fill” function
• Anti-flicker and anti-flutter filters
Enhanced 32-bit VL-RISC CPU - 60 MHz clock
• Fast integer/bit operation and very high code density
High-performance memory/cache subsystem
• 2 Kbytes instruction cache, 2 Kbytes data cache or SRAM, 4 Kbytes SRAM
• 200 Mbytes/s maximum bandwidth
Combined video and audio decoder core
• Video decoder fully supports MPEG-2 MP@ML. Letter box (16:9 and 14:9), 2:1, 3:1 and 4:1 downsizing
• Memory reduction - PAL MP@ML in 12 Mbits
• Audio decoder supports layers 1 and 2 of MPEG 1,and an AC-3 interface to an external decoder
• Digital YCrCb output in 4:2:2 format
PAL/NTSC/SECAM encoder
• MacrovisionTM 7.01, teletext and closed caption
• Outputs RGB with 10-bit DACs and CVBS, Y, C and component output (YUV) with 10-bit DACS
• Separate OSD control for RGB and CVBS outputs
• Genlock support
High performance SDRAM memory interface
• Supports two 16- or one 64-Mbit 100 MHz SDRAMs
• Accessible by MPEG decoder, PTI, DMAs and CPU

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• High bandwidth access from CPU allows high performance OSD operations
Programmable external memory interface (EMI)
• Glueless interface to SDRAM
Programmable transport interface
• Parallel or serial input
• Supports DVB bit-streams
• More than 32 PIDs supported
• DVB descrambler
• 32 SI/PSI filters of 8 bytes
Vectored interrupts - 8 prioritized levels
Interfaces and DMA engines
• 2 SmartCard interfaces, 2 UARTs, 2 I2C/SPI controllers, 3 PWM outputs, 4 timers, 3 capture timers
• Block move DMA
• Teletext interface, input from external source
• IEEE1284 port, or IEEE1394 A/V link layer interface
Low power controller/real time clock/watchdog
JTAG test access port
Professional toolset support
• ANSI C compiler and libraries
• Advanced debugging tools
Non-intrusive debug controller
• Hardware breakpoints
• Real-time trace

3. Architecture overview
The STi5512 includes the following hardware modules:
• Transport demultiplexor
• System microcontroller
• MPEG video decoder
• MPEG audio decoder
• PAL/NTSC/SECAM encoder
The STi5512 directly interfaces to external memory and peripherals with no extra glue logic, keeping the system
cost to a minimum. The STi5512 architectural block diagram is shown below.

4. STi5512 functional modules

These modules are outlined below.

a. Processor
The Central Processing Unit (CPU) on the STi5512 is the ST20-C2 32-bit processor core running at the CPU clock
rate. It contains instruction processing logic, instruction and data pointers and an operand register. It directly
accesses the high speed on-chip caches and SRAM, which can store data or programs. The processor can also
access memory via the External Memory Interface (EMI) and SDRAM interface.

b. MPEG-2 video and MPEG-1 audio decoder subsystems

This subsystem takes the MPEG compressed data streams and decompresses them, outputting digital YUV data in
the case of the video decoder, and stereo PCM samples in the case of the audio decoder. The decoded video is fed
to the display subsystem. An interface is provided to output an audio bit-stream for decoding by an external MPEG
or AC-3 decoder to support multi-channel (surround) audio.
The video decoder implemented on the STi5512 uses a patented memory reduction/bandwidth reduction scheme to
offer the user the best compromise between bandwidth and memory size. The algorithm is lossless and uses “on-
thefly” decoding to reduce the memory requirements to two frame buffers in memory size reduction mode. When
used in bandwidth reduction mode, the memory usage is the normal three buffers, but the bandwidth required by
the decoder is significantly reduced over a classical implementation.

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The SDRAM interface includes all the signals necessary for control of the memory. Refresh is handled automatically
by the decoder. The SDRAM interface supports two 16-Mbit or one 64-Mbit 100 MHz SDRAMs. The memory is
used to hold the bit buffer, store decoded pictures and provide the display buffer. It also holds the user-defined on-
screen display (OSD) bitmaps and can be used by the CPU for private storage of data. For the decoding of PAL
MP@ML sequences, 12 Mbits of SDRAM are required.

c. Graphics and display subsystem

The display unit is part of the MPEG video decoder. It can overlay several display planes.
It takes the decompressed MPEG video data and performs the following functions:
• Optionally perform horizontal resampling of both luminance and chrominance data
• Reconstruct vertical data to create 4:2:2 sample format
• Generate on-screen display bit map for superposition onto picture output
• Allow sub-picture decoder output to be mixed onto picture output
• Optionally perform anti-flicker and anti-flutter filtering
• Optionally perform vertical resampling of both luminance and chrominance data
• Still picture plane with graphics capability
• 2D block move to copy rectangular sections of the display
• 4:4:4 chroma resolution for RGB output.
• 4:2:2 chroma resolution for CVBS output
• Separate control on OSD between CVBS and YC on one hand and RGB and YUV on the other
The sub-picture decoder can also be used as a hardware cursor unit. The priority of the sub-picture is first raised by
programming a register so it is above all the other display planes. A cursor can be defined using an optionally
compressed (run-length encoded) bitmap stored in external SDRAM. The bitmap can be any size up to a full
screen. Per-pixel alpha-blending factors can be defined for each cursor to provide anti-aliasing with the background.
The cursor is then moved around using register writes into X and Y coordinate registers.The digital video data is fed
to the PAL/NTSC/SECAM encoder subsystem.

d. PAL/NTSC/SECAM encoder
Integrated into this subsystem is all the digital processing and the digital to analog convertors required to process
the digital video output from the MPEG video decoder and produce RGB, YUV, YC and CVBS analog outputs. The
output of the teletext interface is filtered and re-inserted into the blanking interval in this subsystem.

e. Programmable Transport Interface

The transport demultiplexing function is performed in a programmable hardware module, the programmable
transport interface (PTI). Its operation is as described below. The input interface may select between either a LinkIC
stream or an IEEE 1394 controller as the source for the transport stream. Data packets from the input interface are
input into a FIFO while the PID is checked to see if it is currently selected for processing or is to be discarded. A
selected packet is parsed by the module to determine its type and to extract data from it. If the packet is encrypted
using the DVB Standard the correct key is written into the DVB decryption core in the transport module and the
packet is decrypted. After parsing and descrambling the packet, the data is either transferred to buffers in external
memory or directly to the MPEG audio and video decoders. If the audio and video data is buffered then the data can
be transferred by DMA from the buffer to the MPEG decoders.
DVB standard sections are filtered by a set from 32 possible 8-byte filters to look for a match. Matching sections are
then transferred to memory buffers for processing by software. Error conditions, system time clock recovery, and
control of the hardware module are handled by software running on the ST20.

f. Memory subsystem
The STi5512 on-chip memory system provides 200 Mbytes/s internal data bandwidth, supporting pipelined 2-cycle
internal memory access at 20 ns cycle times at 60 MHz. The STi5512 memory subsystem consists of instruction
and data caches, SRAM and an external memory interface (EMI). The STi5512 product has 4 Kbytes of on-chip
SRAM. The advantage of this is the ability to store on-chip any timecritical code, such as interrupt routines, software
kernels or device drivers, and even frequently used data. The instruction and data caches are direct mapped with a
write-back system for the data cache. The caches support burst accesses to the external memories for refill and
write-back which are effective for increasing performance with page-mode DRAM memories. The data cache may

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also be configured as an additional 2 Kbytes of internal SRAM. The STi5512 EMI controls access to the external
memory and peripherals including the DMA data ports. It can access a 16 Mbyte physical address space in each of
the three memory banks, or greater if DRAM is used. It provides sustained transfer rates of up to 80 Mbytes/s for
SRAM, and up to 40 Mbytes/s using page-mode DRAM. The 32-bit programmable EMI supports ROM, SRAM and
DRAM/SDRAM for the ST20. SDRAM is supported at the CPU clock rate. The STi5512 supports boot bank width
ROM/Flash population options using the address shift mechanism. The SDRAM interface supports the use of two
16 Mbits or one 64 Mbits of external 100 MHz SDRAM. This memory is used to store the display data generated by
the MPEG decoder and the CPU and read by the display unit.

g. Interrupt subsystem
The STi5512 interrupt subsystem supports eight prioritized interrupt levels. Four external interrupt pins are
provided. Level assignment logic allows any of the internal or external interrupts to be assigned to any interrupt
level. Interrupt level sharing is supported for level-sensitive interrupts.

h. Serial communications
To facilitate the connection of this system to a modem for a pay-per-view type system and other peripherals, two
UARTs (ASC2s) are included in the device. The UARTs provide an asynchronous serial interface and can be
programmed to support a range of baud rates and data formats, for example, data size, stop bits and parity. The
UARTs are buffered with 16 byte FIFOs for transmit and receive data. Two synchronous serial communications
(SSC2) interfaces are provided on the device. These can be used to control, via an I2C or SPI bus, the tuner, Link-
IC, E2PROM (if used) and the remote control devices in the application.

ı. Block move engine

High performance block data transfer can be performed as a memory to memory DMA operation using the block
move module.

k. PWM and counter module

This module includes three separate pulse width modulator (PWM) generators using a shared counter, plus four
timercompare and three capture channels sharing a second counter. The counters can be clocked from a pre-
scaled clock, using the 27 MHz ClockIn for the PWM counter and the system clock for the capture/compare
counter. The event on which the timer value is captured is also programmable. The PWM counter is 8-bit with 8-bit
registers to set the output high time. The capture/compare counter and the compare and capture registers are 32-
bit.

l. Parallel IO module
Forty bits of parallel IO are provided. Each bit is programmable as an output or an input. The output can be
configured as a totem pole or open drain driver. Input compare logic is provided which can generate an interrupt on
any change of any input bit. Many pins of the STi5512 device are multi-functional, and can either be configured as
PIO or connected to an internal peripheral signal such as a UART or SSC.

m. Teletext
The teletext connects to the internal digital encoder using a request and data protocol. It translates teletext data to
and from memory. It has two modes of operation; teletext data in and teletext data out. In teletext data out mode,
the teletext interface uses DMA to retrieve teletext data from memory, and serializes the data for transmission to the
composite video encoder. In teletext data in mode, teletext data is extracted from the composite video signal and is
fed into the teletext interface as a serial stream. The teletext interface assembles the data and uses DMA to pass
this data to memory.

n. Diagnostic controller
The Diagnostic Controller Unit (DCU) is accessed via the JTAG test access port. It is the main access for
communication with a host for development, including loading code and debugging. It provides:
• Bootstrapping and debugging during development
• Hardware breakpoint and watchpoint facilities
• Real-time tracing
• External LSA triggering support

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5. Pin list
Signal names are prefixed by not if they are active low; otherwise they are active high.

Pin Number Function

VDD 13 Power supply
GND 16 Ground
Vclamp1-3 3 Power supply for clamp diodes
VDDA0-1 2 Analog power supply for PAL/NTSC/SECAM encoder
VSSA0-1 2 Analog ground for PAL/NTSC/SECAM encoder
RTCVDD 1 Real time clock supply
VDD_VPLL 1 Analog power supply for video PLL
VSS_VPLL 1 Analog ground for video PLL
Table 1 Power supply pins

Pin In/Out Function

R_OUT Out Red output
G_OUT out Out Green output
B_OUT out Out Blue output
C_OUT out Out Chroma output
CV_OUT out Out Composite video output
Y_OUT out Out Luma output
I_REF_DAC_RGB In DAC current reference
I_REF_DAC_YCC In DAC current reference
V_REF_DAC_RGB In DAC voltage reference
V_REF_DAC_YCC In DAC voltage reference
OSD_ENABLE In/out OSD enable
NotHSYNC In/out Horizontal sync
ODD_OR_EVEN in/out Vertical sync
YC0-71 Output Digital YUV output
CFC Input DENC color burst phase and frequency control. This pin can be
used in non-scart based Genlock applications
Table 2 Video output interface pins

1 This pin is tri-stated during reset and then sampled at the end of the reset to determine whether the OS-Link is active and
to determine the function of the shared CPUAnalyse / TrigIn and the ErrorOut / TrigOut, as described in the System
Services chapter. If the ErrorOut pin is sampled high (i.e at VDD) then the DCU signals (TrigIn and TrigOut) are
selected and a low value indicates OS-Link signals (i.e. CPUAnalyse, ErrorOut) are to be used. External 10KΩ pull-up
or pull-down resistors should be fitted to the ErrorOut according to the functionality desired.

Pin In/Out Function

SCLK/A_C_STB out Serial clock or AC-3 data strobe
PCM_DATA/A_C_DATA out PCM data out or AC-3 data out
PCMCLK in/out PCM clock
LRCLK/A-WORD_CLK out Left/right clock or AC-3 word clock
A_C_REQ in AC-3 data request
A_PTS_STB In AC-3 audio PTS strobe
Table 5 AC-3/MPEG1 audio output interface pins

Table 6 External interrupt pins

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Table 7 System services pins

Table 8 STi5512 External memory interface pins

notMemRAS2 out RAS strobe for SDRAM/DRAM in bank 1, chip select for Bank1 or RAS strobe for lowest DRAM sub-bank in
Bank1. notMemRAS3 out RAS strobe for highest DRAM sub-bank in Bank1 or SDRAM Chip select signal for Bank1
notSDRAMCS0 out SDRAM Chip select signal for Bank0 or lowest sub-bank of Bank0

Table 9 Shared SDRAM interface pins

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Table 10 Low power controller and real time clock pins

Table 11 PIO pins

Table 12 OS-Link pins

Pin In/Out Function

TSInByteClk In Link IC byte clock
TSInByteClkValid In Link IC byte clock valid edge
TSInData0-7 In Link IC data
TSInError In Link IC packet error
TSInPacketClk In Link IC packet strobe
Table 13 Transport stream input pins

Table 14 Teletext interface

The teletext clock and data inputs are shared PIO pins, as shown in Table 17 High speed data port pins have a dual
function, and can be used either to interface to an external IEEE 1394 link layer controller or provide an IEEE 1284
parallel port interface.

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Table 15 High speed data port pins

Table 16 TAP pins

Table 17 Alternative function of PIO pins

SDRAM 8MByte (IC201, IC202)

FEATURES
• PC66-, PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/ precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO

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PRECHARGE, and Auto Refresh Modes

• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply

GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is
internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive
edge of the clock signal, CLK). Each of the x4’s 16,777,216 -bit banks is organized as 4,096 rows by 1,024 columns by 4
bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s
16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE
command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-
speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access
operation. The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is
provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM’s offer
substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate
with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time
and the capability to randomly change column addresses on each clock cycle during a burst access.

Flash Memory 1 MByte (IC203, IC204)

Low Voltage Single Supply Flash Memory

2.7V to 3.6V SUPPLY VOLTAGEfor

PROGRAM, ERASE and READ OPERATIONS
FASTACCESS TIME: 90ns
FASTPROGRAMMING TIME
– 10µs by Byte / 20µs by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-byand AutomaticStand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARSDATARETENTION

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– Defectivity below 1ppm/year

ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code, M29W800T: 00D7h
– Device Code, M29W800B: 005Bh

DESCRIPTION
The M29W800 is a non-volatile memory that may be erased electrically at the block or chip level and programmed
in-system ona Byte-by-Byteor Wordby-Word basis using only a single 2.7V to 3.6V VCC supply. For Program and
Erase operations the necessary high voltages are generated internally. The device can also be programmed in
standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without
affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and
temporarily unprotected to make changes in the application. Each block can be programmed and erased over
100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection
status, Programming, Blockand Chip Erase, Erase Suspend and Resume are written to the device in cycles of
commands to a Command Interface using standard microprocessor write timings. The device is offered in
TSOP48(12 x 20mm) and SO44 packages. Both normal and reverse pinouts are available for the TSOP48package.

Organisation
TheM29W800 is organised as 1 Mx8 or 512K x16 bits selectable by the BYTE signal. When BYTEis Low the Byte-
wide x8 organisation is selected and the address lines are DQ15A–1 and A0-A18. The Data Input/Output signal
DQ15A–1 acts as address line A–1 which selects the lower or upper Byte of the memory word for output on DQ0-
DQ7,DQ8-DQ14 remain at High impedance. When BYTEis High the memory uses the address inputs A0-A18 and
the Data Input/Outputs DQ0-DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write
EnableW inputs. AReset/Block Temporary Unprotection RPtri-level input provides a hardware reset when pulled
Low,and when held High (atVID) temporarily unprotects blocks previously protected allowing them to be programed
and erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status
Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.

Memory Blocks
The devices feature asymmetrically blocked architecture providing system memory integration. Both M29W800Tand
M29W800Bdeviceshavean array of 19 blocks, one Boot Block of 16 KBytes or 8KWords, two Parameter Blocks of 8
KBytes or 4KWords, one Main Block of 32 KBytes or 16KWordsand fifteen Main Blocks of 64 KBytes or 32KWords.
The M29W800Thas the Boot Block at the top of the memory address space and the M29W800B locates the Boot
Block starting at the bottom. The memory maps are showed in Figure3. Each block can be erased separately, any
combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or
program to any block not being ersased, and then resumed. Block protection provides additional data security. Each
block can be separately protected or unprotected against Program or Erase on programming equipment. All
previously protected blocks can be temporarily unprotected in the application.

Bus Operations
The following operations can be performed using the appropriate bus cycles: Read(Array, Electronic Signature,
Block Protection Status), Write command, Output Disable, Standby, Reset, Block Protection, Unprotection,
Protection Verify, Unprotection Verify and Block Temporary Unprotection.

Command Interface
Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a
Command Interface (C.I.). For added data protection, program or erase execution starts after4 or 6 cycles. The first,
second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all
Program/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable, are given on the
third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to
Read Array mode.

Instructions

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Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block
Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C.
automatically handles all timing and verification of the Program and Erase operations. The Status Register Data
Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor
the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded
sequence to the Command Interface which is common to all instructions The third cycle inputs the instruction set-
up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for
Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase
require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data
to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded
sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in
order to read data from another block or to program data in another block, and then resumed. When power is first
applied or if VCC falls below VLKO, the command interface is reset to Read Array.

EEPROMs 128K (16,384 x 8) 2-wire Serial (IC205)

Features
• Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 16,384 x 8 and 32,768 x 8
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: > 4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-pin JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 14-lead TSSOP, and
8-pad Leadless Array Packages

Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only
memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up to
four devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-
pin JEDEC PDIP, 8-lead EIAJ, 8-lead JEDEC SOIC, 14-lead TSSOP, and 8-pad LAP packages. In addition, the
entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-O Red with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not
connected for hardware compatibility with AT24C32/64. When the pins are hardwired, as many as four 128K/256K
devices may be addressed on a single bus system (device addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the default A1 and A0 are zero.

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WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is
tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to
GND. Switching WP to VCC prior to a write operation creates a software write protect function.

Memory Organization
AT24C128/256, 128K/256K SERIAL EEPROM: The128K/256K is internally organized as 256/512 pages of 64-
bytes each. Random word addressing requires a 14/15-bit data word address.

Absolute Maximum Ratings

Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA

I2C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control
(IC301)
Description
The Sony CXA2161R is an Audio/Video switch designed primarily for application in Digital Set Top Boxes. It
provides video and audio routing from the digital encoder source to the TV and VCR scart (peritelevision)
connectors. In addition, the TV audio output has a programmable volume control. The chip is programmed by
means of an I2C interface and can operate from a single or dual power supply. Target specifications: Canal+,
BSkyB, TPS, NorDig, and ECCA Euro-Box

Features
Supply
• Single: 0V, +5V, +12V
• Dual: 0V, –5V, +5V and +12V
(Low number of external parts required)
Video
• 2 scart switching (VCR, TV)
• VCR input supports RGB mode
• Integrated 75 drivers for direct video connection
• Y/C mixer with trap for RF modulators
• Switchable clamps on inputs
• Adjustable gain on RGB outputs
• Video output shutdown for low power modes
• Fast blanking switch
• Slow blanking switch for TV and VCR output
• SVHS switch on VCR output
• Y/C auxiliary input
Audio
• Four stereo audio inputs
• Volume control (–56dB to +6dB in 2dB steps)
• Additional switchable gain on audio DAC inputs
• Audio overlay facility
• Volume bypass for TV and Phono outputs
• Mono switching on TV, VCR outputs
• High drive capability (600 loads possible)
• Switchable audio limiter function
• Switchable Mono output for RF modulators

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I2C and Logic

• Fast mode compatible I2C bus
• Function monitor with loop through
• Interrupt output for function monitor
• Logic output pin
• Sync detector for Y/CVBS inputs
Applications
• Digital Set Top Box
• Integrated digital television
Structure
Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C) unless stated

• Supply voltage VCC 14 V
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 1.1 W (when mounted on the board)
Operating Conditions
• Single supply 12 ± 0.6 V 5 ± 0.25 V
• Dual supply –5 ± 0.25 V 5 ± 0.25 V 12 ± 0.6 V
• Operating temperature Topr –20 to +75 °C
56 pin LQFP (Plastic)

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Tuner Alps (TU501)

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USED IC LISTS

MAINBOARD (16MB04 VER E3)

MAX 232 (IC1) RS232 Driver/Receiver

Sti5512AWE (IC2) Set Top Box Backend Decoder With Integrated Host Processor

TSH 22 (IC3) Dual Bipolar Operational Amplifier

M74HCU04 (IC4) Hex Inverter

MT48LC4M16A2 (IC201,IC202) 1 Mbyte x 16 x 4 banks SDRAM

M28F800B (IC203, IC204) Single Supply Flash Memory

M24C128 (IC205) 128Kbit Serial EEPROM

CXA2161R (IC301) I2C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control

LM833 (IC402) Low Noise Dual Operational Amplifier

CS4335 (IC401) 8-Pin, 24 Bit, 96 KHz Stereo D/A Converter

STA020D (IC403) 96 KHz Digital Audio Interface Transmitter

ADM707 (IC501) Low Cost µP Supervisory Circuits

TC1270 (IC502) 4 – Pin µP Reset Monitors

NDS8947 (Q507) Dual P – Channel Enhancement Mode Field Effect Transistor

74LVX245 (IC601,IC602) Low Voltage Cmos Octal Bus Transceiver (3 - State)

74HCT32 (IC603) Quad 2 – Input or Gate

POWER BOARD (16PW04 )

TOP233Y (IC1) SMPS primary IC

SFH617A (IC2) Optocoupler

TL431(IC3) Programmable Precision Reference

LM358N (IC4) Low Power Dual Operantional Amplifier

LM7812 (IC5) 12V Voltage Regulator

FRONT BOARD (16FP05, 16FP06, 16FP07)

TS87C52X2 (IC6) 8 Bit Microprocessor

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CONNECTORS
Power Connector

Power Connector – PL506

Pin Description
1 LNB_SUPPLY_IN
2 +30V
3 +12 V
4 GND
5 GND
6 +5 V
7 +3V3
8 +3V3
9 H/V
10 LNB_POWER_ENABLE
11 DISEQC

Front Panel Connector

Front Panel Connector – PL505

Pin Description
1 SCL_FP
2 SDA_FP
3 UP_RX
4 UP_TX
5 GND
6 UP_IRQ
7 SCART_ACTIVE
8 5VFP
9 GND
10 STANDBY
11 3V3FP

3. Scart Connector

3. Scart Connector – PL301

Pin Description
1 AUX2_CVBS_IN
2 GND
3 AUX2_CVBS_OUT
4 GND
5 AUX2_PIN8
6 +12VA
7 AUX_LIN
8 AUX_ROUT
9 AUX2_RIN
10 AUX_LOUT

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5512 JTAG Connectors

JTAG Connector – PL1

Pin Description Pin Description
1 ------ 11 TCK
2 GND 12 GND
3 TRIGOUT 13 TDI
4 GND 14 GND
5 TRIGIN 15 TDO
6 GND 16 GND
7 ------ 17 JTAGRESET
8 GND 18 GND
9 TMS 19 TRST
10 GND 20 GND

SCART CONNECTION

20 18 16 14 12 10 8 6 4 2

21 19 17 15 13 11 9 7 5 3 1

TV Scart Socket

TV Scart Socket – PL302

Pin Description Pin Description
1 Audio Right Output 12 No Connection
2 Audio Right Input 13 GND
3 Audio Left Output 14 GND
4 GND 15 RED Output
5 GND 16 Fast Blanking Output
6 Audio Left Input 17 GND
7 BLUE Output 18 GND
8 Function Switching Output 19 CVBS Output
9 GND 20 CVBS Input
10 No Connection 21 GND
11 GREEN Output

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AUX/VCR Scart Socket

AUX/VCR Scart Socket – PL302

Pin Description Pin Description
1 Audio Right Output 12 No Connection
2 Audio Right Input 13 GND
3 Audio Left Output 14 GND
4 GND 15 RED Input
5 GND 16 Fast Blanking Input
6 Audio Left Input 17 GND
7 BLUE Input 18 GND
8 Function Switching Input 19 CVBS Output
9 GND 20 CVBS Input
10 No Connection 21 GND
11 GREEN Input

VCR Scart Socket

VCR Scart Socket – PL1

Pin Description Pin Description
1 Audio Left Output 12 No Connection
2 Audio Right Input 13 No Connection
3 Audio Right Output 14 No Connection
4 GND 15 No Connection
5 GND 16 12 V
6 Audio Left Input 17 GND
7 No Connection 18 GND
8 Function Switching Input 19 CVBS Output
9 No Connection 20 CVBS Input
10 No Connection 21 GND
11 No Connection

RS232 Serial Port

RS232 Header – PL101

Pin Description Pin Description
1 - 2 -
3 TXD 4 CTS
5 RXD 6 RTS
7 - 8 -
9 GND

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RCA (Audio and Composite Video) Connector

A/V Connector – JK301

Pin Description
1 CVBS VIDEO
3 RIGHT AUDIO

POWER REQUIREMENTS
Power measurements are for a board configured according to the included Bill of Materials while playing a
typical DVB channel.

16MB04 VER:E3 Board

Power Consumption
Voltage Current mA Power
STAND_BY

Watts
LNB_SUPPLY_IN (13V, 18V) ----- -----
+30V ----- -----
+12V 30mA 360mW
+5V 145mA 725mW
+3V3 ----- ----
Voltage Current mA Power
POWER_ON

Watts
LNB_SUPPLY_IN (13V, 18V) 500mA (max) 6.5W, 9W
+30V 1mA 30mW
+12V 30mA 360mW
+5V 340mA 1.7W
+3V3 780mA 2.574W

PCB EXPLANATIONS
INTRODUCTION

DVB-S (digital satellite receiver) is designed with ST chipset. The technical information of
the receiver will be explained as three parts in the following pages: Power Board, Main Board
and Front Panel Board.

POWER BOARD (16PW04 – 5 )

The TOPSwitch concept is used for power supply. TOP 233Y (IC1) is designed to work
until 50 Watts in family of TOPSwitch_FX with 5 pins. The receiver works between 85 and 265
VAC mains voltage by using TOP 233Y in SMPS (Switch Mode Power Supply). The secondary

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voltage regulation is adjusted by changing the duty cycle of drain signal according to the
feedback voltage, which is got from the secondary side of transformer. The feedback voltages
are 3.3V and 5V. This is connected to the comparator pin of TOP 233Y (IC1-pin1) via IC12
(Optocoupler). The comparator pin also protects the box against short circuits and overload. The
Vcc voltage of IC1 is between 2V –3V at pin2. The TOP 233Y works at a fixed frequency. This
frequency is fixed by RC oscillator at pin1. The pin3 and pin 4 are ground and the pin5 is drain
of MOSFET, which is inside the TOP 233Y.

The switching of LNB supply voltage is done here. 18V and 22V outputs of transformer
switched by Q1, Q2 and H/V output of STV299 (TU501 or TU502). By this way overheating and
unnecessary power consumption of Q5 (BD235) that regulates the LNB supply is prevented.
22kHz tone which is needed for DiSEqC signals, is generated at pin18 (TU501) or pin10
(TU502) of STV0299 in tuner 22KHz is added to LNB supply here via LM358N (IC4)

16PE04-5 Power Board

Range of Voltage
Power
Voltage Range of Voltage
STAND_BY

Watts
LNB_SUPPLY_IN (13V, 18V) -----
+30V 31V – 34V
+12V 11.8V – 12.20V
+5V 4.2 V – 4.5V
+3V3 3.7 V – 3.9V
Power
Voltage Range of Voltage
Watts
POWER_ON

LNB_SUPPLY_IN ( 13V…VER. ) 13 V – 14 V
LNB_SUPPLY_IN ( 18V HOR.) 17V – 19V
+30V 31 V – 34 V
+12V 11.8 V – 12.2 V
+5V 4.9 V – 5.3 V
+3V3 3.7 V – 3.9V

MAIN BOARD ( 16MB04 Ver:3 )

The main board contains two parts: Front-end and Back-end. The digital signal is
demodulated in Front-end and then decoded in Back-end. Analog signals are processed in
different part.

The tuner (TU501 Alps or TU502 Sharp) is capable of getting both digital broadcasts.
After the modulated signals (I, Q outputs) receive from tuner, they go to STV0299 for
demodulation process in tuner. (TU501 or TU502) In this IC, QPSK (Quadrated Phase Shift
Keying) demodulation and Forward Error Correction (FEC) are done which is necessary to
demodulate DVB-S transmission. TS (transport stream): The multiplexed digital stream which
includes video, audio and data information related to more than one channel (can be only one
channel for SCPC signals) and DVB tables. TS signals which are generated after demodulation,
reach to Sti5512 (IC2) via 8 bits data bus. However, Byte Clock (FE_BCLK), Packet Clock
(FE_PCLK) and Error (FE_ERROR) signals are also sent to ST20 (ICS1) for demultiplexing

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process of TS. STV0299 is controlled by I2C. In addition, 22kHz tone which is needed for
DiSEqC signals, is generated at pin18 (TU501) or pin10 (TU502) of STV0299 in tuner.

LNB supply voltage (13/18V) is regulated via power board. Switching of supply voltage
between LOOP_IN and LNB_SUPPLY is done by Q501 transistors. The voltage on RL507 is
proportional with the current of LNB supply. Overload on LNB supply increases the voltage on
R507, which results switching of Q503, Q504. By this way input LNB_OVERLOAD signal port of
Sti 5512 (IC2) has the knowledge of LNB overload and then LNB supply is cut off for protection
of box via Sti 5512 interrupt port (P45_INT2).

At the backend part, there is a 32-bit CPU ST20 (in Sti 5512 embeded ) that controls all
processes. Demultiplexer of the CPU provides the transmission of the desired channel’s
information from TS (Transport Stream) to MPEG Decoder section. The program that runs on
Sti5512 is in Flash memories (IC203, IC204). 8Mbits SDRAMs (IC201, IC202) are used for data
memory of this program.

ST20 uses 32- bit data and 22- bit address buses for access to flash, DRAM and MPEG
decoder. It uses RAS, CAS etc. (read, write, enable) signals to activate related IC while
accessing them.
The clock which is needed by Sti 5512 (IC2), is generated at power on mode by 27MHz
crystal (X2) and IC4 (74HCU04). The output of PWM outputs of Sti 5512 (IC2), is filtered to have
a DC level via R96 and C22. At the output of ICS3, the 27MHz clock can be adjusted according
to capacity of pins of 27MHz crystal to ground. This capacity is related with DC value on D1 and
D2 (BB133) at pins of crystal. This operation maintains synchronization between audio-video
that are coming from MPEG transport stream and PCR clock.

Sti 5512 (IC2) can communicate any micro controller via RS232 by using IC1 (MAX232-
RS232 level converter). The RS232 output of receiver is used for debug any problem using
Windows Hyper Terminal program.

MPEG decoder in Sti 5512 (IC2), is responsible for decoding of MPEG video and audio
signals. The video, which is compressed using MPEG2 and audio, which is compressed using
MPEG1 Layer 1-2, are processed here. After decoding, CCIR 601 formatted 8-bit video and
PCM formatted audio, are generated by mpeg decoder.

If digital broadcast has a teletext information, Sti 5512 (IC2) inserts teletext info into VBI
(vertical blanking interval) which can be watched on TV. Digital audio that is PCM formatted on
Sti 5512’ s output, is processed by CS4335 (IC401) and amplified by LM833 (IC402) and then
switched through IC301 (CXA2161R).

In digital mode, RGB signals are only delivered to TV scart. CVBS output is distributed
through IC301 (CXA2161R) to TV, AUX/VCR and VCR scarts. When VCR becomes active,
audio and video signals are driven to TV and VCR scarts, which is activated by pin8 of VCR
scart.

The program information is stored in 128Kbits EEPROM (24C128 – IC205) via I2C.

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FRONT PANEL BOARD (16FP05-2, 16FP06-2, 16FP07-4)

To show program number, 4 digit 7 segment displays (MD1, MD2) are used on front
panel board. They are driven by 97C52 ( IC6 ) which is controlled by MC. The functional keys
are Standby, TV/Radio, Menu, OK, Vol+, Vol-, Prog+, Prog-. IR module ( MD3 ) is used for
remote control. Standby/power on led ( D2 ) is used to indicate whether the box is in Standby or
Power on mode with Red (Standby) and Green (Power on). Radio led ( D3 ) is used to show
radio channel.

FRONT PANEL PCBs

Functional Keys
16FP05-2 16FP06-2 16FP07-4
Key Name Description
Key Name Key Name Key Name
Standby Standby/Power on SW12 SW12 -----

TV/Radio TV/Radio SW6 SW6 SW6

Menu Menu SW7 SW7 SW7

OK OK SW9 SW9 SW9

Vol + Volume Up SW10 SW10 SW10

Vol - Volume Down SW11 SW11 SW11
Prog + Program Up SW8 SW8 SW8
Prog - Program Down SW13 SW13 SW13

SERVICE MENU INTERFACE

There is a service menu for service person which is accessed by entering “MAIN MENU”
then pressing “9”, “2”, “9”, “5”, “2”, “6” keys on the remote control or press “MENU” and
“LEFT” buttons on the front panel at the same time in Stand-by mode. You will see service menu
on the screen. This menu consists of fifteen active lines

RF Modulator System :

You can control RF modulator system at this line. RF modulator system option can be
selected as Pal G or Pal I or Pal K type in software side by pressing left or right cursor key on
the remote control.

RF Modulator Type :

You can control RF modulator type at this line. RF modulator option can be selected as
Sharp or Samsung or LG type in software side by pressing left or right cursor key on the remote
control.

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Tuner Type :

You can control Tuner type in software version at this line

Scarts :

You can control number of scarts in software version at this line

Reboot :

You press OK button on the front panel or on the remote commander. Apparatus is
restart.

Clear Database :

You press OK button on the front panel or on the remote commander. These settings
reinitialize whole EEPROM and store all programs erase.

L/R: DBCopy – OK: Upload PGM :

The object of this manual is to give necessary information and details to the user to
UPLOAD the program table to the receiver through RS232.

The list of the necessary equipment is as follows:

• Receiver and TV
• PC with “Hyper Terminal” function,
• RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:

1. Connect the serial communication cable between the RS232 outport of the receiver and the
serial communication port (COM1 or COM2) of the PC.
2. Make sure that the PC is on and the receiver is in Power on mode.
3. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /
Communications / Hyper Terminal menu.
4. For a new connection, run Hypertrm.exe file.
5. Give a name and choose an icon for the connection. (You do not need to make a new
connection every time. You can use this name for the future connections.)
6. Choose communication port in the new coming window (COM1 or COM2) whichever you
have used in Step 1.
7. Port settings should be as follows:
Bits per second : 38400
Data Bits : 8
Parity : None
Stop bits : 1
Flow control : None
8. Now Hyper Terminal connection is established.

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9. Go to “L/R: DBCopy – OK: Upload PGM” line on the service menu and press “LEFT” or
“RIGHT” keys of remote control (for copying database to the receiver). Please wait until the
print statements on the Hyper Terminal screen end.
10. From “Transfer” menu, choose “Receive File”.
11. Choose 1K Xmodem as protocol type.
12. “L/R: DBCopy – OK: Upload PGM” line on the service menu and press “OK” key of remote
control. Then Receive on of Hyper Terminal window and enter a file name like
(Program_table) and press “OK” button. then You will see the progress on the PC screen.
Besides, on TV screen the receiver will count the downloaded packets.
13. Wait for the transfer to be completed. Then, disconnect and exit from Hyper Terminal
window.

Download PGM :

The object of this manual is to give necessary information and details to the user to
upgrade the program table of the receiver through RS232.

The list of the necessary equipment is as follows:

• Receiver and TV
• PC with “Hyper Terminal” function,
• RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:

1. Connect the serial communication cable between the RS232 outport of the receiver and the
serial communication port (COM1 or COM2) of the PC.
2. Make sure that the PC is on and the receiver is in Power on mode.
3. Go to “ Clear Database ” line and press “OK” key and then wait for twenty seconds (old
program table is deleted).
4. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /
Communications / Hyper Terminal menu.
5. For a new connection, run Hypertrm.exe file.
6. Give a name and choose an icon for the connection. (You do not need to make a new
connection every time. You can use this name for the future connections.)
7. Choose communication port in the new coming window (COM1 or COM2) whichever you
have used in Step 1.
8. Port settings should be as follows:
Bits per second : 38400
Data Bits : 8
Parity : None
Stop bits : 1
Flow control : None
9. Now Hyper Terminal connection is established. From “Transfer” menu, choose “Send File”.
10. Enter file name to be sent (program table).
11. Choose Xmodem1K as protocol type.

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12. Press Send button of Hyper Terminal window and then Go to “Download PGM” line on the
service menu and press “OK” key of remote control. You will see the progress on the PC
screen. Besides, on TV screen the receiver will count the downloaded packets.
13. Wait for the transfer to be completed. Then, disconnect and exit from Hyper Terminal
window.
Reset receiver by pressing power on/off button. Receiver will tune to new program table.

Remote/Front Test :

You press “OK” button on the front panel or remote commander to enter Remote/Front
panel test then you can see name of the button on the front panel or remote commander you
pressed. By pressing Menu button on the front panel two times, you can exit.

7-Segment Display Test :

You press the OK key on the front panel or remote commander to start 7-segment
display test. You can see the test pattern on the display.

System Diagnostic :

You press the OK key on the front panel or remote commander and show your IC
information in apparatus main hardware

Development Team :

You press the OK key on the front panel or remote commander and Show your
development team list

Upload Default Sat_Xpdrs :

This line can explain information under line

Download Default Sat_Xpdrs :

The object of this manual is to give necessary information and details to the user to
transmission the program table and preset table to the receiver through RS232.

The list of the necessary equipment is as follows:

• Receiver (master that sends the program table), TV
• Receiver (slave that receives the program table), TV
• RS232 serial communication cable (male to male modem cable).

Steps to be followed by the user are given below:

1. Connect the serial communication cable between the RS232 outport of the receiver to other
receiver.
2. Make sure that both receivers are in Power on mode.

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3. Open the “main menu” and press “929526” keys sequentially for both of the receivers, you
will see service menu on the TV screens.
4. Go to “L/R: DBCopy – OK: Upload PGM” line on the service menu for master receiver and
press “LEFT” or “RIGHT” keys of remote control (for copying database to the receiver).
5. Go to “Download PGM” line on the service menu for slave receiver
6. “L/R: DBCopy – OK: Upload PGM” line on the service menu and press “OK” key of remote
control or front panel for master device. “Download PGM” line on the service menu and
press “OK” key of remote control or front panel for slave device. Besides, on TV screen the
receiver will count the downloaded packets.
7. Wait for the transfer to be completed the program table for both receivers.
8. Power off both receivers then power on them.
9. Open the “main menu” and press “929526” keys sequentially for both of the receivers, you
will see service menu on the TV screens.
10. Go to “Upload default Sat_Xpdrs” line on the service menu for master receiver.
11. Go to “Download default Sat_Xpdrs” line on the service menu for slave receiver
12. “Upload default Sat_Xpdrs” line on the service menu and press “OK” key of remote control
or front panel for master device. “Download default Sat_Xpdrs” line on the service menu
and press “OK” key of remote control or front panel for slave device. Besides, on TV screen
the receiver will count the downloaded packets.
13. Wait for the transfer to be completed the preset table for both receivers.

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Rs232 Test :

You connect the jumper to Rx output and Tx output. You press the “OK” key on the front
panel or remote commander then you can see “tESt” at the front display. You release the “OK”
key on the front panel or remote commander then you can see “Err” at the front display.

You can return to main menu by pressing “Menu” keys on the remote control

SOFTWARE UPGRADE THROUGH RS232

The object of this manual is to give necessary information and details to the user to
upgrade the software of the receiver through RS232.

The list of the necessary equipment is as follows:

Receiver and TV
PC with “Hyper Terminal” function,
RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:

1. Connect the serial communication cable between the RS232 out port of the receiver and the
serial communication port (COM1 or COM2) of the PC.
2. Make sure that the PC is on and the receiver is first reset and then turn to Standby mode.
3. To activate the Software Upgrade function of the receiver, press RIGHT and OK buttons on
the front panel at the same time. You will see the blinking “HOST” on the display. This
means that receiver is waiting for the new software to be sent by the PC.
4. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /
Communications / Hyper Terminal menu.
5. For a new connection, run Hypertrm.exe file.
6. Give a name and choose an icon for the connection. (You do not need to make a new
connection every time. You can use this name for the future connections.)
7. Choose communication port in the new coming window (COM1 or COM2) whichever you
have used in Step 1.
8. Port settings should be as follows:
Bits per second : 115200
Data Bits : 8
Parity : None
Stop bits : 1
Flow control : None
9. Now Hyper Terminal connection is established. From “Transfer” menu, choose “Send File”.
10. Enter file name to be sent.
11. Choose Xmodem1K as protocol type.
12. Press Send button. You will see the progress on the PC screen. Besides, front panel display
of the receiver will count the downloaded packets.
13. Wait for the transfer to be completed. Then, disconnect and exit from Hyper Terminal
window.
Receiver will automatically start to operate

Rev 1.0 12.06.03 15:46 Page 33

SERVICE MANUAL

SCHEMATICS

16PW04-5 POWER BOARD SCHEMATIC

16MB04-E3 MAINBOARD SCHEMATIC I

16MB04-E3 MAINBOARD SCHEMATIC II

16MB04-E3 MAINBOARD SCHEMATIC III

16MB04-E3 MAINBOARD SCHEMATIC IV

16MB04-E3 MAINBOARD SCHEMATIC V

16MB04-E3 MAINBOARD SCHEMATIC VI

16FP0X-X FRONT BOARD SCHEMATIC

DVB2 Sematik\16sc04-4.pdf - 3. SCART SHEMATIC

16UK04-1 REMOTE BOARD SCHEMATIC

Rev 1.0 12.06.03 15:46 Page 34

SERVICE MANUAL

BILL OF MATERIALS

20072807 POWERBOARD CHS.BASIC ON/OFF DVB 2

POS.NO DESCRIPTION VES.CODE POS.NO DESCRIPTION VES.CODE
C01 CAP MKT 220NF 275V M AC 30000094 PL1 CONN.MALE 2P MOLEX 30001792
C02 CAP MKT 220NF 275V M AC 30000094 PL2 CONN MALE 11P TOP WHITE 30006710
C03 CAP EL 47UF 400V M 30000423 PL3 CONN.MALE 2P MOLEX 30001792
C05 CAP CER 100NF 50V Z F 30000295 Q1 TR BD238 30001422
C08 CAP EL 1000UF 16V M 30000359 Q10 TR BC548B 30001454
C09 CAP EL 1000UF 16V M 30000359 Q2 TR BC548B 30001454
C10 CAP EL 100UF 16V M 30000352 Q5 TR BD235 30001446
C11 CAP EL 100UF 16V M 30000352 Q6 TR BC548B 30001454
C12 CAP CER 100NF 50V Z F 30000295 Q7 TR BC548B 30001454
C13 CAP EL 22UF 50V M 30000371 Q8 TR BC548B 30001454
C15 CAP EL 220UF 35V M 30000377 Q9 TR BC548B 30001454
C16 CAP EL 220UF 35V M 30000377 R01 RES CF 1/2W 2.2M J (400V) 30000603
C17 CAP EL 47UF 100V M 30000402 R05 RES CF 1/4W 470R J 30000712
C19 CAP EL 1000UF 35V M 30000361 R06 RES CF 1/4W 10R J 30000452
C20 CAP EL 470UF 25V M 30000409 R07 RES MF 1/4W 10K F 30007200
C21 CAP CER 2.2NF 4KV M 30000440 R08 RES MF 1/4W 10K F 30007200
C24 CAP CER 100NF 50V Z F 30000295 R09 RES MF 1/4W 15K F 30000888
C25 CAP CER 330PF 50V J SL 30000244 R10 RES CF 1/4W 220R J 30000583
C26 CAP CER 1NF 50V K B 30000283 R11 RES CF 1/4W 51R J 30000736
C27 CAP CER 68PF 50V J CH 30000269 R12 RES CF 1/2W 680R J 30000769
C28 CAP CER 10NF 50V K B 30000287 R13 RES CF 1/4W 4.7K J 30000718
C29 CAP CER 1NF 50V K B 30000283 R14 RES CF 1/4W 10K J 30000471
C30 CAP CER 100NF 50V Z F 30000295 R20 RES CF 1/4W 220R J 30000583
C32 CAP CER 100NF 50V Z F 30000295 R21 RES MF 1/4W 10K F 30007200
C33 CAP EL 100UF 16V M 30000352 R22 RES MF 1/4W 47K F 30000985
C34 CAP EL 47UF 50V M 30000400 R23 RES CF 1/4W 10K J 30000471
C35 CAP CER 100PF 1KV M 30000431 R24 RES MF 1/4W 47K F 30000985
C36 CAP CER 100PF 1KV M 30000431 R25 RES MF 1/4W 82K G 30001028
D01 DIODE 1N4007 1A/1000V 30A 30001329 R26 RES CF 1/4W 2.2K J 30000590
D02 DIODE 1N4007 1A/1000V 30A 30001329 R27 RES CF 1/4W 82K J 30000820
D03 DIODE 1N4007 1A/1000V 30A 30001329 R28 RES CF 1/4W 4.7K J 30000718
D04 DIODE 1N4007 1A/1000V 30A 30001329 R29 RES CF 1/4W 10K J 30000471
D05 DIODE 1N4148 0.15A/100V 0.5A 30001284 R30 RES CF 1/4W 10K J 30000471
D06 DIODE BA159 1A/800V 20A 30001318 R31 RES CF 1/4W 4.7K J 30000718
D07 DIODE BYV28-200 3.5A/200V 90A 30010700 R32 RES MF 1/4W 82K G 30001028
D08 DIODE BYV28-200 3.5A/200V 90A 30010700 R34 RES CF 1/4W 10K J 30000471
D09 DIODE BYD33M 1A/1000V 20A 30001303 R35 RES CF 1/4W 10K J 30000471
D10 DIODE BYV28-200 3.5A/200V 90A 30010700 R40 RES CF 1/4W 6.8R J 30000790
D11 DIODE BYV28-200 3.5A/200V 90A 30010700 R41 RES CF 1/2W 1.5K J 30000525
D13 DIODE ZENER 33V UZT 33B 30001377 R42 RES CF 1/4W 220K J 30000599
D14 DIODE 1N4007 1A/1000V 30A 30001329 R43 RES CF 1/4W 220K J 30000599
D15 DIODE 1N4007 1A/1000V 30A 30001329 TR1 TRF SMPS DVB 30014414
D16 DIODE ZENER 200V 30010708 PCB 16PW04-5 30016516
F1 FUSE 2.5A 250V 5*20MM 30001731 SİGORTA YUVASI TK79-A (GRAY) 35000136
IC1 IC TOP233Y 30012864 TR SOĞUTUCU (10X19X35 MM) 35002781
IC2 IC TCET1102G 30015087 POWER CORD ASSY.(2.4MT W/FTZ) 30011787
IC3 IC TL431 30001506 SWITCH ON/OFF ASSY 7cm DVB2 30016532
IC4 IC LM358N (ANALOG SAT) 30015124 CONN ASSY 11P 10CM W/FERRITE 30016831
IC5 IC MC7812CT 30001501
J2 KISA DEVRE TELİ 0.6MM 30002583
J4 KISA DEVRE TELİ 0.6MM 30002583
J5 KISA DEVRE TELİ 0.6MM 30002583
J6 KISA DEVRE TELİ 0.6MM 30002583
J7 KISA DEVRE TELİ 0.6MM 30002583
L1 COIL CHOKE 22UH RADIAL 30011450
L2 COIL CHOKE 22UH RADIAL 30011450
L3 COIL CHOKE 22UH RADIAL 30011450
L5 COIL CHOKE 22UH RADIAL 30011450
L6 LINE FILTER 2*32MH (AK19) 30002103

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SERVICE MANUAL

BILL OF MATERIALS (CONTINUED)

20085501 MAINBOARD DVB2 FULL VERSION 3.SCART(ALPS TUNER)

POS.NO DESCRIPTION VES.CODE POS.NO DESCRIPTION VES.CODE
C1 CAP EL 10UF 50V M 30000345 C347 CAP EL 10UF 50V M 30000345
C2 CAP EL 10UF 50V M 30000345 C348 CAP EL 10UF 50V M 30000345
C203 CAP SMD 100NF 16V K R (0603) 30016654 C349 CAP EL 10UF 50V M 30000345
C205 CAP SMD 100NF 16V K R (0603) 30016654 C350 CAP SMD 220NF 25V Z (0805) 30000315
C206 CAP SMD 100NF 16V K R (0603) 30016654 C351 CAP EL 22UF 50V M 30000371
C207 CAP SMD 100NF 16V K R (0603) 30016654 C352 CAP SMD 220NF 25V Z (0805) 30000315
C209 CAP SMD 100NF 16V K R (0603) 30016654 C353 CAP SMD 220NF 25V Z (0805) 30000315
C212 CAP SMD 100NF 16V K R (0603) 30016654 C354 CAP SMD 220NF 25V Z (0805) 30000315
C213 CAP SMD 100NF 16V K R (0603) 30016654 C355 CAP SMD 220NF 25V Z (0805) 30000315
C215 CAP SMD 100NF 16V K R (0603) 30016654 C356 CAP SMD 220NF 25V Z (0805) 30000315
C217 CAP SMD 100NF 16V K R (0603) 30016654 C357 CAP SMD 1NF 50V K R (0603) 30012581
C218 CAP SMD 100NF 16V K R (0603) 30016654 C358 CAP SMD 1NF 50V K R (0603) 30012581
C219 CAP SMD 100NF 16V K R (0603) 30016654 C359 CAP SMD 100NF 16V K R (0603) 30016654
C22 CAP EL 100UF 16V M 30000352 C36 CAP SMD 100NF 16V K R (0603) 30016654
C23 CAP SMD 100NF 16V K R (0603) 30016654 C360 CAP SMD 1NF 50V K R (0603) 30012581
C24 CAP SMD 100NF 16V K R (0603) 30016654 C361 CAP SMD 1NF 50V K R (0603) 30012581
C25 CAP EL 100UF 16V M 30000352 C362 CAP SMD 1NF 50V K R (0603) 30012581
C26 CAP SMD 10PF 50V D COG (0603) 30012559 C363 CAP SMD 220PF 50V J (0603) 30012567
C27 CAP SMD 22PF 50V J (0603) 30012566 C364 CAP SMD 1NF 50V K R (0603) 30012581
C28 CAP SMD 100NF 16V K R (0603) 30016654 C365 CAP SMD 1NF 50V K R (0603) 30012581
C29 CAP SMD 330PF 50V J (0603) 30012570 C366 CAP SMD 220PF 50V J (0603) 30012567
C3 CAP EL 10UF 50V M 30000345 C367 CAP SMD 1NF 50V K R (0603) 30012581
C30 CAP SMD 100NF 16V K R (0603) 30016654 C368 CAP SMD 220PF 50V J (0603) 30012567
C301 CAP SMD 47PF 50V J (0603) 30012573 C369 CAP SMD 1NF 50V K R (0603) 30012581
C302 CAP SMD 10PF 50V D COG (0603) 30012559 C37 CAP SMD 22PF 50V J (0603) 30012566
C303 CAP SMD 47PF 50V J (0603) 30012573 C370 CAP SMD 1NF 50V K R (0603) 30012581
C304 CAP EL 33UF 16V M 30000386 C371 CAP SMD 220PF 50V J (0603) 30012567
C305 CAP SMD 47PF 50V J (0603) 30012573 C374 CAP SMD 100NF 16V K R (0603) 30016654
C306 CAP SMD 10PF 50V D COG (0603) 30012559 C375 CAP SMD 220PF 50V J (0603) 30012567
C307 CAP SMD 47PF 50V J (0603) 30012573 C376 CAP SMD 220PF 50V J (0603) 30012567
C308 CAP EL 33UF 16V M 30000386 C377 CAP SMD 220PF 50V J (0603) 30012567
C309 CAP SMD 47PF 50V J (0603) 30012573 C378 CAP SMD 220PF 50V J (0603) 30012567
C31 CAP SMD 10NF 25V K R (0603) 30012602 C379 CAP SMD 220PF 50V J (0603) 30012567
C310 CAP SMD 10PF 50V D COG (0603) 30012559 C38 CAP SMD 22PF 50V J (0603) 30012566
C311 CAP SMD 10PF 50V D COG (0603) 30012559 C380 CAP SMD 220PF 50V J (0603) 30012567
C312 CAP SMD 47PF 50V J (0603) 30012573 C381 CAP SMD 220PF 50V J (0603) 30012567
C313 CAP EL 33UF 16V M 30000386 C383 CAP SMD 100NF 50V K (0805) 30000294
C314 CAP SMD 47PF 50V J (0603) 30012573 C384 CAP SMD 220PF 50V J (0603) 30012567
C315 CAP SMD 47PF 50V J (0603) 30012573 C386 CAP SMD 100NF 16V K R (0603) 30016654
C316 CAP EL 33UF 16V M 30000386 C387 CAP EL 10UF 50V M 30000345
C317 CAP EL 47UF 50V M 30000400 C388 CAP EL 10UF 50V M 30000345
C318 CAP EL 47UF 50V M 30000400 C389 CAP SMD 100NF 16V K R (0603) 30016654
C319 CAP SMD 100NF 16V K R (0603) 30016654 C390 CAP EL 100UF 16V M 30000352
C32 CAP SMD 10NF 25V K R (0603) 30012602 C391 CAP EL 100UF 16V M 30000352
C320 CAP SMD 100NF 16V K R (0603) 30016654 C392 CAP SMD 220NF 25V Z (0805) 30000315
C321 CAP SMD 100NF 16V K R (0603) 30016654 C4 CAP EL 10UF 50V M 30000345
C334 CAP SMD 100NF 16V K R (0603) 30016654 C401 CAP SMD 270PF 50V J (0603) 30012568
C335 CAP SMD 220NF 25V Z (0805) 30000315 C402 CAP EL 100UF 16V M 30000352
C336 CAP SMD 220NF 25V Z (0805) 30000315 C403 CAP SMD 100NF 16V K R (0603) 30016654
C337 CAP SMD 100NF 16V K R (0603) 30016654 C404 CAP EL 10UF 50V M 30000345
C338 CAP SMD 220NF 25V Z (0805) 30000315 C405 CAP EL 10UF 50V M 30000345
C339 CAP SMD 220NF 25V Z (0805) 30000315 C406 CAP SMD 270PF 50V J (0603) 30012568
C340 CAP EL 10UF 50V M 30000345 C407 CAP EL 10UF 50V M 30000345
C341 CAP EL 10UF 50V M 30000345 C410 CAP EL 10UF 50V M 30000345
C342 CAP EL 10UF 50V M 30000345 C411 CAP SMD 100NF 16V K R (0603) 30016654
C343 CAP SMD 220NF 25V Z (0805) 30000315 C412 CAP SMD 100NF 16V K R (0603) 30016654
C344 CAP SMD 220NF 25V Z (0805) 30000315 C416 CAP SMD 2.2NF 50V K R (0603) 30012585
C345 CAP SMD 220NF 25V Z (0805) 30000315 C417 CAP SMD 2.2NF 50V K R (0603) 30012585
C346 CAP EL 10UF 50V M 30000345 C418 CAP SMD 2.2NF 50V K R (0603) 30012585

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SERVICE MANUAL

BILL OF MATERIALS (CONTINUED)

POS.NO DESCRIPTION VES.CODE POS.NO DESCRIPTION VES.CODE

C419 CAP SMD 2.2NF 50V K R (0603) 30012585 Q4 TR BC857B SMD 30012552
C420 CAP SMD 47PF 50V J (0603) 30012573 Q501 TR BD238 30001422
C5 CAP SMD 100NF 16V K R (0603) 30016654 Q502 TR BC847B SMD 30012551
C501 CAP SMD 1NF 50V K R (0805) 30000284 Q503 TR BC857B SMD 30012552
C502 CAP SMD 1NF 50V K R (0805) 30000284 Q504 TR BC847B SMD 30012551
C503 CAP SMD 100NF 16V K R (0603) 30016654 Q507 TR NDS8947 30014344
C504 CAP SMD 100NF 50V K (0805) 30000294 Q508 TR BC847B SMD 30012551
C505 CAP SMD 100NF 50V K (0805) 30000294 Q509 TR BC847B SMD 30012551
C506 CAP SMD 100NF 16V K R (0603) 30016654 Q510 TR BC847B SMD 30012551
C508 CAP SMD 100NF 16V K R (0603) 30016654 Q511 TR BC847B SMD 30012551
C509 CAP SMD 100NF 16V K R (0603) 30016654 Q512 TR BC847B SMD 30012551
C510 CAP SMD 100NF 16V K R (0603) 30016654 Q513 TR BC847B SMD 30012551
C511 CAP SMD 100NF 50V K (0805) 30000294 R100 RES SMD 1/10W 9.1K F (0603) 30014170
C512 CAP SMD 100NF 16V K R (0603) 30016654 R101 RES SMD 1/16W 1.5K J (0603) 30012506
C513 CAP EL 47UF 50V M 30000400 R102 RES SMD 1/16W 330K J (0603) 30012683
C514 CAP EL 47UF 50V M 30000400 R103 RES SMD 1/16W 10K J (0603) 30012641
C515 CAP EL 47UF 50V M 30000400 R104 RES SMD 1/16W 10K J (0603) 30012641
C517 CAP SMD 100NF 16V K R (0603) 30016654 R105 RES SMD 1/16W 10K J (0603) 30012641
C524 CAP SMD 100NF 16V K R (0603) 30016654 R106 RES SMD 1/16W 75R J (0603) 30012713
C525 CAP SMD 100NF 16V K R (0603) 30016654 R107 RES SMD 1/16W 75R J (0603) 30012713
C6 CAP SMD 100NF 16V K R (0603) 30016654 R108 RES SMD 1/16W 10K J (0603) 30012641
D1 DIODE VAR BB133 SMD 30010689 R109 RES SMD 1/16W 10K J (0603) 30012641
D2 DIODE VAR BB133 SMD 30010689 R110 RES SMD 1/16W 10K J (0603) 30012641
D501 DIODE 1N4007 1A/1000V 30A 30001329 R111 RES SMD 1/16W 10K J (0603) 30012641
IC1 IC MAX232 (DIP 16) 30010816 R112 RES SMD 1/16W 22K J (0603) 30012669
IC2 IC STI5512 tape&reel 30014086 R113 RES SMD 1/16W 47K J (0603) 30012696
IC201 IC SDRAM 4MX16 100MHZ tape&reel 30014088 R114 RES SMD 1/16W 8.2K J (0603) 30012712
IC203 IC FLASH 8MB (TOP BOOT) tape&re 30014952 R115 RES SMD 1/16W 1M J (0603) 30012658
IC205 IC 24C128 SMD tape&reel 30010796 R116 RES SMD 1/16W 75R J (0603) 30012713
IC3 IC TSH22 (SO8) tape&reel 30007366 R117 RES SMD 1/16W 3K J (0603) 30012690
IC301 IC CXA2161R tape&reel 30014090 R118 RES SMD 1/16W 4.7K J (0603) 30012692
IC4 IC 74HCU04 (SO14) tape&reel 30010780 R119 RES SMD 1/16W 4.7K J (0603) 30012692
IC401 IC DAC CS4335 tape&reel 30012800 R120 RES SMD 1/16W 4.7K J (0603) 30012692
IC402 IC LM 833(SO8) tape&reel 30007378 R121 RES SMD 1/16W 470K J (0603) 30012694
IC503 IC DS1811(RESET IC) 30014714 R122 RES SMD 1/16W 470K J (0603) 30012694
JK301 JACK RCA 3P-DVB- 30014195 R124 RES SMD 1/16W 4.7K J (0603) 30012692
L1 FIXED COIL 22UH J AXIAL 30001994 R126 RES SMD 1/16W 10K J (0603) 30012641
L301 FIXED COIL 10UH Q65 K-A 30001992 R127 RES SMD 1/16W 10K J (0603) 30012641
L302 FIXED COIL 10UH Q65 K-A 30001992 R129 RES SMD 1/16W 10K J (0603) 30012641
L303 FIXED COIL 10UH Q65 K-A 30001992 R14 RES SMD 1/16W 4.7K J (0603) 30012692
L304 COIL FIXED 22UH J RAD 30011011 R15 RES SMD 1/16W 4.7K J (0603) 30012692
L305 FIXED COIL 10UH Q65 K-A 30001992 R21 RES SMD 1/16W 2.2K J (0603) 30012659
L306 COIL FIXED 22UH J RAD 30011011 R22 RES SMD 1/16W 2.2K J (0603) 30012659
L401 COIL FIXED 22UH J RAD 30011011 R225 RES SMD 1/16W 10K J (0603) 30012641
L402 COIL FIXED 22UH J RAD 30011011 R24 RES SMD 1/16W 33R J (0603) 30014128
L501 COIL FIXED 22UH J RAD 30011011 R29 RES SMD 1/16W 10K J (0603) 30012641
L502 COIL FIXED 22UH J RAD 30011011 R301 RES SMD 1/16W 390R J (0603) 30012688
PL1 HEADER 10X2(2,54MM) 30010902 R302 RES SMD 1/16W 390R J (0603) 30012688
PL101 JACK D-SUB 9P 30007040 R303 RES SMD 1/16W 390R J (0603) 30012688
PL301 CONN MALE 10P TOP WHITE 30012894 R304 RES SMD 1/16W 390R J (0603) 30012688
PL302 DOUBLE-DECK SCART SOCKET 30010921 R305 RES SMD 1/16W 390R J (0603) 30012688
PL505 CONN MALE 11P TOP WHITE 30006710 R306 RES SMD 1/16W 390R J (0603) 30012688
PL506 CONN MALE 11P TOP WHITE 30006710 R307 RES SMD 1/16W 390R J (0603) 30012688
Q3 TR BC857B SMD 30012552 R308 RES SMD 1/16W 390R J (0603) 30012688
Q305 TR BC847B SMD 30012551 R321 RES SMD 1/10W 75R J (0805) 30000797
Q306 TR BC847B SMD 30012551 R322 RES SMD 1/10W 75R J (0805) 30000797
Q307 TR BC847B SMD 30012551 R323 RES SMD 1/10W 75R J (0805) 30000797
Q308 TR BC847B SMD 30012551 R324 RES SMD 1/10W 75R J (0805) 30000797
Q309 TR BC847B SMD 30012551 R325 RES SMD 1/16W 10K J (0603) 30012641

Rev 1.0 12.06.03 15:46 Page 37

SERVICE MANUAL

BILL OF MATERIALS (CONTINUED)

POS.NO DESCRIPTION VES.CODE POS.NO DESCRIPTION VES.CODE

R326 RES SMD 1/16W 10K J (0603) 30012641 R434 RES SMD 1/16W 75R J (0603) 30012713
R327 RES SMD 1/16W 10K J (0603) 30012641 R501 RES SMD 1/16W 33K J (0603) 30012685
R329 RES SMD 1/16W 1K J (0603) 30012657 R502 RES CF 1/2W 680R J 30000769
R330 RES SMD 1/16W 1K J (0603) 30012657 R503 RES SMD 1/16W 100R J (0603) 30012510
R331 RES SMD 1/10W 75R J (0805) 30000797 R504 RES SMD 1/16W 100R J (0603) 30012510
R332 RES SMD 1/16W 68K J (0603) 30012708 R505 RES SMD 1/16W 2.2K J (0603) 30012659
R333 RES SMD 1/10W 75R J (0805) 30000797 R506 RES SMD 1/16W 10K J (0603) 30012641
R334 RES SMD 1/10W 75R J (0805) 30000797 R507 RES MF 1/2W 0.82R J 30016742
R335 RES SMD 1/10W 75R J (0805) 30000797 R535 RES SMD 1/16W 33R J (0603) 30014128
R336 RES SMD 1/16W 75R J (0603) 30012713 R536 RES SMD 1/16W 33R J (0603) 30014128
R337 RES SMD 1/10W 75R J (0805) 30000797 R537 RES SMD 1/16W 33R J (0603) 30014128
R338 RES SMD 1/10W 75R J (0805) 30000797 R538 RES SMD 1/16W 33R J (0603) 30014128
R339 RES SMD 1/10W 75R J (0805) 30000797 R539 RES SMD 1/16W 33R J (0603) 30014128
R340 RES SMD 1/16W 47K J (0603) 30012696 R540 RES SMD 1/16W 33R J (0603) 30014128
R342 RES SMD 1/16W 220R J (0603) 30012668 R541 RES SMD 1/16W 33R J (0603) 30014128
R343 RES SMD 1/16W 220R J (0603) 30012668 R542 RES SMD 1/16W 33R J (0603) 30014128
R344 RES SMD 1/10W 75R J (0805) 30000797 R543 RES SMD 1/16W 33R J (0603) 30014128
R345 RES SMD 1/16W 100R J (0603) 30012510 R544 RES SMD 1/16W 33R J (0603) 30014128
R346 RES SMD 1/16W 100R J (0603) 30012510 R545 RES SMD 1/16W 33R J (0603) 30014128
R347 RES SMD 1/16W 1K J (0603) 30012657 R546 RES SMD 1/16W 33R J (0603) 30014128
R348 RES SMD 1/16W 1K J (0603) 30012657 R547 RES SMD 1/16W 10K J (0603) 30012641
R349 RES SMD 1/16W 1K J (0603) 30012657 R549 RES SMD 1/16W 4.7K J (0603) 30012692
R350 RES SMD 1/16W 1K J (0603) 30012657 R550 RES SMD 1/16W 2.2K J (0603) 30012659
R351 RES SMD 1/10W 100R J 30000464 R552 RES SMD 1/16W 33R J (0603) 30014128
R352 RES SMD 1/16W 1K J (0603) 30012657 R553 RES SMD 1/16W 33R J (0603) 30014128
R353 RES SMD 1/16W 1K J (0603) 30012657 R554 RES SMD 1/16W 33R J (0603) 30014128
R354 RES SMD 1/16W 1K J (0603) 30012657 R555 RES SMD 1/16W 33R J (0603) 30014128
R355 RES SMD 1/16W 1K J (0603) 30012657 R556 RES SMD 1/16W 33R J (0603) 30014128
R357 RES SMD 1/16W 1K J (0603) 30012657 R557 RES SMD 1/16W 47K J (0603) 30012696
R358 RES SMD 1/16W 10K J (0603) 30012641 R558 RES SMD 1/16W 4.7K J (0603) 30012692
R359 RES SMD 1/16W 10K J (0603) 30012641 R559 RES SMD 1/16W 47K J (0603) 30012696
R360 RES SMD 1/16W 150R J (0603) 30012649 R560 RES SMD 1/16W 47K J (0603) 30012696
R361 RES SMD 1/16W 1K J (0603) 30012657 R561 RES SMD 1/16W 47K J (0603) 30012696
R362 RES SMD 1/16W 1K J (0603) 30012657 R562 RES SMD 1/16W 47K J (0603) 30012696
R363 RES SMD 1/16W 150R J (0603) 30012649 R96 RES SMD 1/16W 8.2K J (0603) 30012712
R364 RES SMD 1/16W 1K J (0603) 30012657 R97 RES SMD 1/16W 33R J (0603) 30014128
R365 RES SMD 1/16W 1K J (0603) 30012657 R98 RES SMD 1/16W 33R J (0603) 30014128
R366 RES SMD 1/16W 100R J (0603) 30012510 R99 RES SMD 1/10W 9.1K F (0603) 30014170
R367 RES SMD 1/16W 100R J (0603) 30012510 S2 JUMPER SMD 0603 30012985
R368 RES SMD 1/16W 100R J (0603) 30012510 S201 JUMPER SMD 0603 30012985
R369 RES SMD 1/16W 100R J (0603) 30012510 S204 JUMPER SMD 0603 30012985
R370 RES SMD 1/16W 75R J (0603) 30012713 S3 JUMPER SMD 0603 30012985
R371 RES SMD 1/16W 1K J (0603) 30012657 S302 RES SMD 1/16W 4.7R J (0603) 30014076
R372 RES SMD 1/16W 33R J (0603) 30014128 S305 RES SMD 1/16W 4.7R J (0603) 30014076
R373 RES SMD 1/16W 33R J (0603) 30014128 S306 JUMPER SMD 0603 30012985
R374 RES SMD 1/10W 100R J 30000464 S5 JUMPER SMD 0603 30012985
R375 RES SMD 1/16W 220R J (0603) 30012668 S8 JUMPER SMD 0603 30012985
R401 RES SMD 1/16W 1.2K J (0603) 30012504 TU302 MODULATOR RF TAMC_G001D 30014089
R402 RES SMD 1/16W 1.2K J (0603) 30012504 TU501 TUNER NIM BSRU6 ALPS 30014123
R403 RES SMD 1/16W 5.6K J (0603) 30012698 X1 XTAL 32.768KHZ 30010876
R412 RES SMD 1/16W 5.6K J (0603) 30012698 X2 XTAL 27MHZ R=20 OHM 30007367
R413 RES SMD 1/16W 47K J (0603) 30012696 PCB 16MB04E3 30016440
R414 RES SMD 1/16W 47K J (0603) 30012696
R428 RES SMD 1/16W 220K J (0603) 30012667
R429 RES SMD 1/16W 220K J (0603) 30012667
R430 RES SMD 1/16W 1K J (0603) 30012657
R431 RES SMD 1/16W 1K J (0603) 30012657
R432 RES SMD 1/16W 1K J (0603) 30012657
R433 RES SMD 1/16W 1K J (0603) 30012657

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SERVICE MANUAL

BILL OF MATERIALS (CONTINUED)

20071903 FRONT PANEL CHS.BASIC DVB2-7XX

POS.NO DESCRIPTION VES.CODE POS.NO DESCRIPTION VES.CODE
C1 CAP EL 47UF 16V M 30000396 R2 RES SMD 1/16W 220R J (0603) 30012668
C2 CAP EL 47UF 16V M 30000396 R20 RES SMD 1/16W 5.6K J (0603) 30012698
C3 CAP SMD 100NF 16V K R (0603) 30016654 R21 RES SMD 1/16W 1.8K J (0603) 30012508
C4 CAP SMD 27PF 50V J CH (0603) 30012608 R22 RES SMD 1/16W 47R J (0603) 30014022
C5 CAP SMD 27PF 50V J CH (0603) 30012608 R23 RES SMD 1/16W 2.2K J (0603) 30012659
C6 CAP EL 1UF 50V M 30000362 R24 RES SMD 1/16W 4.7K J (0603) 30012692
C7 CAP EL 1UF 50V M 30000362 R25 RES SMD 1/16W 4.7K J (0603) 30012692
D1 DIODE 1N4148 SMD 30001285 R26 RES SMD 1/16W 4.7K J (0603) 30012692
D2 LED RED/GREEN VDC30354 3MM 30010688 R27 RES SMD 1/16W 4.7K J (0603) 30012692
D2 LED HOLDER LED3-11 40009122 R28 RES SMD 1/16W 220R J (0603) 30012668
D3 LED ORANGE VLL30432 3MM 30010686 R29 RES SMD 1/16W 470R J (0603) 30012695
D3 LED HOLDER (16TK01) 40005188 R3 RES SMD 1/16W 220R J (0603) 30012668
IC6 IC TS87C52X2-MCB tape&reel 30014342 R30 RES SMD 1/16W 10K J (0603) 30012641
J1 KISA DEVRE TELİ 0.6MM 30002583 R31 RES SMD 1/16W 10K J (0603) 30012641
J10 KISA DEVRE TELİ 0.6MM 30002583 R32 RES SMD 1/16W 10K J (0603) 30012641
J11 KISA DEVRE TELİ 0.6MM 30002583 R33 RES SMD 1/16W 10K J (0603) 30012641
J12 KISA DEVRE TELİ 0.6MM 30002583 R34 RES SMD 1/16W 10K J (0603) 30012641
J13 KISA DEVRE TELİ 0.6MM 30002583 R35 RES SMD 1/16W 4.7K J (0603) 30012692
J14 KISA DEVRE TELİ 0.6MM 30002583 R36 RES SMD 1/16W 4.7K J (0603) 30012692
J15 KISA DEVRE TELİ 0.6MM 30002583 R37 RES SMD 1/16W 4.7K J (0603) 30012692
J16 KISA DEVRE TELİ 0.6MM 30002583 R38 RES SMD 1/16W 4.7K J (0603) 30012692
J17 KISA DEVRE TELİ 0.6MM 30002583 R39 RES SMD 1/16W 4.7K J (0603) 30012692
J18 KISA DEVRE TELİ 0.6MM 30002583 R4 RES SMD 1/16W 220R J (0603) 30012668
J19 KISA DEVRE TELİ 0.6MM 30002583 R40 RES SMD 1/16W 1K F (0603) 30013001
J2 KISA DEVRE TELİ 0.6MM 30002583 R41 RES SMD 1/16W 1K F (0603) 30013001
J20 KISA DEVRE TELİ 0.6MM 30002583 R5 RES SMD 1/16W 220R J (0603) 30012668
J21 KISA DEVRE TELİ 0.6MM 30002583 R6 RES SMD 1/16W 220R J (0603) 30012668
J22 KISA DEVRE TELİ 0.6MM 30002583 R7 RES SMD 1/16W 220R J (0603) 30012668
J23 KISA DEVRE TELİ 0.6MM 30002583 SW10 SWITCH TACT 30002181
J24 KISA DEVRE TELİ 0.6MM 30002583 SW11 SWITCH TACT 30002181
J25 KISA DEVRE TELİ 0.6MM 30002583 SW13 SWITCH TACT 30002181
J26 KISA DEVRE TELİ 0.6MM 30002583 SW6 SWITCH TACT 30002181
J27 JUMPER SMD 0603 30012985 SW7 SWITCH TACT 30002181
J28 JUMPER SMD 0603 30012985 SW8 SWITCH TACT 30002181
J3 KISA DEVRE TELİ 0.6MM 30002583 SW9 SWITCH TACT 30002181
J4 KISA DEVRE TELİ 0.6MM 30002583 X1 XTAL 8MHZ (12.7mm leg) 30016932
J5 KISA DEVRE TELİ 0.6MM 30002583 PCB 16FP07-3 30016941
J6 KISA DEVRE TELİ 0.6MM 30002583 CONN ASSY 11P 20CM W/FERRITE 30016832
J7 KISA DEVRE TELİ 0.6MM 30002583
J8 KISA DEVRE TELİ 0.6MM 30002583
J9 KISA DEVRE TELİ 0.6MM 30002583
MD1 SEVEN SEGMENT 2'LI ELD-512IDB 30011016
MD2 SEVEN SEGMENT 2'LI ELD-512IDB 30011016
MD3 PREAMPLIFIER TFMS5360 30001670
Q1 TR BC847B SMD 30012551
Q2 TR BC847B SMD 30012551
Q3 TR BC847B SMD 30012551
Q4 TR BC847B SMD 30012551
Q5 TR BC847B SMD 30012551
Q6 TR BC857B SMD 30012552
R1 RES SMD 1/16W 220R J (0603) 30012668
R12 RES SMD 1/16W 100R J (0603) 30012510
R13 RES SMD 1/16W 4.7K J (0603) 30012692
R14 RES SMD 1/16W 4.7K J (0603) 30012692
R15 RES SMD 1/16W 4.7K J (0603) 30012692
R16 RES SMD 1/16W 4.7K J (0603) 30012692
R17 RES SMD 1/16W 4.7K J (0603) 30012692
R18 RES SMD 1/16W 4.7K J (0603) 30012692
R19 RES SMD 1/16W 4.7K J (0603) 30012692

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SERVICE MANUAL

BILL OF MATERIALS (CONTINUED)

20062060 REMOTE CONTROL DVB2 UKV B.ASSY 20087128 3. SCART ASSY DVB-2 (SMD)
POS.NO DESCRIPTION VES.CODE POS.NO DESCRIPTION VES.CODE
C100 CAP EL 47UF 6.3V M (4*7MM) 30000395 C7 CAP SMD 470PF 50V J (0805) 30000256
D100 LED INFRARED IR333 30002733 C8 CAP SMD 470PF 50V J (0805) 30000256
IC1 IC SAA3010T 30002735 C9 CAP SMD 1NF 50V K R (0805) 30000284
Q101 TR BC548B 30001454 C10 CAP SMD 1NF 50V K R (0805) 30000284
Q102 TR BC327 30001452 C11 CAP SMD 1NF 50V K R (0805) 30000284
R100 RES SMD 1/10W 6.8K J 0805 30000778 C12 CAP SMD 1NF 50V K R (0805) 30000284
R101 RES SMD 1/10W 100R J 30000464 R6 RES SMD 1/10W 1K J 0805 30000469
R102 RES SMD 1/10W 1.2K J (0805) 30000499 R7 RES SMD 1/10W 15K J (0805) 30000534
R103 RES SMD 1/10W 68R J 30002731 R8 RES SMD 1/10W 15K J (0805) 30000534
R104 RES SMD 1/10W 10K J 0805 30000475 R5 RES SMD 1/10W 75R J (0805) 30000797
R105 RES SMD 1/10W 47K J (0805) 30000727 PCB 16SC04-4 30017517
R106 RES SMD 1/10W 1.5R J (0805) 30000546 PL1 SOCKET SCART (SATELLITE) 30011596
X100 XTAL REZ 429KHZ (0.9MM) 30011443 CONN ASSY 10P 8CM 30015171
R/C DVB2 (SILVER) 20085209 VİDA C ZN YSMB M3*6 35000180
PCB 16UV04-1 30015100
SINGLE BATT.CONTACT (-) RC2000 35000006
SINGLE BATT.CONTACT (+) RC2000 35000007
DOUBLE BATTERY CONTACT UKV- 35000003
900
VİDA S C ZNSY YSMB 2.9*6.5 35000210
LENS RCDVB (I) 40006044
RUBBER PAD TRP38 (RCDVB) R01 40008432
BOTTOM COVER RCDVB (I) (SILVER) 40009550
BATTERY COVER RCDVB (I) (SILVER 40009561
TOP COVER RCDVB (I) UK750 DVB-2 40009562

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SERVICE MANUAL

BOARD LAYOUT
16PW04-5 Component Layer:

16PW04-5 Bottom Layer:

16MB04-E3 Top Layer:

16MB04-E3 Component Layer:

16MB04-E3 GND Layer:

16MB04-E3 VCC Layer:

16MB04-E3 Bottom Layer:

16FP05-2 Component Layer:

16FP05-2 Bottom Layer:

16FP06-2 Component Layer:

16FP06-2 Bottom Layer:

16FP07-4 Component Layer:

16FP07-4 Bottom Layer:

16SC04-4 Component Layer:

16SC04-4 Bottom Layer:

16UV04-1 Top Layer:

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SERVICE MANUAL

16UV04-1 Bottom Layer:

16UV04-1 Solder Layer:

Rev 1.0 12.06.03 15:46 Page 42