LTC4305

2-Channel,
2-Wire Bus Multiplexer with
Capacitance Buffering
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FEATURES DESCRIPTIO
■ 1:2 2-Wire Multiplexer/Switch The LTC®4305 is a 2-channel, 2-wire bus multiplexer with
■ Connect SDA and SCL Lines with 2-Wire Bus bus buffers to provide capacitive isolation between the
Commands upstream bus and downstream buses. Through software
■ Supply Independent Bidirectional Buffer for SDA control, the LTC4305 connects the upstream 2-wire bus
and SCL Lines Increases Fan-Out to any desired combination of downstream channels.
■ Programmable Disconnect from Stuck Bus Each channel can be pulled up to a supply voltage ranging
■ Compatible with I2C and SMBus Standards from 2.2V to 5.5V, independent of the LTC4305 supply
■ Rise Time Accelerator Circuitry voltage. The downstream channels are also provided with
■ SMBus Compatible ALERT Response Protocol an ALERT1–ALERT2 inputs for fault reporting.
■ Prevents SDA and SCL Corruption During Live Board
Programmable timeout circuitry disconnects the down-
Insertion and Removal from Backplane
stream buses if the bus is stuck low. When activated, rise
■ ±10kV Human Body Model ESD Ruggedness
time accelerators source currents into the 2-wire bus pins
■ 16-Lead (4mm × 5mm) DFN and SSOP Packages
to reduce rise time. Driving the ENABLE pin low restores
U all features to their default states. Three address pins
APPLICATIO S provide 27 distinct addresses.
■ Nested Addressing The LTC4305 is available in 16-lead (4mm × 5mm) DFN
■ 5V/3.3V Level Translator and SSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
■ Capacitance Buffer/Bus Extender trademarks are the property of their respective owners. Patent Pending.

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TYPICAL APPLICATIO
A Level-Shifting and Nested Addressing Application
2.5V 3.3V
I2C Bus Waveforms

0.01µF VCC = 3.3V

10k 10k 10k 10k 10k 10k VBACK = 2.5V

SCLIN
VCC 2V/DIV
SCLIN SCL1
MICRO- SDA1 SFP VCARD1 = 3.3V
SDAIN
CONTROLLER MODULE #1 SCL1
ALERT ALERT1 2V/DIV
ADDRESS = 1111 000
5V
LTC4305
VCARD2 = 5V
10k 10k 10k SCL2
ADR2
2V/DIV
ADR1 SCL2
SFP 4305 TA01b
ADR0 SDA2 500ns/DIV
MODULE #2
GND ALERT2
4305 TA01
ADDRESS = 1111 000
ADDRESS = 1000 100

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LTC4305
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ABSOLUTE AXI U RATI GS (Note 1)
Supply Voltage (VCC) ................................... –0.3V to 7V Operating Temperature Range
Input Voltages (ADR0, ADR1, ADR2, LTC4305C ............................................... 0°C to 70°C
ENABLE, ALERT1, ALERT2) .................... –0.3V to 7V LTC4305I ............................................. –40°C to 85°C
Output Voltages (ALERT, READY) ............... –0.3V to 7V Storage Temperature Range
Input/Output Voltages (SDAIN, SCLIN, DHD Package .................................... –65°C to 125°C
SCL1, SDA1, SCL2, SDA2) ...................... –0.3V to 7V GN Package ....................................... –65°C to 150°C
Output Sink Current (SDAIN, SCLIN, SCL1, Lead Temperature (Soldering, 10 sec)
SDA1, SCL2, SDA2, ALERT, READY) ............... 10mA GN Package ...................................................... 300°C

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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ALERT2 1 16 SCL2
ALERT2 1 16 SCL2
ALERT 2 15 SDA2
ALERT 2 15 SDA2
SDAIN 3 14 ALERT1
SDAIN 3 14 ALERT1
GND 4 13 SDA1
17 GND 4 13 SDA1
SCLIN 5 12 SCL1
SCLIN 5 12 SCL1
ENABLE 6 11 READY
ENABLE 6 11 READY
VCC 7 10 ADR2
VCC 7 10 ADR2
ADRO 8 9 ADR1
ADR0 8 9 ADR1
DHD PACKAGE
16-LEAD (4mm × 5mm) PLASTIC DFN GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
EXPOSED PAD (PIN 17) PCB CONNECTION OPTIONAL
MUST BE CONNECTED TO PCB TO OBTAIN TJMAX = 125°C, θJA = 135°C/W
θJA = 43°C/W OTHERWISE θJA = 140°C/W. TJMAX = 125°C

ORDER PART NUMBER DHD PART MARKING ORDER PART NUMBER GN PART MARKING
LTC4305CDHD 4305 LTC4305CGN 4305
LTC4305IDHD 4305 LTC4305IGN 4305I
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marketing: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply/Start-Up
VCC Input Supply Range ● 2.7 5.5 V
ICC Input Supply Current Downstream Connected, VCC = 5.5V ● 5.2 8 mA
SCL Bus Low, SDA Bus High
ICC ENABLE = 0V Input Supply Current VENABLE = 0V, VCC = 5.5V ● 1.25 2.5 mA
VUVLOU UVLO Upper Threshold Voltage ● 2.3 2.5 2.7 V
VUVLOHYST UVLO Threshold Hysteresis Voltage ● 100 175 250 mV
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 LTC4305
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply/Start-Up
VTH EN ENABLE Falling Threshold Voltage ● 0.8 1.0 1.2 V
VEN HYST ENABLE Threshold Hysteresis Voltage 60 mV
tPHL EN ENABLE Delay, On-Off 60 ns
tPLH EN ENABLE Delay, Off-On 20 ns
IIN EN ENABLE Input Leakage Current VENABLE = 0V, 5.5V, VCC = 5.5V ● 0.1 ±1 µA
VLOW READY READY Pin Logic Low Output Voltage IPULL-UP = 3mA, VCC = 2.7V ● 0.18 0.4 V
IOFF READY READY Off State Input Leakage Current VREADY = 0V, 5.5V, VCC = 5.5V ● 0 ±1 µA
ALERT
VALERT(OL) ALERT Output Low Voltage IALERT = 3mA, VCC = 2.7V ● 0.2 0.4 V
IOFF, ALERT ALERT Off State Input Leakage Current VALERT = 0V, 5.5V ● 0 ±1 µA
IIN, ALERT1–2 ALERT1–ALERT2 Input Current VALERT1–2 = 0V, 5.5V ● 0 ±1 µA
VALERT1–2(IN) ALERT1–ALERT2 Pin Input Falling 0.8 1.0 1.2 V
Threshold Voltages ●
VALERT1–2(HY) ALERT1–ALERT2 Pin Input Threshold 80 mV
Hysteresis Voltages
Rise Time Accelerators
VSDA,SCL slew Initial Slew Requirement to Activate SDAIN, SCLIN, SDA1–2, 0.4 0.8 V/µs
Rise Time Accelerator Currents SCL1–2 Pins ●
VRISE,DC Rise Time Accelerator DC Threshold Voltage SDAIN, SCLIN, SDA1–2, 0.7 0.8 1 V
SCL1–2 Pins ●
IBOOST Rise Time Accelerator Pull-Up Current SDAIN, SCLIN, SDA1–2, 4 5.5 mA
SCL1–2 Pins (Note 3)
Stuck Low Timeout Circuitry
VTIMER(L) Stuck Low Falling Threshold Voltage VCC = 2.7V, 5.5V ● 0.4 0.52 0.64 V
VTIMER(HYST) Stuck Low Threshold Hysteresis Voltage 80 mV
TTIMER1 Timeout Time #1 TIMSET1,0 = 01 ● 25 30 35 ms
TTIMER2 Timeout Time #2 TIMSET1,0 = 10 ● 12.5 15 17.5 ms
TTIMER3 Timeout Time #3 TIMSET1,0 = 11 ● 6.25 7.5 8.75 ms
Upstream-Downstream Buffers
VOS,BUF Buffer Offset Voltage RBUS = 10k, VCC = 2.7V, 5.5V (Note 4) ● 25 60 100 mV
VOS,UP-BUF Upstream Buffer Offset Voltage VCC = 2.7V, RBUS = 2.7k (Note 4) ● 40 80 120 mV
VIN,BUFFER = 0V VCC = 5.5V, RBUS = 2.7k (Note 4) ● 70 110 150 mV
VOS,DOWN-BUF Downstream Buffer Offset Voltage VCC = 2.7V, RBUS = 2.7k (Note 4) ● 60 110 160 mV
VIN,BUFFER = 0V VCC = 5.5V, RBUS = 2.7k (Note 4) ● 80 140 200 mV
VOL Output Low Voltage, VIN,BUFFER = 0V SDA, SCL Pins; ISINK = 4mA, ● 400 mV
VCC = 3V, 5.5V
VOL Output Low Voltage, VIN,BUFFER = 0.2V SDA, SCL Pins; ISINK = 500µA, ● 320 mV
VCC = 2.7V, 5.5V
VIL,MAX Buffer Input Logic Low Voltage VCC = 2.7V, 5.5V ● 0.4 0.52 0.64 V
VTHSDA,SCL Downstream SDA, SCL Logic Threshold Voltage ● 0.8 1.0 1.2 V
ILEAK Input Leakage Current SDA, SCL Pins; ● ±5 µA
VCC = 0 to 5.5V;
Buffers Inactive
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LTC4305
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I2C Interface
VADR(H) ADR0–2 Input High Voltage ● 0.75 • VCC 0.9 • VCC V
VADR(L) ADR0–2 Input Low Voltage ● 0.1 • VCC 0.25 • VCC V
IADR(IN, L) ADR0–2 Logic Low Input Current ADR0–2 = 0V, VCC = 5.5V ● –30 –60 –80 µA
IADR(IN, H) ADR0–2 Logic High Input Current ADR0–2 = VCC = 5.5V ● 30 60 80 µA
IADR,FLOAT ADR0–2 Allowed Input Current VCC = 2.7V, 5.5V (Note 5) ● ±5 ±13 µA
VSDAIN,SCLIN(TH) SDAIN, SCLIN Input Falling Threshold Voltages VCC = 5.5V ● 1.4 1.6 1.8 V
VSDAIN,SCLIN(HY) SDAIN, SCLIN Hysteresis 30 mV
ISDAIN,SCLIN(OH) SDAIN, SCLIN Input Current SCL, SDA = VCC ● ±5 µA
CIN SDA, SCL Input Capacitance (Note 2) 6 10 pF
VSDAIN(OL) SDAIN Output Low Voltage ISDA = 4mA, VCC = 2.7V ● 0.2 0.4 V
I2C Interface Timing
fSCL Maximum SCL Clock Frequency (Note 2) 400 kHz
tBUF Bus Free Time Between Stop/Start Condition (Note 2) 0.75 1.3 µs
tHD, STA Hold Time After (Repeated) Start Condition (Note 2) 45 100 ns
tSU, STA Repeated Start Condition Set-Up Time (Note 2) –30 0 ns
tSU, STO Stop Condition Set-Up Time (Note 2) –30 0 ns
tHD, DATI Data Hold Time Input (Note 2) –25 0 ns
tHD, DATO Data Hold Time Output (Note 2) 300 600 900 ns
tSU, DAT Data Set-Up Time (Note 2) 50 100 ns
tf SCL, SDA Fall Times (Note 2) 20 + 0.1 • 300 ns
CBUS
tSP Pulse Width of Spikes Suppressed by the (Note 2) 50 150 250 ns
Input Filter
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 4: When a logic low voltage VLOW is forced on one side of the
of a device may be impaired. upstream-downstream buffers, the voltage on the other side is regulated
Note 2: Guaranteed by design and not subject to test, unless stated to a voltage VLOW2 = VLOW + VOS is a positive offset voltage. VOS,DOWN-BUF
otherwise in the Conditions. is the offset voltage when the LTC4305 is driving the upstream pin (e.g.,
Note 3: The boosted pull-up currents are regulated to prevent excessively SDAIN) and VOS,DOWN-BUF is the offset voltage when the LTC4305 is
fast edges for light loads. See the Typical Performance Characteristics for driving the downstream pin (e.g., SDA1). See the Typical Performance
rise time as a function of VCC and parasitic bus capacitance CBUS and for Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a function of VCC and
IBOOST as a function of VCC and temperature. bus pull-up current.
Note 5: When floating, the ADR0–ADR2 pins can tolerate pin leakage
currents up to IADR,FLOAT and still convert the address correctly.

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TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C unless otherwise specified.)

Buffer Circuitry tPHL

vs Temperature Rise Time vs CBUS vs VCC ICC vs Temperature
120 250 6
dV = 0.3V • VCC TO 0.7V • VCC
VCC = 5V
RBUS = 10k
100 5
200
VCC = 3.3V
VCC = 3.3V VCC = 3.3V
80 4

CURRENT (mA)
VCC = 5V

RISE TIME (ns)

VCC = 5V 150
tPHL (ns)

60 3
100
40 2

20 50
1
UPSTREAM CONNECTED TO CHANNEL 1,
SCL BUS LOW, SDA BUS HIGH
0 0 0
–50 –25 0 25 50 75 100 125 0 200 400 600 800 1000 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) CAPACITANCE, CBUS (pF) TEMPERATURE (°C)
4305 G01 4305 G02 4305 G03

VOS,DOWN-BUF
VOS,UP-BUF vs Bus Pull-Up Current vs Bus Pull-Up Current
180 300
160
250
140

120 200
VCC = 3.3V
VOS (mV)

VOS (mV)

100 VCC = 3.3V

VCC = 5V 150
80 VCC = 5V

60 100
40
50
20

0 0
0 1 2 3 4 0 1 2 3 4
BUS PULL-UP CURRENT (mA) BUS PULL-UP CURRENT (mA)
4305 G04 4305 G05

Downstream RFET on Resistance

vs VCC and Temperature IBOOST vs Temperature
45 14

40
12
35 VCC = 5V
10
30
IBOOST (mA)

VCC = 3.3V
8
RON (Ω)

25
VCC = 5V
20 6
15 VCC = 3.3V
4
10
2
5

0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
4305 G06 4305 G07

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LTC4305
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PI FU CTIO S
ALERT1–ALERT2 (Pins 14, 1): Fault Alert Inputs, VCC (Pin 7): Power Supply Voltage. Connect a bypass
Channels 1–2. Devices on each of the two output channels capacitor of at least 0.01µF directly between VCC and GND
can pull their respective pin low to indicate that a fault has for best results.
occurred. The LTC4305 then pulls the ALERT low to pass ADR0–ADR2 (Pins 8–10): Three-State Serial Bus
the fault indication on to the host. See the “Operation” Address Inputs. Each pin may be floated, tied to ground,
section below for the details of how ALERT is set and or tied to VCC. There are therefore 27 possible addresses.
cleared. Connect unused fault alert inputs to VCC. See Table 1 in Applications Information section. When the
ALERT (Pin 2): Fault Alert Output. An open-drain output pins are floated, they can tolerate ±5µA of leakage current
that is pulled low when a fault occurs to alert the host and still convert the address correctly.
controller. The LTC4305 pulls ALERT low when any of the READY (Pin 11): Connection Ready Digital Output. An
ALERT1–ALERT2 pins is low; when the two-wire bus is N-channel MOSFET open-drain output transistor that pulls
stuck low; or when the Connection Requirement bit of down when none of the downstream channels is con-
register 2 is low and a master tries to connect to a nected to the upstream bus and turns off when one or
downstream channel that is low. See the “Operation” more downstream channels is connected to the upstream
section below for the details of how ALERT is set and bus. Connect a 10k resistor to a power supply voltage to
cleared. The LTC4305 is compatible with the SMBus Alert provide the pull-up. Tie to ground if unused.
Response Address protocol. Connect a 10k resistor to a
power supply voltage to provide the pull-up. Tie to ground SCL1–SCL2 (Pins 12, 16): Serial Bus Clock Outputs
if unused. Channels 1–2. Connect pins SCL1–SCL2 to the SCL lines
on the downstream channels 1–2, respectively. It is ac-
SDAIN (Pin 3): Serial Bus Data Input and Output. Connect ceptable to float any pin that will never be connected to the
this pin to the SDA line on the master side. An external upstream bus. Otherwise, an external pull-up resistor or
pull-up resistor or current source is required. current source is required on each pin.
GND (Pin 4): Device Ground. SDA1–SDA2 (Pins 13, 15): Serial Bus Data Output
SCLIN (Pin 5): Serial Bus Clock Input. Connect this pin to Channels 1–2. Connect pins SDA1–SDA2 to the SDA lines on
the SCL line on the master side. An external pull-up downstream channels 1–2, respectively. It is acceptable
resistor or current source is required. to float any pin that will never be connected to the
upstream bus. Otherwise, an external pull-up resistor or
ENABLE (Pin 6): Digital Interface Enable and Register
current source is required on each pin.
Reset. Driving ENABLE high enables I2C communication
to the LTC4305. Driving ENABLE low disables I2C com- Exposed Pad (Pin 17, DHD Package Only): Exposed pad
munication to the LTC4305 and resets the registers to may be left open or connected to device ground.
their default state as shown in the Operations section.
When ENABLE returns high, masters can read and write
the LTC4305 again. If unused, tie ENABLE to VCC.

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 LTC4305
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BLOCK DIAGRA
INACC UPSTREAM OUTACC
DOWNSTREAM
SLEW RATE SLEW RATE
BUFFERS
DETECTOR DETECTOR

SDAIN 3 13 SDA1

15 SDA2

DOWNSTREAM
INACC UPSTREAM OUT ACC 1V THRESHOLD
2 COMPARATORS
DOWNSTREAM
SLEW RATE SLEW RATE
BUFFERS
DETECTOR DETECTOR

SCLIN 5 12 SCL1

STUCK LOW 0.52V

16 SCL2
COMPARATORS

READY 11

FET1 FET2

CONN 14 ALERT1
ALERT
FET1 1V THRESHOLD 1 ALERT2
COMPARATORS
SCLIN + 100ns FET2
2

1.6V/1.52V – GLITCH FILTER

AL1-AL2
TIMSET1 STUCK LOW
SDAIN + 100ns TIMEOUT 2 ALERT
TIMSET0
GLITCH FILTER CIRCUITRY FET1
– TIMEOUT_REAL
FET2 ALERT LOGIC
TIMEOUT_LATCH
VCC
2 CH1CONN-CH2CONN
RLIM CONNECTION UVLO
C1 50k CONN_REQ CIRCUITRY
2-WIRE
2pF DIGITAL 4 GND
INTERFACE FAILCONN_ATTEMPT
AND
REGISTERS
2 BUS1_LOG-BUS2_LOG

2
AL1-AL2
VCC 7 + 1µs UVLO PORB ADDRESS
2.5V/2.35V – FILTER FIXED BITS
“10” 10 ADR2
5 I2C ADDR 5
ENABLE 6 + 1 OF 27 9 ADR1
1.1V/1V – INACC 8 ADR0
OUTACC
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OPERATIO
Control Register Bit Definitions
Register 0 (00h) Register 1 (01h)
BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 Downstream R Indicates if upstream bus is connected d7 Upstream R/W Activates upstream rise time
Connected to any downstream buses Accelerators accelerator currents
0 = upstream bus disconnected from Enable 0 = upstream rise time accelerator
all downstream buses currents inactive (default)
1 = upstream bus connected to one or 1 = upstream rise time accelerator
more downstream buses currents active
d6 ALERT1 Logic State R Logic state of ALERT1 pin, noninverting d6 Downstream R/W Activates downstream rise time
d5 ALERT2 Logic State R Logic state of ALERT2 pin, noninverting Accelerators accelerator currents
Enable 0 = downstream rise time accelerator
d4 Reserved R Not Used currents inactive (default)
d3 Reserved R Not Used 1 = downstream rise time accelerator
d2 Failed Connection R Indicates if an attempt to connect to a currents active
Attempt downstream bus failed because the d5-d0 Reserved R Not Used
“Connection Requirement” bit in * For Type, “R/W” = Read Write, “R” = Read Only
Register 2 was low and the
downstream bus was low
0 = Failed connection attempt occurred
1 = No failed attempts at connection
occurred
d1 Latched Timeout R Latched bit indicating if a timeout has
occurred and has not yet been cleared.
0 = no latched timeout
1 = latched timeout
d0 Timeout Real Time R Indicates real-time status of Stuck Low
Timeout Circuitry
0 = no timeout is occurring
1 = timeout is occurring
Note: Masters write to Register 0 to reset the fault circuitry after a fault
has occurred and been resolved. Because Register 0 is Read-Only, no
other functionality is affected.
* For Type, “R/W” = Read Write, “R” = Read Only

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OPERATIO
Register 2 (02h) Register 3 (03h)
BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 Reserved R Not Used d7 Bus 1 FET State R/W Sets and indicates state of FET
d6 Reserved R Not Used switches connected to downstream
bus 1
d5 Connection R/W Sets logic requirements for 0 = switch open (default)
Requirement downstream buses to be connected 1 = switch closed
to upstream bus
0 = Bus Logic State bits (see register d6 Bus 2 FET State R/W Sets and indicates state of FET
3) of buses to be connected must be switches connected to downstream
high for connection to occur (default) bus 2
1 = Connect regardless of 0 = switch open (default)
downstream logic state 1 = switch closed
d4 Reserved R Not Used d5 Reserved R Not Used
d3 Reserved R Not Used d4 Reserved R Not Used
d2 Mass Write Enable R/W Enable Mass Write Address using d3 Bus 1 Logic State R Indicates logic state of downstream
address (1011 110)b bus 1; only valid when disconnected
0 = Disable Mass Write from upstream bus†
1 = Enable Mass Write (default) 0 = SDA1, SCL1 or both are below 1V
1 = SDA1 and SCL1 are both above
d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1** 1V
d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0** d2 Bus 2 Logic State R Indicates logic state of downstream
* For Type, “R/W” = Read Write, “R” = Read Only bus 2; only valid when disconnected
** from upstream bus†
TIMSET1 TIMSET0 TIMEOUT MODE 0 = SDA2, SCL2 or both are below 1V
1 = SDA2 and SCL2 are both above
0 0 Timeout Disabled (Default) 1V
0 1 Timeout After 30ms d1 Reserved R Not Used
1 0 Timeout After 15ms d0 Reserved R Not Used
1 1 Timeout After 7.5ms * For Type, “R/W” = Read Write, “R” = Read Only
† These bits are meant to give the logic state of disconnected downstream
buses to the master, so that the master can choose not to connect to a low
downstream bus. A given bit is a “don’t care” if its associated downstream
bus is already connected to the upstream bus.

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OPERATIO
The LTC4305 is a 2-channel 2-wire bus multiplexer/ stuck low. Masters can override this feature by setting the
switch with bus buffers to provide capacitive isolation Connection Requirement Bit of register 2 high. With this
between the upstream bus and downstream buses. Mas- bit high, the LTC4305 executes connection commands
ters on the upstream 2-wire bus (SDAIN and SCLIN) can without regard to the logic states of the downstream
command the LTC4305 to neither, either or both of the 2 channels.
downstream buses. Masters can also program the LTC4305
Upon receiving the connection command, the Connection
to disconnect the upstream bus from the downstream
Circuitry shown in the block diagram will activate the
buses if the bus is stuck low.
Upstream-Downstream Buffers under two conditions:
Undervoltage Lockout (UVLO) and ENABLE first, the master must be commanding connection to one
Functionality or more downstream channels, and second, there must be
no stuck low condition (see “Stuck Low Timeout Fault”
The LTC4305 contains undervoltage lockout circuitry that discussion that follows). If the connection command is
maintains all of its SDA, SCL and ALERT pins in high successful, the Upstream-Downstream Buffer circuitry
impedance states until the device has sufficient VCC sup- passes signals between the upstream bus and the con-
ply voltage to function properly. It also ignores any nected downstream buses. The LTC4305 also turns off its
attempts to communicate with it via the 2-wire buses in N-channel MOSFET open-drain pull-down on the READY
this condition. When the ENABLE pin voltage is low (below pin, so that READY can be pulled high by its external pull-
0.8V), all control bits are reset to their default high up resistor.
impedance states, and the LTC4305 ignores 2-wire bus
commands. However, with ENABLE low, the LTC4305 still Upstream-Downstream Buffers
monitors the ALERT1–ALERT2 pin voltages and pulls the
Once the Upstream-Downstream Buffers are activated,
ALERT pin low if any of ALERT1–ALERT2 is low. When
the functionality of the SDAIN and any connected down-
ENABLE is high, devices can read from and write to the
stream SDA pins is identical. A low forced on any con-
LTC4305.
nected SDA pin at any time results in all pins being low.
Connection Circuitry External devices must pull the pin voltages below 0.4V
worst-case with respect to the LTC4305’s ground pin to
Masters on the upstream SDAIN/SCLIN bus can write to ensure proper operation. The SDA pins enter a logic high
the Bus 1 FET State and Bus 2 FET State bits of register 3 state only when all devices on all connected SDA pins
to connect to any combination of downstream channels. force a high. The same is true for SCLIN and the connected
By default, the Connection Circuitry shown in the block downstream SCL pins. This important feature ensures
diagram will only connect to downstream channels whose that clock stretching, clock arbitration and the acknowl-
corresponding Bus Logic State bits in register 3 are high edge protocol always work, regardless of the how the
at the moment that it receives the connection command. devices in the system are connected to the LTC4305.
If the LTC4305 is commanded to connect to multiple
channels at once, it will only connect to the channels that The Upstream-Downstream Buffers provide capacitive
are high. This prevents the master on the upstream bus isolation between SDAIN/SCLIN and the downstream
from connnecting to a downstream channel that may be connected buses. Note that there is no capacitive isolation
between connected downstream buses; they are only

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 LTC4305
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OPERATIO
separated by the series combination of their switches’ on first, the pin’s voltage is rising at a minimum slew rate of
resistances. While neither, either or both downstream 0.8V/µs; second, the voltages on both the upstream bus
buses may be connected at the same time, logic high and the connected downstream buses exceed 0.8V.
levels are corrupted if both downstream buses are active
Note that a downstream bus must be connected to the
and both the VCC voltage and one downstream bus pull-up
upstream bus in order for its rise time accelerator current
voltage are larger than the pull-up supply voltage of the to be active. See the Applications Section for choosing a
other downstream bus. An example of this issue is shown bus pull-up resistor value to ensure that the rise time
in Figure 1. During logic highs, DC current flows from accelerator switches turn on. Do not activate boost cur-
VBUS1 through the series combination of R1, N1, N2 and rents on a bus whose pull-up supply voltage VBUS < VCC.
R2 and into VBUS2, causing the SDA1 voltage to drop and Doing so would cause the boost currents to source
current to be sourced into VBUS2. To avoid this problem,
current from VCC into the VBUS supply during rising
do not activate bus 1 when bus 2 is active.
edges.
VCC = VBUS1 = 5V
Downstream Bus Connection Fault
R1
SDA1 10k By default, the LTC4305 will only connect to downstream
N1
buses whose SDA and SCL pins are both high (above 1V)
VBUS2 = 2.5V
at the moment that it receives the connection command.
In this case, the LTC4305 sets the Failed Connection
R2
SDA2 10k Attempt bit of register 0 low and pulls the ALERT low when
N2
the master tries to connect to a low downstream bus. Note
4305 F01
that users can write a high to the Connection Requirement
Figure 1. Example of Unacceptable Level Shifting bit of register 2 to program the LTC4305 to connect to
Rise Time Accelerators downstream buses regardless of their logic state at the
moment of connection. In this case, the Downstream
The Upstream Accelerators Enable and Downstream Ac- Channel Connection Fault never occurs.
celerators Enable bits of register 1 activate the upstream
and downstream rise time accelerators, respectively. When Stuck Low Timeout Fault
activated, the accelerators turn on in a controlled manner
The Stuck Low Timeout Circuitry monitors the two com-
and source current into the pins during positive bus
mon internal nodes of the downstream SDA and SCL
transitions.
switches and runs a timer whenever either of the internal
When no downstream buses are connected, an upstream node voltages is below 0.52V. The timer is reset whenever
accelerator turns on when its pin voltage exceeds 0.8V both internal node voltages are above 0.6V. If the timer
and is rising at a minimum slew rate of 0.8V/µs. When one ever reaches the time programmed by Timeout Mode Bits
or more downstream buses are connected, the accelera- 1 and 0 of register 2, the LTC4305 pulls ALERT low and
tor on a given pin turns on when these conditions are met:

4305f

11
LTC4305
U
OPERATIO ALERT
FAULT ON DISCONNECTED
disconnects the downstream buses from the upstream DOWNSTREAM BUS
DOWNSTREAM BUS VCC
bus by de-biasing the Upstream-Downstream Buffers. CONNECTION FAULT
D Q
Note that the downstream switches remain in their exist- WRITE
REGISTER 0 RD
ing state. The Timeout Real Time bit of register 0 indicates ADDRESS LTC4305
FAULT ON CONNECTED
DOWNSTREAM BUS

the real-time status of the stuck low situation. The Latched LTC4305 RESPONDS
TO ARA
Timeout Bit of register 0 is a latched bit that is set high STUCK BUS
when a timeout occurs. VCC

D Q
WRITE
External Faults on the Downstream Channels REGISTER 0 RD
4305 F02

When a slave on downstream channel 1 pulls the ALERT1

pin below 1V, the LTC4305 passes this information to Figure 2. Setting and Resetting the ALERT Pin
master on the upstream bus by pulling the ALERT pin low.
The functionality is the same for the slaves on down- occur on unconnected downstream buses are grouped
stream channel 2 and the ALERT2 pin. Each channel has together and generate a single signal to drive ALERT. The
its own dedicated fault bit in Register 0, so that masters Stuck Low Timeout Fault has its own dedicated pathway to
can read Register 0 to determine which channels have ALERT; however, once a stuck low occurs, another one
faults. will not occur until the first one is cleared. For these
reasons, once the master has established the LTC4305 as
ALERT Functionality and Fault Resolution the source of the fault, it should read register 0 to deter-
mine the specific problem, take action to solve the prob-
When a fault occurs, the LTC4305 pulls the ALERT pin low,
lem, and clear the fault promptly. All faults are cleared by
as described previously. The procedure for resolving
writing a dummy databyte to register 0, which is a read-
faults depends on the type of fault. If a master on the
only register.
upstream bus is communicating with devices on a down-
stream bus via the upstream-downstream buffer circuitry— For example, assume that a fault occurs, the master sends
channel 1, for example—and a device on this bus pulls the out the ARA, and the LTC4305 successfully writes
ALERT1 pin low, the LTC4305 acts transparently, and the its address onto SDAIN and releases its ALERT pin. The
master communicates directly with the device that caused master reads register 0 and learns that the ALERT2 logic
the fault via the Upstream-Downstream Buffer circuitry to state bit is low. The master now knows that a device on
resolve the fault. downstream bus 2 has a fault and writes to register 3 to
connect to bus 2, so that it can communicate with the
In all other cases, the LTC4305 communicates with the
source of the fault. At this point, the master writes to
master to resolve the fault. After the master broadcasts the
register 0 to clear the fault.
Alert Response Address (ARA), the LTC4305 will respond
with its address on the SDAIN line and release the ALERT I2C Device Addressing
pin. The ALERT line will also be released if the LTC4305 is
addressed by the master. Twenty-seven distinct bus addresses are configurable
using the three state ADR0, ADR1 and ADR2 pins. Table
The ALERT signal will not be pulled low again until a 1 shows the correspondence between pin states and
different type of fault has occurred or the original fault is addresses. Note that address bits a6 and a5 are internally
cleared and has occurred again. Figure 2 shows the details configured to 1 and 0, respectively. In addition, the
of how the fault latches and ALERT pin are set and reset. LTC4305 responds to two special addresses. Address
The Downstream Bus Connection Fault and faults that (1011 110) is a mass write used to write all LTC4305’s,

4305f

12
 LTC4305
U
OPERATIO
regardless of their individual address settings. The mass Glitch Filters
write can be masked by setting the mass write enable bit
The LTC4305 provides glitch filters on the SDAIN and
of register 2 to zero. Address (0001 100) is the SMBus SCLIN pins as required by the I2C Fast Mode (400kHz)
Alert Response Address. Figure 3 shows data transfer
Specification. The filters prevent signals of up to 50ns
over a 2-wire bus.
(minimum) time duration and rail-to-rail voltage magni-
Supported Commands tude from passing into the two-wire bus digital interface
circuitry.
Users must write to the LTC4305 using the SMBus Write
Byte protocol and read from it using the Read Byte Fall Time Control
protocol. During fault resolution, the LTC4305 also
Per the I2C Fast Mode (400kHz) Specification, the
supports the Alert Response Address protocol. The
two-wire bus digital interface circuitry provides fall time
formats for these protocols are shown in Figure 4. Users
control when forcing logic lows onto the SDAIN bus. The
must follow the Write Byte protocol exactly to write to the
fall time always meets the limits:
LTC4305; if a Repeated Start Bit is issued before a Stop
Bit, the LTC4305 ignores the attempted write, and its (20 + 0.1 • CB) < tf < 300ns
control bits remain in their preexisting state. When users where tf is the fall time in ns and CB is the equivalent bus
follow the WriteByte protocol exactly, the new data con- capacitance in pF. Whenever the upstream-downstream
tained in the Data Byte is written into the register selected buffer circuitry is active, its output signal will meet the fall
by r1 and r0 on the Stop Bit. time requirements, provided that its input signal meets the
fall time requirements.

SDA a6 - a0 d7 - d0 d7 - d0

SCL 1-7 8 9 1-7 8 9 1-7 8 9

S P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

CONDITION CONDITION
4305 F03

Figure 3. Data Transfer Over I2C/SMBus

1 7 1 1 8 1 8 1 1
START 10 a4 - a0 WR ACK XXXXXX r1 r0 ACK d7 - d0 ACK STOP
SLAVE S REGISTER S DATA S
ADDRESS 0 0 0 BYTE 0
WRITE BYTE PROTOCOL

1 7 1 1 8 1 1 7 1 1 8 1 1
START 10 a4 - a0 WR ACK XXXXXX r1 r0 ACK START 10 a4 - a0 RD ACK d7 - d0 ACK STOP
SLAVE S REGISTER S SLAVE S DATA M
ADDRESS 0 0 0 ADDRESS 1 0 BYTE 1
READ BYTE PROTOCOL

1 7 1 1 8 1 1
S 0001 100 Rd ACK DEVICE ADDRESS ACK P
S M
1 0 1
ALERT RESPONSE ADDRESS PROTOCOL 4305 F04

Figure 4. Protocols Accepted by LTC4305

4305f

13
LTC4305
U
OPERATIO
Table 1. LTC4305 I2C Device Addressing
HEX DEVICE LTC4305
DESCRIPTION ADDRESS BINARY DEVICE ADDRESS ADDRESS PINS
h a6 a5 a4 a3 a2 a1 a0 R/W ADR2 ADR1 ADR0
Mass Write BC 1 0 1 1 1 1 0 0 X X X
Alert Response 19 0 0 0 1 1 0 0 1 X X X
0 80 1 0 0 0 0 0 0 X L NC L
1 82 1 0 0 0 0 0 1 X L H NC
2 84 1 0 0 0 0 1 0 X L NC NC
3 86 1 0 0 0 0 1 1 X L NC H
4 88 1 0 0 0 1 0 0 X L L L
5 8A 1 0 0 0 1 0 1 X L H H
6 8C 1 0 0 0 1 1 0 X L L NC
7 8E 1 0 0 0 1 1 1 X L L H
8 90 1 0 0 1 0 0 0 X NC NC L
9 92 1 0 0 1 0 0 1 X NC H NC
10 94 1 0 0 1 0 1 0 X NC NC NC
11 96 1 0 0 1 0 1 1 X NC NC H
12 98 1 0 0 1 1 0 0 X NC L L
13 9A 1 0 0 1 1 0 1 X NC H H
14 9C 1 0 0 1 1 1 0 X NC L NC
15 9E 1 0 0 1 1 1 1 X NC L H
16 A0 1 0 1 0 0 0 0 X H NC L
17 A2 1 0 1 0 0 0 1 X H H NC
18 A4 1 0 1 0 0 1 0 X H NC NC
19 A6 1 0 1 0 0 1 1 X H NC H
20 A8 1 0 1 0 1 0 0 X H L L
21 AA 1 0 1 0 1 0 1 X H H H
22 AC 1 0 1 0 1 1 0 X H L NC
23 AE 1 0 1 0 1 1 1 X H L H
24 B0 1 0 1 1 0 0 0 X H H L
25 B2 1 0 1 1 0 0 1 X L H L
26 B4 1 0 1 1 0 1 0 X NC H L

4305f

14
 LTC4305
U U W U
APPLICATIO S I FOR ATIO
Design Example For larger bus capacitances, refer to equation (1) below.
The LTC4305 works with capacitive loads up to 2nF.
A typical LTC4305 application circuit is shown in Figure 5.
The circuit illustrates the level-shifting, multiplexer/switch Assume in Figure 5 that the total parasitic bus capacitance
and capacitance buffering features of the LTC4305. In this on SDA1 due to trace and device capacitance is 100pF. To
application, the LTC4305 VCC voltage and downstream ensure that the boost currents are active during rising
bus 1 are powered from 3.3V, downstream bus 2 is edges, the pull-up resistor must be strong enough to
powered from 5V, and the upstream bus is powered from cause the SDA1 pin voltage to rise at a rate of 0.8V/µs as
2.5V. The following sections describe a methodology for the pin voltage is rising above 0.8V. The equation is:
choosing the external components in Figure 5.
⎧ ⎡ ns ⎤ ⎫
SDA, SCL Pull-Up Resistor Selection ⎨( VBUSMIN – 0 . 8 V) • 1250 ⎢ ⎥ ⎬
⎣ V ⎦ ⎭ (1)
RPULL −UP,MAX [kΩ ] = ⎩
The pull-up resistors on the SDA and SCL pins must be CBUS [pF ]
strong enough to provide a minimum of 100µA pull-up
current, per the SMBus Specification. In most systems, where VBUSMIN is the minimum operating pull-up supply
the required minimum strength of the pull-up resistors is voltage, and CBUS is the bus parasitic capacitance. In our
determined by the minimum slew requirement to guaran- example, VBUS1 = VCC = 3.3V, and assuming ±10% supply
tee that the LTC4305’s rise time accelerators are activated tolerance, VBUS1MIN = 2.97V. With CBUS = 100pF,
during rising edges. At the same time, the pull-up value RPULL-UP,MAX = 27.1kΩ. Therefore, we must choose a
should be kept low to maximize the logic low noise margin pull-up resistor smaller (i.e., stronger pull-up) than 27.1k,
and minimize the offset voltage of the Upstream-Down- so a 10k resistor works fine.
stream Buffer circuitry. The LTC4305 is designed to
ALERT and READY Component Selection
function for a maximum DC pull-up current of 4mA. If
multiple downstream channels are active at the same time, The pull-up resistors on the ALERT and READY pins must
this means that the sum total of the pull-up currents from provide a maximum pull-up current of 3mA, so that the
these channels must be less than 4mA. At supply voltages LTC4305 is capable of holding the pins at logic low
of 2.7V and 5.5V, pull-up resistor values of 10k work well voltages below 0.4V.
for capacitive loads up to 215pF and 420pF, respectively.

VBACK = 2.5V VCC = VBUS1 = 3.3V

C1
R1 R2 R3 0.01µF R4 R5 R6
10k 10k 10k 7 10k 10k 10k
5 VCC
SCLIN
MICRO- 3 12
SDAIN SCL1
CONTROLLER 2 13 SFP
SDA1
ALERT MODULE #1
14
ALERT1
ADDRESS = 1111 000
VBUS2 = 5V
LTC4305

10 R7 R8 R9
ADR2 10k 10k 10k
9 16
ADR1 SCL2
8 15 SFP
ADR0 SDA2
4 1 MODULE #2
GND ALERT2
ADDRESS = 1111 001
ADDRESS = 1000 100 4305 F05

Figure 5. A Level Shifting Circuit

4305f

15
LTC4305
U U W U
APPLICATIO S I FOR ATIO
Level Shifting Considerations from the ENABLE pin and make the ENABLE pin the
shortest pin on the card connector, so that the ENABLE pin
In Figure 5, the LTC4305 VCC voltage is less than or equal
to both of the downstream bus pull-up voltages, so both remains at a constant logic low while all other pins are
connecting. This ensures that the LTC4305 remains in its
downstream buses can be active at the same time. Like-
default high impedance state and ignores connection
wise, the rise time accelerators can be turned on for the
downstream buses, but must never be activated on SCLIN transients on its SDAIN and SCLIN pins until they have
established solid contact with the backplane 2-wire bus.
and SDAIN, because doing so would result in significant
In addition, make sure that the ALERT card connector pin
current flow from VCC to VBACK during rising edges.
is shorter than the VCC pin, so that VCC establishes solid
Other Application Circuits contact with the I/O card pull-up supply pin and powers
the pull-up resistors on ALERT1–ALERT2 before ALERT
Figure 6 illustrates how the LTC4305 can be used to makes contact.
expand the number of devices in a system by using nested
addressing. Each I/O card contains a temperature sensor Figure 8 illustrates an alternate SDA and SCL hot-
having device address 1001 000. If both I/O cards were swapping technique, where the LTC4305 is located on the
plugged directly into the backplane, the two sensors backplane and an I/O card plugs into downstream channel
would require two unique addresses. However, if masters 2. Before plugging and unplugging the I/O card, make sure
use the LTC4305 in multiplexer mode, where only one that channel 2’s downstream switch is open, so that it does
downstream channel is connected at a time, then each not disturb any 2-wire transaction that may be occurring
I/O card can have a device with address 1001 000 and no at the moment of connection/disconnection. Note that
problems will occur. pull-up resistor R10 on ALERT2 should be located on the
backplane and not the I/O card to ensure proper operation
Figures 7 and 8 show two different methods for hot- of the LTC4305 when the I/O card is not present. The pull-
swapping I/O cards onto a live two-wire bus using the up resistors on SCL2 and SDA2—R8 and R9, respec-
LTC4305. The circuitry of Figure 7 consists of an LTC4305 tively—may be located on the I/O card, provided that
residing on the edge of an I/O card having two separate downstream bus 2 is never activated when the I/O card is
downstream buses. Connect a 200k resistor to ground not present. Otherwise, locate R8 and R9 on the backplane.

VCC

C1
0.01µF
R1 R2 R3 R4 R5 R6 R7
7
10k 10k 10k 10k 10k 10k 10k
5 VCC
SCLIN
MICRO-
CONTROLLER 3 12
SDAIN SCL1
6 13 TEMPERATURE
ENABLE SDA1
14 SENSOR
2 ALERT1
ALERT
LTC4305 ADDRESS = 1001 000
11
READY I/O CARD #1
10
VCC ADR2 R8 R9 R10
10k 10k 10k
9 16
OPEN ADR1 SCL2
15 TEMPERATURE
SDA2
1 SENSOR
8 ALERT2
ADR0
4 ADDRESS = 1001 000
GND I/O CARD #2
ADDRESS = 1010 000 4305 F06

Figure 6. Nested Addressing Application

4305f

16
 LTC4305
U U W U
APPLICATIO S I FOR ATIO
VCC

C1
0.01µF
R1 R2 R5 R6 R7
10k 10k 7 10k 10k 10k
VCC 12
SCL1 CARD_SCL1
5 13
SCLIN SDA1 CARD_SDA1
MICRO- 14
ALERT1 CARD_ALERT1#
CONTROLLER 3
SDAIN
VCC
6 VBUS2
ENABLE
R8 R9 R10
VCC R4 10k 10k 10k
16
200k SCL2 CARD_SCL2
R3 15
SDA2 CARD_SDA2
10k 2 1
ALERT ALERT2 CARD_ALERT2#
LTC4305

VCC R11
10k
10 11
ADR2 READY

9
OPEN ADR1

8
ADR0

4
GND
4305 F07

BACKPLANE BACKPLANE CARD ADDRESS = 1010 000

CONNECTOR CONNECTOR

Figure 7. Hot-Swapping Application

4305f

17
LTC4305
U
PACKAGE DESCRIPTIO
DHD Package
16-Lead Plastic DFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1707)

0.70 ±0.05

4.50 ±0.05
3.10 ±0.05
2.44 ±0.05
(2 SIDES)

PACKAGE
OUTLINE

0.25 ± 0.05
0.50 BSC
4.34 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115 0.40 ± 0.10

5.00 ±0.10
TYP
(2 SIDES)
9 16
R = 0.20
TYP

4.00 ±0.10 2.44 ± 0.10

(2 SIDES) (2 SIDES)

PIN 1 PIN 1
TOP MARK NOTCH
(SEE NOTE 6)
(DHD16) DFN 0504

8 1
0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 BSC
4.34 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

4305f

18
 LTC4305
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Narrow Plastic SSOP
(Reference LTC DWG # 05-08-1641)

.045 ±.005 .189 – .196*

(4.801 – 4.978)
.009
(0.229)
16 15 14 13 12 11 10 9 REF

.254 MIN .150 – .165

.229 – .244 .150 – .157**

(5.817 – 6.198) (3.810 – 3.988)

.0165 ± .0015 .0250 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8

.015 ± .004
× 45° .0532 – .0688 .004 – .0098
(0.38 ± 0.10)
(1.35 – 1.75) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: TYP BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

4305f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4305
U
TYPICAL APPLICATIO
VCC

C1
0.01µF
R1 R2 R3 R4 R5 R6 R7
10k 10k 10k 10k 10k 10k 10k
VCC
SCLIN

SDAIN
MICRO- SCL1
CONTROLLER ENABLE TEMPERATURE
SDA1
SENSOR
ALERT ALERT1

READY
LTC4305

VCC2

VCC
R8 R9 R10
ADR2 10k 10k 10k
SCL2
OPEN ADR1 VOLTAGE
SDA2
MONITOR
ADR0 ALERT2
I/O CARD
GND 4305 F08

ADDRESS = 1010 000

Figure 8. Alternate Hot-Swapping Application

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ThinSOT is a trademark of Linear Technology Corporation.
4305f
LT/LWI/TP 0805 500 • PRINTED IN USA
Linear Technology Corporation
20 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
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