TABLE 4.
1
BJT Bias Configurations
Type Configuration Pertinent Equations
Fixed-bias VCC
VCC - VBE
RC IB =
RB RB
IC = bIB, IE = (b + 1)IB
VCE = VCC - IC RC
Emitter-bias VCC
RC VCC - VBE
RB IB =
RB + (b + 1)RE
IC = bIB, IE = (b + 1)IB
Ri = (b + 1)RE
VCE = VCC - IC (RC + RE)
RE
Voltage-divider VCC
bias
RC R2VCC APPROXIMATE: bRE Ú 10R2
R1 EXACT: RTh = R1||R2, ETh =
R1 + R2 R2VCC
VB = , VE = VB - VBE
ETh - VBE R1 + R2
IB =
RTh + (b + 1)RE VE IE
IE = , IB =
IC = bIB, IE = (b + 1)IB RE b + 1
R2
RE VCE = VCC - IC (RC + RE) VCE = VCC - IC (RC + RE)
Collector-feedback VCC
RC
RF
VCC - VBE
IB =
RF + b(RC + RE)
IC = bIB, IE = (b + 1)IB
VCE = VCC - IC (RC + RE)
RE
Emitter-follower
VEE - VBE
IB =
RB + (b + 1)RE
IC = bIB, IE = (b + 1)IB
RB
RE VCE = VEE - IE RE
–VEE
Common-base VEE - VBE
IE =
RE
RE RC IE
IB = , IC = bIB
– + b + 1
VEE VCC VCE = VEE + VCC - IE (RC + RE)
+ –
VCB = VCC - ICRC
193
TABLE 5.1
Unloaded BJT Transistor Amplifiers
Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k ) Medium (2 k ) High (-200) High (100)
VCC
Io = RB 7 bre = RC 7 ro (RC 7 ro) bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii
+ bre RC
Vo RC b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)
Voltage-divider Medium (1 k ) Medium (2 k ) High (-200) High (50)
bias: VCC
Io RC = R1 7 R2 7 bre = RC 7 ro R C 7 ro b(R1 7 R2)ro
R1 = - =
Ii
re (ro + RC)(R1 7 R2 + bre)
+ RC
+ Zo
(ro Ú 10RC) -
RC b(R1 7 R2)
Vo re
Vi Zi R2 R1 7 R2 + bre
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)
Unbypassed High (100 k ) Medium (2 k ) Low (- 5) High (50)
emitter bias: VCC
= RB 7 Zb = RC RC bRB
Io RC = - -
RB re + RE R B + Zb
Ii Zb b(re + RE) (any level of ro)
+
RB 7 bRE RC
+ Zo -
Vo RE
Vi (RE W re)
Zi RE
(RE W re)
– –
Emitter- High (100 k ) Low (20 ) Low ( 1) High (-50)
follower: VCC
= RB 7 Zb = RE 7 re RE bRB
Ii RB = -
RE + re RB + Zb
Zb b(re + RE)
+ re
RB 7 bRE 1
Vi
Zi Io RE + (RE W re)
Vo
– Zo (RE W re)
–
Common-base: Low (20 ) Medium (2 k ) High (200) Low (-1)
Ii
= R E 7 re = RC RC -1
+ Io RC + re
RE re
Vi Zi Zo Vo
VEE VCC
– – (RE W re)
Collector Medium (1 k ) Medium (2 k ) High (-200) High (50)
feedback: VCC
Io
RC re RC 7 RF RC bRF
RF = - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) (RF W RC) RC
Vi Z
– o
–
293
TABLE 6.3
Field Effect Transistors
Symbol and Input Resistance
Type Basic Relationships Transfer Curve and Capacitance
JFET
(n-channel)
Ri 7 100 M
Ci: (1 - 10) pF
MOSFET
depletion type
(n-channel)
Ri 7 1010
Ci: (1 - 10) pF
MOSFET
enhancement type
(n-channel)
Ri 7 1010
Ci: (1 - 10) pF
MESFET
depletion type
(n-channel)
Ri 7 1012
Ci: (1 - 5) pF
MESFET
enhancement type
(n-channel)
Ri 7 1012
Ci: (1 - 5) pF
TABLE 7.1
FET Bias Configurations
Type Configuration Pertinent Equations Graphical Solution
VDD ID
RD IDSS
JFET VGSQ = - VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS
ID
VDD
IDSS
RD
JFET VGS = -IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS
VDD ID
RD
R2VDD IDSS
JFET R1 VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS
VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point RS
Common-gate VDS = VDD + VSS - ID(RD + RS)
RS
–VSS VP 0 VSS VGS
ID
VDD VGS = -IDRS IDSS
RD
JFET VD = VDD
(RD = 0 ) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS
VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
RG
IDQ = IDSS Q
(VGSQ = 0 V)
VGG
VP 0 VGS
ID
VDD
Depletion-type Q-point
MOSFET VGSQ = + VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS
VG ID
Depletion-type VDD R2VDD
RD VG = RS Q-point
MOSFET R1
R1 + R2 IDSS
Voltage-divider
R2 VGS = VG - ISRS
bias RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS
VDD ID
Enhancement VDD
RD RD
type MOSFET RG ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th) VDD VGS
VGS(on)
Enhancement VDD VG ID
R2VDD RS
type MOSFET R1
RD
VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS
450
TABLE 8.1
Zi, Zo, and Av for various FET configurations
Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k ) Medium (-10)
RD
C2 High (10 M )
Vo = RD rd = - gm(rd RD)
C1
Vi = RG
Zo RD -gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k ) Medium (- 10)
[JFET or D-MOSFET] RD High (10 M )
C2
Vo = R D rd = -gm(rd RD)
C1 = RG
Vi RD -gmRD
Zo (rd Ú 10 RD) (rd Ú 10 RD)
Zi
RG
RS CS
Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (-2)
Self-bias +VDD RS
unbypassed RS c 1 + gmRS + dR
rd D gmRD
[JFET or D-MOSFET] RD High (10 M ) = =
C2 RS RD RD + RS
Vo c 1 + gmRS + + d 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd = -
RG 1 + gmRS
RS 3 rd Ú 10 (RD + RS) 4
Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k ) Medium (-10)
RD High (10 M )
C2
R1
Vo = RD rd = -gm(rd RD)
C1
Vi = R1 R2
Zo RD - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS
514
