H

Intelligent Power Module and

Gate Drive Interface Optocouplers
HCPL-4506
Technical Data HCPL-0466
HCNW4506

Features Applications gation delay difference between

• Performance Specified for • IPM Isolation devices make these optocouplers
Common IPM Applications • Isolated IGBT/MOSFET Gate excellent solutions for improving
over Industrial Temperature Drive inverter efficiency through
Range: -40°C to 100°C reduced switching dead time.
• AC and Brushless DC Motor
• Fast Maximum Propagation Drives
Delays An on chip 20 kΩ output pull-up
tPHL = 400 ns • Industrial Inverters resistor can be enabled by short-
tPLH = 550 ns ing output pins 6 and 7, thus
• Minimized Pulse Width Description eliminating the need for an
Distortion (PWD = 450 ns) The HCPL-4506 and HCPL-0466 external pull-up resistor in
• 15 kV/µs Minimum Common contain a GaAsP LED while the common IPM applications. Speci-
Mode Transient Immunity at HCNW4506 contains an AlGaAs fications and performance plots
VCM = 1500 V LED. The LED is optically are given for typical IPM
• CTR > 44% at IF = 10 mA coupled to an integrated high gain applications.
• Safety Approval photo detector. Minimized propa-
UL Recognized - 2500 V rms
for 1 minute (5000 V rms for Functional Diagram Truth Table
1 minute for HCNW4506 and
HCPL-4506 Option 020) per LED VO
NC 1 8 VCC
UL1577 ON L
CSA Approved 20 kΩ
OFF H
ANODE 2 7 VL
VDE 0884 Approved
-VIORM = 630 V peak for
HCPL-4506 Option 060 CATHODE 3 6 VO
-VIORM = 1414 V peak for
HCNW4506 4 5
NC GND
BSI Certified (HCNW4506) SHIELD

Selection Guide
Operating Temperature
TA [°C] Single Channel Packages
8-Pin DIP Small Outline Widebody
Min. Max. (300 Mil) SO-8 (400 Mil) Hermetic*
-40 100 HCPL-4506 HCPL-0466 HCNW4506
-55 125 HCPL-5300
HCPL-5301
*Technical data for these products are on separate HP publications.

The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.

5965-3603E 1-49
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4506#XXX
020 = UL 5000 V rms/1 Minute Option*
*For HCPL-4506 only. Combination of Option 020 and
060 = VDE 0884 VIORM = 630 V peak Option*
Option 060 is not available.
300 = Gull Wing Surface Mount Option† †Gull wing surface mount option applies to through
500 = Tape and Reel Packaging Option hole parts only.

Option data sheets are available. Contact your Hewlett-Packard sales representative or authorized
distributor for information.

Package Outline Drawings

9.65 ± 0.25 7.62 ± 0.25
(0.380 ± 0.010) (0.300 ± 0.010)

TYPE NUMBER 8 7 6 5 6.35 ± 0.25

OPTION CODE* (0.250 ± 0.010)
HP XXXXZ DATE CODE

YYWW RU
UL
1 2 3 4 RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.
+ 0.076
5° TYP. 0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

1.080 ± 0.320 0.65 (0.025) MAX. * MARKING CODE LETTER FOR OPTION NUMBERS.
(0.043 ± 0.013) "L" = OPTION 020
2.54 ± 0.25
(0.100 ± 0.010) "V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.

Figure 1. HCPL-4506 Outline Drawing (Standard DIP Package).

PAD LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25 1.016 (0.040)
(0.380 ± 0.010) 1.194 (0.047)
8 7 6 5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010) 9.398 (0.370)
9.906 (0.390)
1 2 3 4

0.381 (0.015)
1.194 (0.047) 0.635 (0.025)
1.778 (0.070)
1.780 9.65 ± 0.25
1.19 (0.070) (0.380 ± 0.010)
(0.047) MAX. 7.62 ± 0.25
MAX. (0.300 ± 0.010)

4.19 MAX. + 0.076

0.254 - 0.051
(0.165)
+ 0.003)
(0.010 - 0.002)

1.080 ± 0.320 0.635 ± 0.25

(0.043 ± 0.013) (0.025 ± 0.010)
0.635 ± 0.130 12° NOM.
2.54
(0.100) (0.025 ± 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

Figure 2. HCPL-4506 Gull Wing Surface Mount Option #300 Outline Drawing.

1-50
 8 7 6 5
5.842 ± 0.203
(0.236 ± 0.008)
XXX
3.937 ± 0.127 YWW TYPE NUMBER
(0.155 ± 0.005) (LAST 3 DIGITS)
DATE CODE
1 2 3 4

0.381 ± 0.076
(0.016 ± 0.003) 1.270 BSG
(0.050)

5.080 ± 0.127 7° 0.432

45° X (0.017)
(0.200 ± 0.005)

3.175 ± 0.127
(0.125 ± 0.005) 0.228 ± 0.025
1.524 (0.009 ± 0.001)
(0.060)

0.152 ± 0.051
(0.006 ± 0.002)
DIMENSIONS IN MILLIMETERS (INCHES). 0.305 MIN.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES). (0.012)

Figure 3. HCPL-0466 Outline Drawing (8-Pin Small Outline Package).

Pin Location (for reference only)

11.15 ± 0.15 11.00 MAX.
(0.442 ± 0.006) (0.433)
9.00 ± 0.15
8 7 6 5 (0.354 ± 0.006)
TYPE NUMBER
HP
HCNWXXXX DATE CODE

YYWW

1 2 3 4

10.16 (0.400)
TYP.
1.55
(0.061) 7° TYP. + 0.076
MAX. 0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)

3.10 (0.122)
3.90 (0.154) 0.51 (0.021) MIN.

2.54 (0.100)
TYP.
1.78 ± 0.15 0.40 (0.016)
(0.070 ± 0.006) 0.56 (0.022) DIMENSIONS IN MILLIMETERS (INCHES).

Figure 4a. HCNW4506 Outline Drawing (8-Pin Widebody Package).

11.15 ± 0.15
(0.442 ± 0.006) PAD LOCATION (FOR REFERENCE ONLY)

8 7 6 5
6.15 TYP.
(0.242)
9.00 ± 0.15
(0.354 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
1 2 3 4

1.3 0.9
(0.051) (0.035)
1.55
(0.061) 12.30 ± 0.30
MAX. (0.484 ± 0.012)
11.00 MAX.
(0.433)

4.00 MAX.
(0.158)

1.78 ± 0.15 1.00 ± 0.15

(0.070 ± 0.006) (0.039 ± 0.006)
2.54 0.75 ± 0.25 + 0.076
(0.030 ± 0.010) 0.254 - 0.0051
(0.100)
BSC + 0.003)
(0.010 - 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 7° NOM.

Figure 4b. HCNW4506 Outline Drawing (8-Pin Widebody Package with Gull Wing Surface Mount Option 300).

1-51
Solder Reflow Temperature Profile
260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
TEMPERATURE – °C

180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12
TIME – MINUTES

Note: Use of nonchlorine activated fluxes is recommended.

Regulatory Information CSA BSI

The devices contained in this data Approved under CSA Component Certification according to
sheet have been approved by the Acceptance Notice #5, File CA BS451:1994
following organizations: 88324. (BS EN60065:1994);
BS EN60950:1992
UL VDE (BS7002:1992) and
Recognized under UL 1577, Approved according to VDE EN41003:1993 for Class II
Component Recognition 0884/06.92 (HCNW4506 and applications (HCNW4506 only).
Program, File E55361. HCPL-4506 Option 060 only).

Insulation and Safety Related Specifications

8-Pin DIP Widebody
(300 Mil) SO-8 (400 Mil)
Parameter Symbol Value Value Value Units Conditions
Minimum External L(101) 7.1 4.9 9.6 mm Measured from input terminals
Air Gap (External to output terminals, shortest
Clearance) distance through air.
Minimum External L(102) 7.4 4.8 10.0 mm Measured from input terminals
Tracking (External to output terminals, shortest
Creepage) distance path along body.
Minimum Internal 0.08 0.08 1.0 mm Through insulation distance,
Plastic Gap conductor to conductor, usually
(Internal Clearance) the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
Minimum Internal NA NA 4.0 mm Measured from input terminals
Tracking (Internal to output terminals, along
Creepage) internal cavity.
Tracking Resistance CTI 200 200 200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative
Tracking Index)
Isolation Group IIIa IIIa IIIa Material Group
(DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

1-52
VDE 0884 Insulation Related Characteristics
(HCPL-4506 OPTION 060 ONLY)
Description Symbol Characteristic Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms I-IV
for rated mains voltage ≤ 450 V rms I-III
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 630 V peak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1181 V peak
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test, VPR 945 V peak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec) VIOTM 6000 V peak
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature TS 175 °C
Input Current IS,INPUT 230 mA
Output Power PS,OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS ≥ 109 Ω

VDE 0884 Insulation Related Characteristics (HCNW4506 ONLY)

Description Symbol Characteristic Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms I-IV
for rated mains voltage ≤ 1000 V rms I-III
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1414 V peak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 2652 V peak
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test, VPR 2121 V peak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec) VIOTM 8000 V peak
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature TS 150 °C
Input Current IS,INPUT 400 mA
Output Power PS,OUTPUT 700 mW
Insulation Resistance at TS, VIO = 500 V RS ≥ 109 Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.

1-53
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS -55 125 °C
Operating Temperature TA -40 100 °C
Average Input Current[1] IF(avg) 25 mA
Peak Input Current[2] (50% duty cycle, ≤ 1 ms pulse width) IF(peak) 50 mA
Peak Transient Input Current (<1 µs pulse width, 300 pps) IF(tran) 1.0 A
Reverse Input Voltage (Pin 3-2) HCPL-4506, HCPL-0466 VR 5 Volts
HCNW4506 3
Average Output Current (Pin 6) IO(avg) 15 mA
Resistor Voltage (Pin 7) V7 -0.5 VCC Volts
Output Voltage (Pin 6-5) VO -0.5 30 Volts
Supply Voltage (Pin 8-5) VCC -0.5 30 Volts
Output Power Dissipation[3] PO 100 mW
Total Power Dissipation[4] PT 145 mW
Lead Solder Temperature (HCPL-4506) 260°C for 10 s, 1.6 mm below seating plane
Lead Solder Temperature (HCNW4506) 260°C for 10 s (up to seating plane)
Infrared and Vapor Phase Reflow Temperature See Package Outline Drawings Section
(HCPL-0466 and Option 300)

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Power Supply Voltage VCC 4.5 30 Volts
Output Voltage VO 0 30 Volts
Input Current (ON) IF(on) 10 20 mA
Input Voltage (OFF) VF(off)* -5 0.8 V
Operating Temperature TA -40 100 °C
*Recommended VF(OFF) = -3 V to 0.8 V for HCNW4506.

Electrical Specifications
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V 5
Low Level Output Current IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V 5,6
Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA
Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 5 14
High Level Output Current IOH 5 50 µA VF = 0.8 V 7
High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 14
Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 14
Input Forward Voltage VF 1.5 1.8 V HCPL-4506 IF = 10 mA 8
HCPL-0466
1.6 1.85 HCNW4506 9
Temperature Coefficient ∆VF /∆TA -1.6 mV/°C HCPL-4506 IF = 10 mA
of Forward Voltage HCPL-0466
-1.3 HCNW4506
Input Reverse Breakdown BVR 5 V HCPL-4506 IR = 100 µA
Voltage HCPL-0466
3 HCNW4506
Input Capacitance CIN 60 pF HCPL-4506 f = 1 MHz,
HCPL-0466 VF = 0 V
72 HCNW4506
Internal Pull-up Resistor RL 14 20 25 kΩ TA = 25°C 10,11
Internal Pull-up Resistor ∆RL /∆TA 0.014 kΩ/°C
Temperature Coefficient
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCNW4506.

1-54
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPHL 30 200 400 ns CL = 100 pF IF(on) = 10 mA, 10, 9,
Time to Low VF(off) = 0.8 V, 12, 12,
Output Level 100 ns CL = 10 pF V = 15.0 V, 14-17 14
CC
Propagation Delay tPLH VTHLH = 2.0 V,
270 400 550 ns CL = 100 pF
Time to High VTHHL = 1.5 V
Output Level 130 CL = 10 pF
Pulse Width PWD 200 450 ns CL = 100 pF 18
Distortion
Propagation Delay tPLH-tPHL -150 200 450 ns 15
Difference Between
Any 2 Parts
Output High Level |CMH| 15 30 kV/µs IF = 0 mA, VCC = 15.0 V, 11 16
Common Mode VO > 3.0 V CL = 100 pF,
Transient Immunity VCM = 1500 VP-P
Output Low Level |CML| 15 30 kV/µs IF = 10 mA TA = 25°C 17
Common Mode VO < 1.0 V
Transient Immunity

Switching Specifications (RL = Internal Pull-up)

Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPHL 20 200 400 ns IF(on) = 10 mA, VF(off) = 0.8 V, 10, 9-12,
Time to Low VCC = 15.0 V, CL = 100 pF, 13 14
Output Level VTHLH = 2.0 V, VTHHL = 1.5 V
Propagation Delay tPLH 220 450 650 ns
Time to High
Output Level
Pulse Width PWD 250 500 ns 18
Distortion
Propagation Delay tPLH-tPHL -150 250 500 ns 15
Difference Between
Any 2 Parts
Output High Level |CMH| 30 kV/µs IF = 0 mA, VCC = 15.0 V, 11 16
Common Mode VO > 3.0 V CL = 100 pF,
Transient Immunity VCM = 1500 VP-P,
Output Low Level |CML| 30 kV/µs IF = 16 mA, TA = 25°C 17
Common Mode VO < 1.0 V
Transient Immunity
Power Supply PSR 1.0 VP-P Square Wave, tRISE, tFALL 14
Rejection > 5 ns, no bypass capacitors
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCNW4506.

1-55
Package Characteristics
Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.
Parameter Sym. Min. Typ.* Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO 2500 V rms HCPL-4506 RH < 50%, 6, 7, 8
Withstand Voltage† HCPL-0466 t = 1 min.
5000 HCNW4506 TA = 25°C 6, 8, 13
Option 020
5000 HCNW4506 6, 8
Resistance RI-O 10 12 Ω HCPL-4506 VI-O = 500 Vdc 6
(Input-Output) HCPL-0466
1012 1013 HCNW4506
Capacitance CI-O 0.6 pF HCPL-4506 f = 1 MHz 6
(Input-Output) HCPL-0466
0.5 HCNW4506
*All typical values at 25°C, VCC = 15 V.
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.

Notes: 8. For option 020, in accordance with 14. Use of a 0.1 µF bypass capacitor
1. Derate linearly above 90°C free-air UL 1577, each optocoupler is proof connected between pins 5 and 8 can
temperature at a rate of 0.8 mA/°C. tested by applying an insulation test improve performance by filtering
2. Derate linearly above 90°C free-air voltage ≥ 6000 V rms for 1 second power supply line noise.
temperature at a rate of 1.6 mA/°C. (leakage detection current limit, II-O 15. The difference between tPLH and tPHL
3. Derate linearly above 90°C free-air ≤ 5 µA). This test is performed before between any two devices under the
temperature at a rate of 3.0 mW/°C. the 100% Production test for partial same test condition. (See IPM Dead
4. Derate linearly above 90°C free-air discharge (method b) shown in the Time and Propagation Delay
temperature at a rate of 4.2 mW/°C. VDE 0884 Insulation Related Specifications section.)
5. CURRENT TRANSFER RATIO in Characteristics Table, if applicable. 16. Common mode transient immunity in
percent is defined as the ratio of 9. Pulse: f = 20 kHz, Duty Cycle = 10%. a Logic High level is the maximum
output collector current (IO) to the 10. The internal 20 kΩ resistor can be tolerable dVCM/dt of the common
forward LED input current (IF) times used by shorting pins 6 and 7 mode pulse, VCM, to assure that the
100. together. output will remain in a Logic High
6. Device considered a two-terminal 11. Due to tolerance of the internal state (i.e., VO > 3.0 V).
device: Pins 1, 2, 3, and 4 shorted resistor, and since propagation delay 17. Common mode transient immunity in
together and Pins 5, 6, 7, and 8 is dependent on the load resistor a Logic Low level is the maximum
shorted together. value, performance can be improved tolerable dVCM/dt of the common
7. In accordance with UL 1577, each by using an external 20 kΩ 1% load mode pulse, VCM, to assure that the
optocoupler is proof tested by resistor. For more information on output will remain in a Logic Low
applying an insulation test voltage how propagation delay varies with state (i.e., VO < 1.0 V).
≥ 3000 V rms for 1 second (leakage load resistance, see Figure 12. 18. Pulse Width Distortion (PWD) is
detection current limit, II-O ≤ 5 µA). 12. The RL = 20 kΩ, CL = 100 pF load defined as |tPHL - tPLH| for any given
This test is performed before the represents a typical IPM (Intelligent device.
100% Production test shown in the Power Module) load.
VDE 0884 Insulation Related 13. See Option 020 data sheet for more
Characteristics Table, if applicable. information.

1-56
 IOH – HIGH LEVEL OUTPUT CURRENT – µA
10 1.05 20.0
VF = 0.8 V

NORMALIZED OUTPUT CURRENT

VCC = VO = 4.5 V OR 30 V
IO – OUTPUT CURRENT – mA

8 1.00
15.0

6 0.95 4.5 V
30 V
10.0
4 0.90
IF = 10 mA
VO = 0.6 V VO = 0.6 V 5.0
2 100 °C 0.85
25 °C
-40 °C
0 0.80 0
0 5 10 15 20 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
IF – FORWARD LED CURRENT – mA TA – TEMPERATURE – °C TA – TEMPERATURE – °C

Figure 5. Typical Transfer Figure 6. Normalized Output Current Figure 7. High Level Output
Characteristics. vs. Temperature. Current vs. Temperature.

1000 100
IF – INPUT FORWARD CURRENT – mA

TA = 25°C
TA = 25 °C
IF – FORWARD CURRENT – mA

100 10
IF
IF
10 +
VF +
– 1 VF
–
1.0
0.1
0.1

0.01
0.01

0.001 0.001
1.10 1.20 1.30 1.40 1.50 1.60 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VF – FORWARD VOLTAGE – VOLTS VF – INPUT FORWARD VOLTAGE – V

Figure 8. HCPL-4506 and HCPL-0466 Figure 9. HCNW4506 Input Current

Input Current vs. Forward Voltage. vs. Forward Voltage.

1 8

20 kΩ 0.1 µF 20 kΩ
IF(ON) =10 mA
2 7 +
+ – If
5V VCC = 15 V tf tr
– VO
3 6 VOUT
90% 90%
CL *
4 5 VTHHL VTHLH
SHIELD 10% 10%

*TOTAL LOAD CAPACITANCE tPHL tPLH

Figure 10. Propagation Delay Test Circuit.

1-57
 1 8 VCM

20 kΩ 0.1 µF 20 kΩ δV = VCM
IF
2 7 δt ∆t
+ VCC = 15 V OV
B A –
∆t
3 6 VOUT
100 pF*
VO
4 5 VCC
+ SHIELD SWITCH AT A: IF = 0 mA
VFF *100 pF TOTAL
– CAPACITANCE VO
VOL
SWITCH AT B: IF = 10 mA

+
–

VCM = 1500 V

Figure 11. CMR Test Circuit. Typical CMR Waveform.

500 500 800

IF = 10 mA
IF = 10 mA
VCC = 15 V
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns

tP – PROPAGATION DELAY – ns
VCC = 15 V
CL = 100 pF IF = 10 mA
CL = 100 pF
400 RL = 20 kΩ (EXTERNAL) 400 RL = 20 kΩ VCC = 15 V
(INTERNAL) 600
CL = 100 pF
TA = 25 °C

300 300
tPLH tPLH 400 tPLH
tPHL tPHL tPHL

200 200
200

100 100
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 0 10 20 30 40 50
TA – TEMPERATURE – °C TA – TEMPERATURE – °C RL – LOAD RESISTANCE – K Ω

Figure 12. Propagation Delay with Figure 13. Propagation Delay with Figure 14. Propagation Delay vs. Load
External 20 kΩ RL vs. Temperature. Internal 20 kΩ RL vs. Temperature. Resistance.

1400 500
IF = 10 mA 1400 IF = 10 mA VCC = 15 V
tPLH
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns

tP – PROPAGATION DELAY – ns

VCC = 15 V CL = 100 pF CL = 100 pF

1200 tPHL
RL = 20 kΩ 1200 RL = 20 kΩ RL = 20 kΩ
TA = 25°C TA = 25°C 400 TA = 25°C
1000 1000
tPLH tPLH
tPHL tPHL
800 800
300
600 600

400 400 200

200 200

0 0 100
0 100 200 300 400 500 5 10 15 20 25 30 0 5 10 15 20
CL – LOAD CAPACITANCE – pF VCC – SUPPLY VOLTAGE – V IF – FORWARD LED CURRENT – mA

Figure 15. Propagation Delay vs. Load Figure 16. Propagation Delay vs. Figure 17. Propagation Delay vs. Input
Capacitance. Supply Voltage. Current.

1-58
 OUTPUT POWER – PS, INPUT CURRENT – IS
OUTPUT POWER – PS, INPUT CURRENT – IS

HCPL-4506 OPTION 060 HCNW4506

800 1000
PS (mW) PS (mW)
900 1 8
700 IS (mA) IS (mA)
800 20 kΩ
600 CLEDP
700 2 7
500
600
400 500
3 6
400 CLEDN
300
(230) 300
200 4 5
200 SHIELD
100
100
0 0
0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175
TS – CASE TEMPERATURE – °C TS – CASE TEMPERATURE – °C
Figure 20. Optocoupler Input to
Output Capacitance Model for
Unshielded Optocouplers.
Figure 18. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per VDE 0884.

1 8
20 kΩ
CLEDP
1 8 2 CLED02 7
20 kΩ 0.1 µF 20 kΩ CLED01
2 7 +
+5 V – VCC = 15 V 3 6
CLEDN
310 Ω
3 6 VOUT
4 5
CMOS 100 pF SHIELD

4 5
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 21. Optocoupler Input to
Output Capacitance Model for
Shielded Optocouplers.
Figure 19. Recommended LED Drive Circuit.

1 8
20 20 kΩ
ITOTAL* ICLEDP kΩ
2 CLED02 7
IF CLEDP
310 Ω CLED01
1 8
+5 V ICLED01
0.1 µF 20 kΩ VOUT
20 kΩ 3 6
2 7 + CLEDN
– VCC = 15 V 100 pF
310 Ω
4 5
3 6 VOUT SHIELD

CMOS 100 pF * THE ARROWS INDICATE THE DIRECTION OF CURRENT

FLOW FOR +dVCM/dt TRANSIENTS.
4 5
+
–

SHIELD
*100 pF TOTAL VCM
CAPACITANCE

Figure 22. LED Drive Circuit with Resistor Connected to LED Figure 23. AC Equivalent Circuit for Figure 22 During
Anode (Not Recommended). Common Mode Transients.

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 1 8
1 8
20 +5 V
CLEDP kΩ 20 kΩ
CLED02 20 kΩ
2 7
2 7
CLED01
310 Ω CLEDN VOUT
3 6
3 6
ICLEDN* Q1
100 pF
+ VR** –
4 5
SHIELD 4 5
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.

+ Figure 25. Not Recommended Open

–

VCM
Collector LED Drive Circuit.

Figure 24. AC Equivalent Circuit for Figure 19 During

Common Mode Transients.

1 8
20
CLEDP kΩ
20 kΩ
2 CLED02 7 1 8
CLED01 +5 V
20 kΩ
Q1 CLEDN VOUT
3 6 2 7
ICLEDN*
100 pF

4 5 3 6
SHIELD

* THE ARROWS INDICATE THE DIRECTION OF CURRENT 4 5

FLOW FOR +dVCM/dt TRANSIENTS. SHIELD

+
–

VCM

Figure 26. AC Equivalent Circuit for Figure 25 During Figure 27. Recommended LED Drive
Common Mode Transients. Circuit for Ultra High CMR.

HCPL-4506
1 8 VCC1

I 20 kΩ 0.1 µF IPM
LED1
+5 V 2 7 20 kΩ
+HV

310 Ω VOUT1
3 6
CMOS Q1
M
4 5
SHIELD

HCPL-4506 Q2
1 8 VCC2 HCPL-4506

I 20 kΩ 0.1 µF HCPL-4506 -HV

LED2
+5 V 2 7 20 kΩ
HCPL-4506

310 Ω VOUT2 HCPL-4506

3 6
CMOS HCPL-4506
4 5
SHIELD

Figure 28. Typical Application Circuit.

1-60
 ILED1

Q1 OFF
ILED1 VOUT1 Q1 ON
VOUT2
Q2 OFF
Q2 ON
Q1 OFF
VOUT1 Q1 ON
VOUT2 ILED2
Q2 OFF
Q2 ON tPLH
MIN.
tPLH
ILED2 MAX.
tPLH MAX. PDD* tPHL
MAX. MIN.
tPHL tPHL
MIN. MAX.
MAX.
PDD* MAX. = DEAD TIME
(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
*PDD = PROPAGATION DELAY DIFFERENCE = (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)

NOTE: THE PROPAGATION DELAYS USED TO CALCULATE = (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
PDD ARE TAKEN AT EQUAL TEMPERATURES. = PDD* MAX. - PDD* MIN.

Figure 29. Minimum LED Skew for Zero Dead Time. *PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.

Figure 30. Waveforms for Dead Time Calculation.

LED Drive Circuit (Figure 19), can achieve 15 kV/µs achieved by overdriving the LED
Considerations for Ultra CMR while minimizing component current beyond the input
High CMR Performance complexity. Note that a CMOS threshold so that it is not pulled
gate is recommended in Figure 19 below the threshold during a
Without a detector shield, the
to keep the LED off when the gate transient. The recommended
dominant cause of optocoupler
is in the high state. minimum LED current of 10 mA
CMR failure is capacitive coupling
provides adequate margin over
from the input side of the opto-
Another cause of CMR failure for the maximum ITH of 5.0 mA (see
coupler, through the package, to
a shielded optocoupler is direct Figure 5) to achieve 15 kV/µs
the detector IC as shown in CMR. Capacitive coupling is
Figure 20. The HCPL-4506, coupling to the optocoupler
output pins through CLEDO1 and higher when the internal load
HCPL-0466 and HCNW4506
CLEDO2 in Figure 21. Many factors resistor is used (due to CLEDO2)
improve CMR performance by
influence the effect and magni- and an IF = 16 mA is required to
using a detector IC with an optic-
tude of the direct coupling includ- obtain 10 kV/µs CMR.
ally transparent Faraday shield,
ing: the use of an internal or
which diverts the capacitively
coupled current away from the external output pull-up resistor, The placement of the LED current
the position of the LED current setting resistor effects the ability of
sensitive IC circuitry. However,
setting resistor, the connection of the drive circuit to keep the LED on
this shield does not eliminate the
the unused input package pins, during transients and interacts with
capacitive coupling between the
and the value of the capacitor at the direct coupling to the
LED and the optocoupler output
the optocoupler output (CL). optocoupler output. For example,
pins and output ground as shown
the LED resistor in Figure 22 is
in Figure 21. This capacitive
Techniques to keep the LED in connected to the anode. Figure 23
coupling causes perturbations in
the proper state and minimize the shows the AC equivalent circuit for
the LED current during common
effect of the direct coupling are Figure 22 during common mode
mode transients and becomes the
discussed in the next two transients. During a +dVcm/dt in
major source of CMR failures for
sections. Figure 23, the current available at
a shielded optocoupler. The main
the LED anode (Itotal) is limited by
design objective of a high CMR
CMR with the LED On the series resistor. The LED current
LED drive circuit becomes keep-
(CMRL ) (IF) is reduced from its DC value by
ing the LED in the proper state
A high CMR LED drive circuit an amount equal to the current that
(on or off) during common mode
must keep the LED on during flows through CLEDP and CLEDO1.
transients. For example, the
common mode transients. This is The situation is made worse
recommended application circuit

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because the current through CLEDO1 during a 15 kV/µs transient with specifications, preferably over the
has the effect of trying to pull the VCM = 1500 V. Additional margin desired operating temperature
output high (toward a CMR failure) can be obtained by adding a diode range.
at the same time the LED current is in parallel with the resistor, as
being reduced. For this reason, the shown by the dashed line connec- The limiting case of zero dead time
recommended LED drive circuit tion in Figure 24, to clamp the occurs when the input to Q1 turns
(Figure 19) places the current set- voltage across the LED below off at the same time that the input
ting resistor in series with the LED VF(OFF). to Q2 turns on. This case
cathode. Figure 24 is the AC equiv- determines the minimum delay
alent circuit for Figure 19 during Since the open collector drive cir- between LED1 turn-off and LED2
common mode transients. In this cuit, shown in Figure 25, cannot turn-on, which is related to the
case, the LED current is not keep the LED off during a +dVcm/ worst case optocoupler propagation
reduced during a +dVcm/dt tran- dt transient, it is not desirable for delay waveforms, as shown in
sient because the current flowing applications requiring ultra high Figure 29. A minimum dead time of
through the package capacitance is CMRH performance. Figure 26 is zero is achieved in Figure 29 when
supplied by the power supply. the AC equivalent circuit for Figure the signal to turn on LED2 is
During a -dVcm/dt transient, how- 25 during common mode delayed by (tPLH max - tPHL min) from
ever, the LED current is reduced by transients. Essentially all the the LED1 turn off. Note that the
the amount of current flowing current flowing through CLEDN propagation delays used to calcu-
through CLEDN. But, better CMR during a +dVcm/dt transient must late PDD are taken at equal temper-
performance is achieved since the be supplied by the LED. CMRH atures since the optocouplers under
current flowing in CLEDO1 during a failures can occur at dV/dt rates consideration are typically mounted
negative transient acts to keep the where the current through the LED in close proximity to each other.
output low. and CLEDN exceeds the input (Specifically, tPLH max and tPHL min
threshold. Figure 27 is an in the previous equation are not the
Coupling to the LED and output alternative drive circuit which does same as the tPLH max and tPHL min,
pins is also affected by the connec- achieve ultra high CMR over the full operating temperature
tion of pins 1 and 4. If CMR is performance by shunting the LED range, specified in the data sheet.)
limited by perturbations in the LED in the off state. This delay is the maximum value for
on current, as it is for the recom- the propagation delay difference
mended drive circuit (Figure 19), IPM Dead Time and specification which is specified at
pins 1 and 4 should be connected to Propagation Delay 450 ns for the HCPL-4506, HCPL-
the input circuit common. However, Specifications 0466 and HCNW4506 over an
if CMR performance is limited by The HCPL-4506, HCPL-0466 and operating temperature range of
direct coupling to the output when HCNW4506 include a Propagation -40°C to 100°C.
the LED is off, pins 1 and 4 should Delay Difference specification
be left unconnected. intended to help designers minimize Delaying the LED signal by the
“dead time” in their power inverter maximum propagation delay dif-
CMR with the LED Off designs. Dead time is the time ference ensures that the minimum
(CMRH) period during which both the high dead time is zero, but it does not
A high CMR LED drive circuit must and low side power transistors (Q1 tell a designer what the maximum
keep the LED off (VF ≤ VF(OFF)) and Q2 in Figure 28) are off. Any dead time will be. The maximum
during common mode transients. overlap in Q1 and Q2 conduction dead time occurs in the highly
For example, during a +dVcm/dt will result in large currents flowing unlikely case where one optocoup-
transient in Figure 24, the current through the power devices between ler with the fastest tPLH and another
flowing through CLEDN is supplied the high and low voltage motor rails. with the slowest tPHL are in the
by the parallel combination of the same inverter leg. The maximum
LED and series resistor. As long as To minimize dead time the designer dead time in this case becomes the
the voltage developed across the must consider the propagation sum of the spread in the tPLH and
resistor is less than VF(OFF) the LED delay characteristics of the opto- tPHL propagation delays as shown in
will remain off and no common coupler as well as the characteris- Figure 30. The maximum dead time
mode failure will occur. Even if the tics of the IPM IGBT gate drive is also equivalent to the difference
LED momentarily turns on, the 100 circuit. Considering only the delay between the maximum and mini-
pF capacitor from pins 6-5 will characteristics of the optocoupler mum propagation delay difference
keep the output from dipping below (the characteristics of the IPM specifications. The maximum dead
the threshold. The recommended IGBT gate drive circuit can be time (due to the optocouplers) for
LED drive circuit (Figure 19) pro- analyzed in the same way) it is the HCPL-4506, HCPL-0466 and
vides about 10 V of margin between important to know the minimum HCNW4506 is 600 ns (= 450 ns -
the lowest optocoupler output and maximum turn-on (tPHL) and (-150 ns)) over an operating
voltage and a 3 V IPM threshold turn-off (tPLH) propagation delay temperature range of -40°C to
100°C.

1-62