Hazards
Pipeline hazards are situations that prevent the next instruction in the
instruction stream from executing during its designated clock cycles.
Any condition that causes a stall in the pipeline operations can be
called a hazard.
i. Data Hazards:
A data hazard is any condition in which either the source or the
destination operands of an instruction are not available at the time
expected in the pipeline.
As a result of which some operation has to be delayed and the
pipeline stalls. Whenever there are two instructions one of which
depends on the data obtained from the other.
Eg. A=3+A
B=A*4
For the above sequence, the second instruction needs the value of
‘A’ computed in the first instruction.
Thus the second instruction is said to depend on the first.
If the execution is done in a pipelined processor, it is highly likely that
the interleaving of these two instructions can lead to incorrect results
due to data dependency between the instructions. Thus the pipeline
needs to be stalled as and when necessary to avoid errors.
ii. Structural Hazards:
This situation arises mainly when two instructions require a given
hardware resource at the same time and hence for one of the
instructions the pipeline needs to be stalled.
The most common case is when memory is accessed at the same
time by two instructions.
One instruction may need to access the memory as part of the
Execute or Write back phase while other instruction is being fetched.
In this case if both the instructions and data reside in the same
memory.
Both the instructions can’t proceed together and one of them needs
to be stalled till the other is done with the memory access part. Thus
in general sufficient hardware resources are needed for avoiding
structural hazards.
iii. Control hazards:
The instruction fetch unit of the CPU is responsible for providing a
stream of instructions to the execution unit. The instructions fetched
by the fetch unit are in consecutive memory locations and they are
executed.
However the problem arises when one of the instructions is a
branching instruction to some other memory location. Thus all the
instruction fetched in the pipeline from consecutive memory locations
are invalid now and need to removed(also called flushing of the
pipeline).
This induces a stall till new instructions are again fetched from the
memory address specified in the branch instruction.
Thus the time lost as a result of this is called a branch penalty. Often
dedicated hardware is incorporated in the fetch unit to identify branch
instructions and compute branch addresses as soon as possible and
reducing the resulting delay as a result.
