8 March 2024

Data Link Layer

Design Specifications

Design Specifications

Data Link Layer

Revision 1.0

8 March 2024

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 Data Link Layer
Design Specifications

TABLE OF CONTENTS
TABLE OF CONTENTS 2
LIST OF FIGURES 3
LIST OF TABLES 4
REVISION HISTORY 5
1. Data Link Layer Architecture 6
2. Link Management Control 7
3. Data Link Layer Transmitter 8
3.1. Interface 9
3.1.1. Pins Description 9
3.1.2. Parameters Description 10
3.2. Function Description 10
3.2.1. TLP Gen 10
3.2.2. Retry Buffer 10
3.2.3. DLLP Gen 12
3.2.4. Tx Control 13
3.2.5. DLLP Manager 14
3.2.6. Transmit Mux 15
3.3. Timing Diagram 15
4. Data Link Layer Receiver 16
4.1. Interface 16
4.1.1. Pins Description 16
4.1.2. Parameters Description 18
4.2. Function Description 19
4.2.1. Order_Control 19
4.2.2. Queues 19
4.2.3. Check_seq_num 19
4.2.4. Check_LCRC 19
4.2.5. Check_ECRC 20
4.2.6. De_frame_TLP 20
4.2.7. Next_tlp_counter 20
4.2.8. Check DLLP_CRC 20
4.3. Timing Diagram 21

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 Data Link Layer
Design Specifications

LIST OF FIGURES
Figure 1. Data Link Layer architecture ............................................................................................................... 6
Figure 2. Link Management Control finite state machine ................................................................................... 7
Figure 3. Architecture of dll_tx top ..................................................................................................................... 8
Figure 4. FSM of Retry buffer controller ........................................................................................................... 12
Figure 5 Architecture of Tx Controller .............................................................................................................. 13
Figure 6 FSM of Tx controller .......................................................................................................................... 14
Figure 7 Timing diagram of Tx controller ......................................................................................................... 15
Figure 8. Data Link Layer Receiver architecture .............................................................................................. 16
Figure 9. Order Control finite state machine .................................................................................................... 19
Figure 10. Receiver Timing diagram ................................................................................................................ 21

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 Data Link Layer
Design Specifications

LIST OF TABLES
Table 1. Pins description of dll_tx 9
Table 2 . Parameter description of dll_tx 10
Table 3. Size of Retry buffer 11
Table 4. Pin Description of dll_rx 16
Table 5. Parameters Description 18

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 Data Link Layer
Design Specifications

REVISION HISTORY
Revision Date Description of Changes
1.0 03-05-24 Document created
1.0 03-08-24 Document finished

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 Data Link Layer
Design Specifications

1. Data Link Layer Architecture

Figure 1. Data Link Layer architecture

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 Data Link Layer
Design Specifications

2. Link Management Control

Figure 2. Link Management Control finite state machine

This module control training process between two Links and also enable transmitting/receiving data from
Transaction Layer :
 DL_InActive : this is the initial state (dl_down = 0 and dl_up = 0). It waits until Physical Layer finishes the
training process (physical_link_up = 1) and begins to sponsor Flow Control of two devices .
 DL_InitFC1 : transmits Init FC1 to the other end of Link once per 34us and switches to DL_InitFC2 when
receives 3 InitFC1 in the right order (tx_fc1 & rx_fc1).
 DL_InitFC2 : transmit Init Flow_Control2 to confirm the buffer space of two devices. Data from
Transaction Layer can even be exchanged in this state (dl_up = 1).
 DL_Active : normal state in which data is usually exchanged

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 Data Link Layer
Design Specifications

3. Data Link Layer Transmitter

Figure 3. Architecture of dll_tx top

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 Data Link Layer
Design Specifications

3.1. Interface

3.1.1. Pins Description

Table 1. Pins description of dll_tx

Name Direction Type Bound Default Description

clk input

reset_n input

tlp_hdr input

tlp_data input

tlp_ecrc input

tlp_rdy input

tlp_vld input

tx_credit input

next_rcv_seq input

ack_nak_rx_flag input

ack_nak_rx_flag_vld input

tlp_rx_seq_num input

replay_num output logic [1:0] 0

tx_tlp_len output logic [MAC_TLP_LEN_WIDTH - 1:0] 0

tx_tlp_seq output logic [MAC_TLP_SEQ_WIDTH - 1:0] 0

tx_tlp_data output logic [FRM_DATA_WIDTH - 1:0] 0

tx_tlp_vld output logic 0

tx_tlp_end output logic 0

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 Data Link Layer
Design Specifications

tx_tlp_start output logic 0

tx_tlp_edb output logic 0

tx_dllp_data output logic [MAC_DLLP_DATA_WIDTH - 1:0] 0

tx_dllp_vld output logic 0

3.1.2. Parameters Description

Table 2 . Parameter description of dll_tx

Name Value Description

LANE_NUM 32 Lane number
MAC_TLP_LEN_WIDTH

MAC_TLP_SEQ_WIDTH

FRM_DATA_WIDTH

MAC_DLLP_DATA_WIDTH

3.2. Function Description

3.2.1. TLP Gen

 Next Transmit Seq: This module stores the Sequence number that will be added at the beginning of the next TLP
to transmit.
 LCRC Calculator: This module calculates a 32-bit CRC. The LCRC value is added to the tail of the TLP.

3.2.2. Retry Buffer

 This module stores the TLPs which are transmitted to the Physical Layer. When it is necessary, the Retry Buffer
retransmits the stored TLPs that are unacknowledged.

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Design Specifications

Table 3. Size of Retry buffer

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Design Specifications

Figure 4. FSM of Retry buffer controller

 ST_IDLE: IDLE state.

 ST_DELETE: When the transmitter receives an Ack/Nak, it purges TLPs from the Replay Buffer with Sequence
Numbers equal to or earlier than the Sequence Num‐ ber in the Ack/Nak.
 ST_RETRY: When the transmitter receives a Nak, it still purges the Replay Buffer of TLPs with Sequence Numbers
that are equal to or earlier than the Sequence Number that arrives in the Nak, but then it also replays (re‐sends)
TLPs of later Sequence Numbers (the remain‐ ing TLPs in the Replay Buffer). Block transmit TLPs during this state.
 ST_RETRAIN: When the REPLAY_NUM count rolls over from 11b to 00b (indicating 4 failed attempts to deliver the
same set of TLPs), the Data Link Layer automatically forces the Physical Layer to retrain the Link (LTSSM goes to
the Recovery state).

3.2.3. DLLP Gen

 CRC Calculator: This module generates a 16 bit CRC, which corresponds to a DLLP.
 DLLP Gen: Create DLLP Packets.

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 Data Link Layer
Design Specifications

3.2.4. Tx Control

Figure 5 Architecture of Tx Controller

 Replay num: received from Retry buffer, counts the number of retransmissions. It counts from 00b to 11b. When
the Replay num rolls over 11b to 00b, the Data Link Layer indicates to the Physical Layer to retrain Link.
 Ack/Nak notifications: Notifies to Retry Buffer the TLPs acknowledged or unacknowledged in the receiver.
 DLLP Manager: Manages transmission of DLLPs. Control Transmit Mux, DLLP is FC_DLLP or Ack/Nak_DLLP.

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Design Specifications

3.2.5. DLLP Manager

Figure 6. FSM of Tx controller

 ST_IDLE: IDLE state.

 ST_ACTIVE: TLPs is sent normally .
 ST_FC_INIT1: During the FC_INIT1 state, devices continuously send a sequence of 3 InitFC1 Flow Control
DLLPs advertising their receiver buffer sizes. The packets must be sent in this order: Posted, Non‐ posted,
and Completions.
 ST_FC_INIT2: In this state a device continuously sends InitFC2 DLLPs. These are sent in the same sequence
as the InitFC1s and contain the same credit information, but they also confirm that FC initialization has
succeeded at the sender.
 ST_ACK_NAK: The receiving device notifies the transmitting device that a good TLP has been received by
returning an Ack, and bad TLP by NAK.

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Design Specifications

 ST_UPDATE_FC: The receiver must regularly update its neighboring device with Flow Control credits that
become available when transactions are removed from the buffer.

3.2.6. Transmit Mux

 Select the outgoing port of the Data Link Layer Transmitter, where the TLPs that are transmitted by the Transaction
Layer of the TLPs that are retransmitted by Retry Buffer.

3.3. Timing Diagram

Figure 7. Timing diagram of Tx controller

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Design Specifications

4. Data Link Layer Receiver

Figure 8. Data Link Layer Receiver architecture

4.1. Interface

4.1.1. Pins Description

Table 4. Pin Description of dll_rx

Name Direction Type Bound Default Description

clk input

reset_n input

rx_tlp_start input [MAC_TLP_INTF_NUM - 1 : 0]

rx_tlp_vld input [MAC_TLP_INTF_NUM - 1 : 0]

rx_tlp_end input [MAC_TLP_INTF_NUM - 1 : 0]

rx_tlp_edb input [MAC_TLP_INTF_NUM - 1 : 0]

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Design Specifications

[MAC_TLP_INTF_NUM - 1 : 0] [LANE_NUM
* MAC_LANE_DATA_BYTE *
rx_tlp_data input MAC_BYTE_WIDTH - 1:0]
[MAC_TLP_INTF_NUM - 1 : 0]
rx_tlp_lcrc input [31:0]
[MAC_TLP_INTF_NUM - 1 : 0]
rx_tlp_len input [MAC_TLP_LEN_WIDTH - 1 : 0 ]
[MAC_TLP_INTF_NUM - 1 : 0]
rx_tlp_seq input [MAC_TLP_SEQ_WIDTH - 1:0]
[MAC_DLLP_DATA_BYTE *
rx_dllp_data input MAC_BYTE_WIDTH - 1:0]

rx_dllp_vld input

rx_dllp_malformed input

rx_dllp_unbound input
Header of
transaction layer
tlp_hdr output logic 0 packet
Data of transaction
tlp_data output logic 0 layer packet
Digest of transaction
layer packet
tlp_digest output logic 0 (Optional)

ack_nak_rx_flag output logic 0 0 : Nak, 1 : Ack

Can be used when
ack_nak_rx_flag_vld output logic 0 be asserted
Sequence Number
tlp_rx_seq_num output logic 0 of Rx TLP

ack_nak_tx_flag output logic 0 0 : Nak, 1 : Ack

Can be used when
ack_nak_tx_flag_vld output logic 0 be asserted
Sequence Number
tlp_tx_seq_num output logic 0 of Tx TLP
Enter Power
ent_pm_state output logic 0 Management state

p_hdr_rx_crd output logic 0

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Design Specifications

p_data_rx_crd output logic 0

np_hdr_rx_crd output logic 0

RxCredit of each
np_data_rx_crd output logic 0 type

cpl_hdr_rx_crd output logic 0

cpl_data_rx_crd output logic 0

4.1.2. Parameters Description

Table 5. Parameters Description

Name Value Description

MAC_TLP_INTF_NUM 4 Number of ports send data parallelly from PHY-Layer
MAC_TLP_LEN_WIDTH 11 Width of length field
MAC_TLP_SEQ_WIDTH 12 Width of sequence number field
MAC_DLLP_DATA_BYTE 6 Number of byte in DLLP data payload
MAC_BYTE_WIDTH 8 Number of bit in each data byte
LANE_NUM 32 Lane number

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4.2. Function Description

4.2.1. Order_Control

Figure 9. Order Control finite state machine

 IDLE : this is the initial state. It waits until the Data Link Layer finishes the training process (dl_up = 1) and one of
the ports contains data, then switches to PROCESS state.
 PROCESS : received data will be processed along these steps :
o Calculate the order of processing data in queues.
o Pop received data with calculated order.
o Check LCRC and sequence_number of each packet.
o Return Ack/Nak flag : if packet passes all the checks, return ACK flag and transmit packet to Transaction
Layer. Otherwise, it returns the NAK flag (!good_tlp) and switches to SUSPEND state.
o De-frame : extract packet into main information’s Transaction Layer : Header, Data, Digest.
 SUSPEND : If received data is not a valid packet, all data in queues are removed and wait for next rx_tlp_start to
switch to PROCESS state again.

4.2.2. Queues

Synchronous buffer which saves content of packets before it has been transferred to the next block to process.

4.2.3. Check_seq_num

This module counts the sequence number and compares which is received.

4.2.4. Check_LCRC

This module calculates LCRC-32bit based on the content of packets : Sequence number, Header, Data. And compare
with received LCRC from the other end of Link. And each packet must be processed in one cycle.

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4.2.5. Check_ECRC

ECRC is optional and activated in software.

4.2.6. De_frame_TLP

If all the checker blocks indicate that TLP is valid, this block will de-frame packets into frames : Header, Data, Digest.

4.2.7. Next_tlp_counter

When a good TLP is transmitted to the Transaction Layer, this block will increment the counter and transmit to
DLL_Tx to gen Ack/Nak flag.

4.2.8. Check DLLP_CRC

This module calculates CRC-16 bit based on DLLP data received and compares with CRC received, if passed it will
send data corresponding with each type of DLL packet.

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Design Specifications

4.3. Timing Diagram

Figure 10. Receiver Timing diagram

 In PROCESS state :
 Each packet must be processed in one cycle and follow the calculated order of ports.
 If any packet is an error, return the NAK flag and remove all relevant remaining data from buffers. It also
switches to SUSPEND state.
 If the last state is SUSPEND, now it checks for the first received packet, and the same process is maintained
like the above step.
 In SUSPEND state : now it waits for next rx_tlp_start to return to PROCESS state.

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