Indian Journal of Geo Marine Sciences

Vol.46 (09), September 2017, pp. 1920-1930

Novel Symmetric and Asymmetric Multilevel Inverter Topologies

With Minimum Number of Switches for High Voltage of Electric Ship
Propulsion System
S.Menaka1* & S.Muralidharan2
1
Department of Electrical and Electronics Engineering, Agni College of Technology, Chennai-600130, Tamilnadu, India
2
Department of Electrical and Electronics Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamilnadu, India
*
[Email:menaka.seeni@gmail.com]

Received 04 December 2015 ; revised 29 January 2016

Multilevel inverters are the excellent solution to attain speed range from minimum to maximum with high torque
at the propeller shaft in electric ship propulsion system. To produce high voltage with less harmonic content, multilevel
inverter requires more number of switching devices. In this paper, a new topology for symmetric, asymmetric multilevel
inverter is proposed. Hybrid topologies are extracted from proposed topologies for operating in higher voltage levels. It
generates dc voltage levels analogous to conventional topologies with less number of switches. It results in the reduction of
switching losses, complexity and converter cost. The effectiveness of the suggested topologies are verified by simulation
using MATLAB/SIMULINK. From the proposed topologies, asymmetric multilevel inverter is experimentally verified with
simulation results. By proper selection of switches in the proposed topologies, it is possible to supply power to the ship
propeller with maximum efficiency.

[Keywords: Propeller, Propulsion, Multilevel inverters, Cascaded H-bridge, Symmetric, Asymmetric, Hybrid]

Introduction
In recent years, multilevel inverters receive more phase 6-wire motor coupled to the propeller.
attention from both academy and industry.
Multilevel inverters are the excellent solution to
attain higher voltages with better harmonic
spectrum. Multilevel inverter is a power
electronic system that synthesizes a desired output
voltage from several levels of dc voltages as
inputs. The objective of multilevel inverter is to
produce a staircase output voltage using available
dc voltage sources. Quality of the output voltage
is improved by increasing the number of voltage
levels. Multilevel inverter not only achieves high
power ratings, but also enables the use of
renewable energy sources like photovoltaic, wind
and fuel cells1-4.
Fig. 1 Diagram of an electric ship propulsion system
Fig.1 shows the diagram of an electric ship
propulsion system. In this system, each diesel The two generator sets can operate either jointly
engine is directly coupled to a permanent magnet or one at a time, depending on the power demand
synchronous generator. A diode rectifier connects from the drive system. The working point of each
the output of the generator to a variable voltage dc diesel engine is determined in order to supply
bus. The dc bus feeds one of the input sides of the power to the propeller with maximum efficiency.
double inverter. The double inverter acts as a Depending upon the application requirements, it
multilevel inverter and it is able to drive the 3- is possible to connect the output of N number of
 INDIAN J. MAR. SCI., VOL. 46, NO. 09, SEPTEMBER 2017 1921

generator set by using multilevel inverter. half cycle and also produce the zero voltage
The multilevel concept is used to diminish the level. Based on the states of the switches,
harmonic distortion in the output waveform different levels of output voltage are generated.
without decreasing the inverter power output. To obtain +Vdc, switches SA,SB and S1 are turned
Multilevel inverter is classified as multilevel with on, whereas –Vdc can be obtained by turning on
common dc source such as diode clamped, flying switches SC,SD and S1 .To obtain +2Vdc, switches
capacitor and cascaded H-bridge(CHB)1-4. Among SA,SB and S2 are turned on, whereas –2Vdc can be
the familiar topologies, the most popular one is obtained by turning on switches SC,SD and S2.
cascaded multilevel inverter. It exhibits several Similarly, ac output voltage at each level can be
attractive features such as simple circuit layout, obtained in the same manner. Zero level is
modular in structure and avoid unbalance produced by turning on SA and SC or SB and SD.
capacitor voltage problem. The main switches (S1,S2,S3…..SN ) are used to
produce ac output voltage levels from Vdc to
Based upon the values of dc voltage sources, the NVdc.
CHB multilevel inverter is classified as symmetric
and asymmetric multilevel inverter. Symmetric An output phase voltage waveform of an Nlevel
multilevel inverter has the equal magnitude of proposed multilevel inverter is obtained by
voltage sources. But the magnitude of dc voltage Van(ωt)=Va1(ωt)+Va2(ωt)+……+Va(N-1)(ωt)+VaN(ωt). (1)
sources used in an asymmetric multilevel inverter The effective number of output phase voltage
are not equal. The symmetric CHB multilevel levels (Nlevel) in symmetric multilevel converter
inverter offers the advantage of high modularity. may be related to the number of separate dc
However this topology uses high number of sources (N) by:
switches resulting in high cost and control Nlevel = 2N+1 (2)
complexity. Asymmetric CHB Multilevel inverter Nswitch = N+4 (3)
rectifies the above problem. However,
The maximum output voltage (Vo.Max) of this
asymmetric topology looses modularity.
proposed symmetric multilevel inverter is:
Apart from the basic topologies, nowadays many
Vo.Max = NVdc (4)
modified topologies5-10 have been introduced for
both symmetric and asymmetric multilevel
inverter with less number of switches. In this From the equations (2) and (3), the relation
paper new topology is proposed for both between Nlevel and Nswitch can be derived as
symmetric and asymmetric multilevel inverters. follows for the proposed symmetric topology.
Principle of operation of proposed symmetric and Nlevel = 2Nswitch - 7 (5)
asymmetric multilevel inverters are discussed in
the next section. These proposed multilevel
inverters produce higher level output voltage with
fewer components when compared with
conventional symmetric, asymmetric CHB11 and
other topologies12. Finally simulation results are
illustrated to validate the capability of the
proposed topology in generation of desired output
voltage.

Materials and Methods

The main purpose of this paper is to reduce the
number of components in cascaded H-bridge
multilevel inverters. Single phase structure of a
proposed symmetric multilevel inverter is shown
in Fig.2. This inverter includes three parts:
separate dc sources (N), main switches (N) and
one H-bridge cell. The separate dc sources(SDCS)
used in the proposed topology have the same
magnitude equal to Vdc. H bridge is used to
change the polarity of the output voltage in every Fig. 2 Proposed symmetric multilevel inverter
1922 MENAKA & MURALIDHARAN: NOVEL SYMMETRIC AND ASYMMETRIC MULTILEVEL INVERTER TOPOLOGIES

Table 1: Status of the switches for different output voltage same as the cascade topology with less number of
levels in the proposed symmetric multilevel inverter
semiconductor switches.
Switch State
Output Van
S1 S2 S3 … SN-1 SN SASB SCSD
NVdc 0 0 0 … 0 1 1 0
(N-1)Vdc 0 0 0 … 1 0 1 0
…
…

…
3Vdc 0 0 1 … 0 0 1 0
2Vdc 0 1 0 … 0 0 1 0
Vdc 1 0 0 … 0 0 1 0
0 0 0 0 … 0 0 1 1
-Vdc 1 0 0 … 0 0 0 1
-2Vdc 0 1 0 … 0 0 0 1
-3Vdc 0 0 1 … 0 0 0 1
…
…

-(N-1)Vdc 0 0 0 … 1 0 0 1
-NVdc 0 0 0 … 0 1 0 1

Single phase structure of proposed asymmetric

multilevel inverter is shown in Fig.3.This inverter
includes three parts: separate dc sources (N), main
switches (2N) and one H-bridge cell. The separate
dc sources (SDCS) used in this proposed topology
Fig. 3 Proposed asymmetric multilevel inverter
are not of equal magnitudes. The H-bridge part is
as same as the symmetric topology. Unlike the Table 2: Status of the switches for different output voltage
symmetric topology, the asymmetric topology levels in the proposed asymmetric multilevel inverter
must be able to bypass or conduct the dc voltage
sources separately. This is necessary to generate Switch State
Output
all of the desired voltage levels. Van SA SC
S1 S2 S3 S4 … S2N-3 S2N-2 S2N-1 S2N
For the asymmetric multilevel inverter, the SB SD
separate dc sources are chosen such that N

V
K 1
K 0 1 0 1 … 0 1 0 1 1 0

Vk = 2(k-1) Vdc k = 1, 2, . . . N (6) …

…

…
…
…
…

…
…
…
Then VN 1 0 1 0 … 1 0 0 1 1 0
Nlevel = 2(N+1) - 1 (7) …
…

…
…
…
…

…
…
…

Nswitch = 2N+4 (8) V1 +V2 0 1 0 1 … 1 0 1 0 1 0

N
Vo.Max = (2 -1)Vdc (9) V2 1 0 0 1 … 1 0 1 0 1 0
V1 0 1 1 0 … 1 0 1 0 1 0
From the equations (7) and (8), the relation 0 0 0 0 0 … 0 0 0 0 1 1
between Nlevel and Nswitch can be derived as - V1 0 1 1 0 … 1 0 1 0 0 1
follows for the proposed asymmetric topology. - V2 1 0 0 1 … 1 0 1 0 0 1
…
N level  2 ( N switch 2) / 2  1 (10) -(V1 +V2) 0 1 0 0 1 0 1 0 0 1
…
…

…
…
…
…

…
…
…

-VN 1 0 1 0 … 1 0 0 1 0 1
Table1 and 2 shows the switching states of
…
…

…
…
…
…

…
…
…

proposed symmetric and asymmetric multilevel

N
inverter.
The main objective of this paper is to reduce the V
K 1
K 0 1 0 1 … 0 1 0 1 0 1

number of components in cascaded H-bridge

multilevel inverters. The proposed multilevel In the proposed multilevel inverters, switches
inverter can generate dc voltage levels that are the that are put on in the level creator arms are
switched in two half periods and those put on in
 INDIAN J. MAR. SCI., VOL. 46, NO. 09, SEPTEMBER 2017 1923

the H- bridge cell are almost switched with

fundamental frequency. Reduction in number of
switches and low frequency switching of the
proposed inverters improves the efficiency in
comparison with other topologies.
For example, for a 15 level inverter, the
proposed symmetric topology uses 11 IGBTs and
7 dc voltage sources whereas the cascaded
symmetric H-bridge use 28 IGBTs and 7 dc
voltage sources. The proposed asymmetric
multilevel inverter uses considerable lower
number of IGBTs and dc sources in comparison
with other topologies. For instance, for a 31 level (a)
inverter, the proposed asymmetric topology uses
12 IGBTs and 4 dc voltage sources whereas the
cascaded H-bridge use 16 IGBTs and 4 dc voltage
sources.
Table 3 and 4 summarize the comparison study
between the conventional cascaded topology in
symmetric and asymmetric with proposed
topology in symmetric and asymmetric states.

Table 3: Cascaded symmetric Vs. Proposed symmetric MLI

Inverter
Cascaded Proposed
Configuration
Symmetric Symmetric
Parameters H-Bridge inverter
(b)
DC sources N N
Fig. 4 Comparison study: Number of Levels vs. Number
Voltage Level 2N+1 2N+1 of Switches (a) Symmetric state (b) Asymmetric state

Vo Max NVdc NVdc In the proposed topologies, the switches of the

H-bridge part have to withstand a voltage equal to
Main switching sum of all the dc voltage sources. So, the H-
4N N+4
Devices
bridge switches should have the high standing
voltage which restricts the application of the
Table 4: Cascaded asymmetric Vs. Proposed asymmetric MLI proposed topologies for high voltage
requirements. In order to mitigate this problem,
Inverter Cascaded Proposed the proposed topologies can be used in hybrid
Configuration Asymmetric Asymmetric forms. Fig.5 shows the hybrid topology using the
H-Bridge inverter series connected proposed symmetric or
Parameters
asymmetric topology and an H-bridge.
DC sources N N

Voltage Level 2(N+1)-1 2(N+1)-1

Vo Max (2N-1) Vdc (2N-1) Vdc

Main switching
4N 2N+4
Devices

Fig.4 shows the comparison of the number of

switches between the topology suggested in this
paper and the conventional cascaded H-bridge
topology in symmetric and asymmetric states.

Fig. 5 Hybrid Topology

1924 MENAKA & MURALIDHARAN: NOVEL SYMMETRIC AND ASYMMETRIC MULTILEVEL INVERTER TOPOLOGIES

In proposed symmetric hybrid multilevel Va2max= 2N Vdc (17)

inverter, the input voltage of added H-bridge
inverter can be determined by the following
equation. From the equation (16) and (17), the maximum
VT = (N+1) Vdc (11) output voltage can be derived as follows for the
Where N is the number of separate dc sources asymmetric hybrid topology.
used in the proposed topology only. VLmax = (2N+1)Vdc (18)
Table 6 summarize the comparison study
The maximum output voltage of the proposed between the conventional cascade asymmetric
symmetric multilevel inverter used in the hybrid hybrid topology with proposed asymmetric hybrid
topology is: topology.
Va1max = NVdc (12)
Table 6: Cascaded asymmetric hybrid vs. Proposed
The maximum output voltage of the H-bridge asymmetric hybrid MLI
used in the symmetric hybrid topology is:
Va2max= (N+1)Vdc (13) Inverter Cascaded Proposed
Configuration Asymmetric Asymmetric
Parameters Hybrid Hybrid
From the equation (12) and (13), the maximum
output voltage can be derived as follows for the
DC sources N+1 N+1
symmetric hybrid topology.
VLmax = (2N+1)Vdc (14) Voltage Level 2(N+2) - 1 2(N+2) - 1
Table 5 summarize the comparison study
Vo Max (2N+1 - 1) Vdc (2N+1 - 1) Vdc
between the conventional cascade symmetric
hybrid topology with proposed symmetric hybrid Main switching
4(N+1) 2N+8
topology. Devices

Table 5: Cascaded symmetric hybrid vs. Proposed symmetric

hybrid MLI

Inverter Cascaded Proposed

Configuration Symmetric Symmetric
Parameters Hybrid Hybrid

DC sources N+1 N+1

Voltage Level 4N+3 4N+3

Vo Max (2N+1)Vdc (2N+1)Vdc

Main switching
4(N+1) N+8
Devices

In proposed asymmetric hybrid multilevel

inverter, the input voltage of added H-bridge
inverter can be determined by the following
equation.
VT = 2N Vdc (15)
Where N is the number of separate dc sources Fig.6 (a) Output voltage of the proposed symmetric
used in the proposed topology only. topology (for three Vdc sources) (b) Output voltage of the
added H-bridge(c) Output voltage of the hybrid topology

The maximum output voltage of the proposed Fig.6 shows the typical output of the proposed
asymmetric multilevel inverter used in the hybrid symmetric hybrid topology. Fig.6 (a) and (b)
topology is: shows the output voltage of the proposed
Va1max = (2N - 1) Vdc (16) symmetric topology and added H-bridge. This
figure indicates a possible modulation scheme to
The maximum output voltage of the H-bridge get the desired output voltage. Fig.6(c) shows the
used in the asymmetric hybrid topology is: output voltage of the hybrid topology.
 INDIAN J. MAR. SCI., VOL. 46, NO. 09, SEPTEMBER 2017 1925

In this hybrid MLI, the proposed symmetric voltage and level as that of proposed symmetric
topology is responsible for creating the voltage inverter with less number of separate dc voltage
levels. The added H-bridge decreases the voltage sources and switches. Reduction of switches leads
rating requirements of the switches for a specific to improved efficiency of the proposed topology.
output voltage rating. The same form can be done
for the asymmetric topology.

Result and Discussion

The performance of the proposed symmetric
and asymmetric inverter is verified via computer
simulation. The MATLAB-SIMULINK power
blockset software has been used for simulation.
The dc voltage sources used in the simulation
studies are separate dc sources. In practice, these
dc voltage sources may be available via
renewable energy sources such as photovoltaic,
wind and fuel cells.
For verifying the validity of the proposed
multilevel inverter in the generation of a desired
output voltage waveform, a prototype is simulated
based on the proposed symmetric topology which
is shown in Fig.2.
The input is given from generator through
rectifier as shown in Fig.1 or renewable energy
sources. The symmetrical multilevel inverter
shown in Fig.7 is adjusted to produce an output
voltage of 252 volts, 50Hz and 15 level staircase
waveform. This symmetric 15-level inverter
requires 7 separate dc voltage sources with the
rating of 36 volts which is now available in the
market. A resistive load of 100Ω is selected as a
parameter for testing the proposed symmetric
Fig. 7 The proposed symmetric topology -15 level MLI circuit
topology.
Switching status are given in Table 7 and the Table 7: Status of the switches – 15 level proposed
output voltage waveform for the proposed symmetric MLI
symmetric 15 level multilevel inverter is shown in Switch State
Fig.8. Output
Van SA SC
The asymmetrical multilevel inverter is shown in S1 S2 S3 S4 S5 S6 S7
SB SD
Fig.9 is adjusted to produce an output voltage of 7Vdc 0 0 0 0 0 0 1 1 0
252 volts, 50Hz and 15 level staircase waveform. 6Vdc 0 0 0 0 0 1 0 1 0
A resistive load of 100Ω is selected as a 5Vdc 0 0 0 0 1 0 0 1 0
parameter for testing the proposed asymmetric 4Vdc 0 0 0 1 0 0 0 1 0
topology. 3Vdc 0 0 1 0 0 0 0 1 0
This asymmetric 15-level inverter requires 3 2Vdc 0 1 0 0 0 0 0 1 0
Vdc 1 0 0 0 0 0 0 1 0
separate dc voltage sources with different voltage
0 0 0 0 0 0 0 0 1 1
rating of V1=36V, V2=72V and V3=144V. The
-Vdc 1 0 0 0 0 0 0 0 1
output voltage waveform for the proposed
-2Vdc 0 1 0 0 0 0 0 0 1
asymmetric 15 level multilevel inverter is shown -3Vdc 0 0 1 0 0 0 0 0 1
in Fig.10 and the status of the switches for the -4Vdc 0 0 0 1 0 0 0 0 1
corresponding output is given in Table 8. The -5Vdc 0 0 0 0 1 0 0 0 1
simulation results shows that the proposed -6Vdc 0 0 0 0 0 1 0 0 1
asymmetric multilevel inverter produce the output -7Vdc 0 0 0 0 0 0 1 0 1
1926 MENAKA & MURALIDHARAN: NOVEL SYMMETRIC AND ASYMMETRIC MULTILEVEL INVERTER TOPOLOGIES

Table 8: Status of the switches – 15 level proposed

asymmetric MLI

Switch State
Output Van
SA SC
S1 S2 S3 S4 S5 S6
SB SD
V1 + V2+ V3 0 1 0 1 0 1 1 0
V2 + V3 1 0 0 1 0 1 1 0
V1 + V3 0 1 1 0 0 1 1 0
V3 1 0 1 0 0 1 1 0
V1 + V2 0 1 0 1 1 0 1 0
V2 1 0 0 1 1 0 1 0
V1 0 1 1 0 1 0 1 0
0 0 0 0 0 0 0 1 1
- V1 0 1 1 0 1 0 0 1
- V2 1 0 0 1 1 0 0 1
Fig. 8 Proposed Symmetric Topology - 15 Level Output - (V1 + V2) 0 1 0 1 1 0 0 1
Voltage - V3 1 0 1 0 0 1 0 1
- (V1 + V3) 0 1 1 0 0 1 0 1
- (V2 + V3) 1 0 0 1 0 1 0 1
-(V1 +V2 + V3) 0 1 0 1 0 1 0 1

Fig.11 and Fig.12 shows the hybrid topology

based on the proposed symmetric and asymmetric
topology, respectively. These proposed inverters
are used for simulation studies of the hybrid
topologies. As shown in Fig.11, the proposed
symmetric topology uses 3 dc voltage sources,
each of which 36V and a 144 V dc voltage source
for the added H-bridge. Therefore the maximum
output voltage will be 252V for the proposed
symmetric hybrid topology. The simulation
results for the proposed symmetric hybrid
topology is shown in Fig.13. As the figure shows
the rated voltage (252V) is divided almost equally
between the two parts of the multilevel inverter.

As shown in Fig.12, the proposed asymmetric

topology uses 3 dc voltage sources of 18V, 36V
and 72V and an added H-bridge uses a dc voltage
Fig. 9 The proposed asymmetric topology-15 level MLI source of 144V. Therefore the maximum output
circuit voltage will be 270V for the proposed asymmetric
hybrid topology. The simulation results for the
proposed asymmetric hybrid topology is shown in
Fig.14. As the figure shows the rated voltage
(270V) is divided almost equally between the two
parts of the multilevel inverter leading to
reduction in the voltage rating of the switches
used in the H-bridge parts. Therefore, the
proposed hybrid topologies will be more suitable
for higher voltage application. Proposed hybrid
topologies are used to reduce and mitigate the
voltage stress problem persist in the switches of
the H-bridge part (Fig.7 and Fig.9). Proposed
hybrid topologies require less number of switches
Fig. 10 Proposed Asymmetric Topology - 15Level Output when compared to conventional cascaded H-
Voltage bridge hybrid topologies.
 INDIAN J. MAR. SCI., VOL. 46, NO. 09, SEPTEMBER 2017 1927

Fig. 11 The proposed symmetric hybrid topology -

15 level MLI

Experimental Results
In order to validate the proposed concept, the
asymmetric multilevel inverter in Fig.3 was
constructed and tested in the 15 level mode. It can
generate staircase waveform with maximum of 42
Fig. 12 The proposed asymmetric hybrid topology -
volts on the output.
31 level MLI
Fig.15 shows the generation of control signal for
proposed multilevel inverter circuit. The control
signal generation circuit consist of Field Fig.17 shows the experimental waveforms of the
Programmable Gate array (FPGA) controller, 15 level output voltage and current of the
opto-coupler and driver circuit. Each switch in the prototype system.The output voltage is a 50Hz
converter requires an isolated driver circuit. This staircase waveform with amplitude of 42 volts. As
isolation can be provided by using opto-coupler. can be seen, the results verify the ability of the
FPGA controller has been used to generate the proposed system for the generation of desired
Pulse Width Modulation (PWM) control signals output voltage.Also, we can note that in 15 level
according to the proposed switching strategy. The output, due to the reduction of switches two
PWM signal is used to trigger the power switches percent reduction in Total Harmonic
present in the proposed multilevel inverter circuit. Distortion(THD) is obtained in proposed
Fig.16 shows the experimental setup of the symmetric and asymmetric topologies compared
proposed asymmetric multilevel inverter.The to cascaded symmetric and asymmetric
converter consists of dc voltage sources of 6V, topologies.As the number of level increases,there
12V, 24V and one H-bridge. The experimental will be a appreciable reduction in THD. Harmonic
setup was realized by supplying a R load with profile can be improved further by applying
1.5A current. This prototype inverter was built various modulation and control techniques like
using MOSFET IRF840 as switching devices, IC carrier based Sinusoidal Pulse Width Modulation
TLP250 as MOSFET driver. The gating pulses (SPWM), Selective Harmonic Elimination (SHE-
are produced by FPGA controller (Xilinx ISE). PWM) and Space Vector Modulation(SVM).
1928 MENAKA & MURALIDHARAN: NOVEL SYMMETRIC AND ASYMMETRIC MULTILEVEL INVERTER TOPOLOGIES

Fig.13 Simulation results- The proposed symmetric hybrid Fig. 14 Simulation results- The proposed asymmetric hybrid
topology (a) output voltage of the proposed symmetric topology (a) output voltage of the proposed asymmetric
topology(Va1), (b) output voltage of the added H- topology(Va1), (b) output voltage of the added H-
bridge(Va2), (c) voltage across the load VL(15 level). bridge(Va2), (c) voltage across the load VL(31 level).
 INDIAN J. MAR. SCI., VOL. 46, NO. 09, SEPTEMBER 2017 1929

Conclusion
In this paper, a novel topology has been
proposed for both symmetric and asymmetric
multilevel inverter. The suggested topology needs
fewer switches to obtain the same levels of output
voltage when compared with conventional one. It
provides more flexibility for the designers with
low switching loss. Also, two hybrid topologies
have been proposed based on new symmetric and
asymmetric multilevel inverter which are more
suitable for high voltage applications.
The advantages of proposed inverter over
conventional inverter scheme can be summarized
as follows:
(1) Reduced switching loss.
Fig. 15 Generation of control signal for proposed MLI (2) Improved efficiency and reliability.
(3) Reduced cost, size and weight compared
to conventional systems.
Therefore, the suggested multilevel inverter
circuit is a good choice for electric ship
propulsion system because it allows to choose
optimal sizing of diesel motor and synchronous
generator thereby reducing the fuel consumption.
Simulation and experimental results are given to
verify the proposed topologies.

Acknowledgement
We are grateful to the management of
Agni college of Technology, Chennai and Mepco
Schlenk Engineering College, Sivakasi for
providing facilities to carry out the above research
Fig. 16 Experimental setup of proposed asymmetric work.
multilevel inverter
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