Scribd
Upload
180 views10 pages

VHDL Design: Adders and Subtractors

The document describes how to design adders and subtractors using VHDL. It includes the truth tables and code for half adders, full adders, half subtractors and full subtractors. It also provides examples of how to implement multi-bit addition and subtraction as well as a test bench example.

Uploaded by

Hazem Ha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
180 views10 pages

VHDL Design: Adders and Subtractors

The document describes how to design adders and subtractors using VHDL. It includes the truth tables and code for half adders, full adders, half subtractors and full subtractors. It also provides examples of how to implement multi-bit addition and subtraction as well as a test bench example.

Uploaded by

Hazem Ha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

Exercice 1 :

On veut réaliser un montage permettant d’effectuer l’addition ou la soustraction sur 1 bit avec
retenue entrante et sortante.

1. Etablir la table de vérité du demi-additionneur qui effectue l’opération Si = Ai Ꚛ Bi et


qui calcule la retenue sortante Ci.

library ieee;
use ieee.std_logic_1164.all;

Entity Demi_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci : out std_logic;
Si : out std_logic);
end Demi_additionneur;

architecture arch of Demi_additionneur is


Begin
Si <= Ai XOR Bi ;
Ci <= Ai AND Bi ;
End arch;

2. En déduire la table de vérité de l’additionneur complet qui effectue l’opération Si = Ai


Ꚛ Bi Ꚛ Ci-1 et qui calcule la retenue sortante.
A.

library ieee;
use ieee.std_logic_1164.all;

Entity Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci_1 : in std_logic;
Ci : out std_logic;
Si : out std_logic);
end Full_additionneur;

architecture arch of Full_additionneur is


Begin
Si <= Ai XOR Bi XOR Ci ;
Ci <= (Ai AND Bi) OR (Ci_1 AND (Ai XOR Bi)) ;
End arch;
B.

library ieee;
use ieee.std_logic_1164.all;

Entity Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci_1 : in std_logic;
Ci : out std_logic;
Si : out std_logic);
end Full_additionneur;

architecture arch of Full_additionneur is


Component Demi_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci : out std_logic;
Si : out std_logic);
end Component Demi_additionneur;
Signal sig1, sig2, sig3 : std_logic ;
Begin
ADD1 : Demi_additionneur port map (Ai, Bi, sig2, sig1) ;
ADD2 : Demi_additionneur port map (sig1, Ci_1, sig3, Si) ;
Ci <= sig2 OR sig3 ;
End arch;

3. Mêmes questions 1 et 2 pour le soustracteur.

library ieee;
use ieee.std_logic_1164.all;

Entity Demi_soustracteur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci : out std_logic;
Si : out std_logic);
end Demi_soustracteur;

architecture arch of Demi_soustracteur is


Begin
Si <= Ai XOR Bi ;
Ci <= (NOT(Ai)) AND Bi ;
End arch;

library ieee;
use ieee.std_logic_1164.all;

Entity Full_soustracteur is
Port ( A : in std_logic ;
B : in std_logic ;
bi : in std_logic;
b : out std_logic;
S : out std_logic);
end Full_soustracteur;

architecture arch of Full_soustracteur is


Begin
S <= A XOR B XOR bi ;
b <= ((NOT(A)) AND B) OR (bi AND (A XOR B)) ;
End arch;

4. En comparant l’étage additionneur et l’étage soustracteur 1 bit, proposer un schéma


unique qui, à l’aide d’une commande externe permet de réaliser soit l’addition, soit la
soustraction.
A. Soustraction à l’aide additionneur complet.
library ieee;
use ieee.std_logic_1164.all;

Entity Full_soustracteur is
Port ( A : in std_logic ;
B : in std_logic ;
C_1 : in std_logic;
C : out std_logic;
S : out std_logic);
end Full_soustracteur;

architecture arch of Full_soustracteur is


Component Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci_1 : in std_logic;
Ci : out std_logic;
Si : out std_logic);
end Component Full_additionneur;
Signal sig1 : std_logic ;
Begin
U1 : Full_additionneur port map (A, sig1, C_1, C, S);
sig1 <= NOT (B) ;
End arch;

B. Une commande externe permet de réaliser soit l’addition, soit la soustraction.

library ieee;
use ieee.std_logic_1164.all;

Entity Full_soustracteur is
Port ( A1 : in std_logic ;
B1 : in std_logic ;
M : in std_logic;
C1 : out std_logic;
S1 : out std_logic);
end Full_soustracteur;
architecture arch of Full_soustracteur is
Component Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci_1 : in std_logic;
Ci : out std_logic;
Si : out std_logic);
end Component Full_additionneur;
Signal sig1 : std_logic ;
Begin
U1 : Full_additionneur port map (A1, sig1, M, C1, S1);
sig1 <= B1 XOR M ;
End arch;

C. Soustraction 4 bits.

library ieee;
use ieee.std_logic_1164.all;

Entity Full_soustracteur is Entity Full_soustracteur is


Port ( A1,A2,A3,A4 : in std_logic ; Port (A: in std_logic_vector (3 downto 0) ;
B1,B2,B3,B4 : in std_logic ; B: in std_logic_vector (3 downto 0) ;
M : in std_logic; M : in std_logic;
C4 : out std_logic; C4 : out std_logic;
S1,S2,S3,S4 : out std_logic); S: out std_logic_vector (3 downto 0));
end Full_soustracteur; end Full_soustracteur;

architecture arch1 of Full_soustracteur is


Component Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci_1 : in std_logic;
Ci : out std_logic;
Si : out std_logic);
end Component Full_additionneur;
Signal sig1,sig2,sig3,sig4 : std_logic ;
Signal C1,C2,C3 : std_logic ;
Begin
U1 : Full_additionneur port map (A1, sig1, M , C1, S1);
U2 : Full_additionneur port map (A2, sig2, C1, C2, S2);
U3 : Full_additionneur port map (A3, sig3, C2, C3, S3);
U4 : Full_additionneur port map (A4, sig4, C3, C4, S4);
sig1 <= B1 XOR M ;
sig2 <= B2 XOR M ;
sig3 <= B3 XOR M ;
sig4 <= B4 XOR M ;
End arch1;
Ou Architecture 2

architecture arch2 of Full_soustracteur is


Component Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci_1 : in std_logic;
Ci : out std_logic;
Si : out std_logic);
end Component Full_additionneur;
Signal sig : std_logic_vector (3 downto 0) ;
Signal C : std_logic_vector (2 downto 0) ;
Begin
U1 : Full_additionneur port map (A(0), sig(0), M , C(0), S(0));
U2 : Full_additionneur port map (A(1), sig(1), C(0), C(1), S(1));
U3 : Full_additionneur port map (A(2), sig(2), C(1), C(2), S(2));
U4 : Full_additionneur port map (A(3), sig(3), C(2), C4 , S(3));
Sig(0) <= B(0) XOR M ;
Sig(1) <= B(1) XOR M ;
Sig(2) <= B(2) XOR M ;
Sig(3) <= B(3) XOR M ;
End arch2;

5. Ecrire le test bench de circuit additionneur en utilisant un design à base de langage de


description VHDL.

library ieee;
use ieee.std_logic_1164.all;

Entity Full_additionneur_TB is
end Full_additionneur_TB;

architecture arch of Full_additionneur_TB is


Component Full_additionneur is
Port ( Ai : in std_logic ;
Bi : in std_logic ;
Ci : out std_logic;
Si : out std_logic);
end Component Full_additionneur;
Signal Ai, Bi, Ci_1, Ci, Si : std_logic ;
Begin
ADD1 : Full_additionneur port map (Ai, Bi, Ci_1, Ci, Si) ;
Data : Process()
Begin
Ai <= ‘0’;
Bi <= ‘0’;
Ci_1 <= ‘0’;
Wait for 10 ns;
Ai <= ‘1’;
Bi <= ‘0’;
Ci_1 <= ‘0’;
Wait for 10 ns;
Ai <= ‘0’;
Bi <= ‘1’;
Ci_1 <= ‘0’;
Wait for 10 ns;
Ai <= ‘0’;
Bi <= ‘0’;
Ci_1 <= ‘1’;
Wait for 10 ns;
Ai <= ‘1’;
Bi <= ‘0’;
Ci_1 <= ‘0’;
Wait for 10 ns;
Ai <= ‘1’;
Bi <= ‘1’;
Ci_1 <= ‘0’;
Wait for 10 ns;
Ai <= ‘1’;
Bi <= ‘1’;
Ci_1 <= ‘1’;
Wait for 10 ns;
Wait ;
End process ;
End arch;

Exercice 2 :

Ecrire les circuits combinatoires réalisant les fonctions logiques précédentes utilisant un
design à base de langage de description VHDL.

• Mux à une entrée de commande (Mux 2 vers 1).


library ieee;
use ieee.std_logic_1164.all;

Entity MUX_2_1 is
Port ( E0 : in std_logic ;
E1 : in std_logic ;
S0 : in std_logic ;
Y : out std_logic);
end MUX_2_1;

architecture arch of MUX_2_1 is architecture arch of MUX_2_1 is


Begin Begin
With S0 select Y <= ((NOT(S0) ) AND E0) OR (S0 AND E1) ;
Y <= E0 when ’0’ , End arch;
E1 when others;
End arch;

• Mux à deux entrées de commande (Mux 4 vers 1).

library ieee;
use ieee.std_logic_1164.all;
Entity MUX_4_1 is
Port ( E0 : in std_logic ;
E1 : in std_logic ;
E2 : in std_logic ;
E3 : in std_logic ;
S0, S1 : in std_logic ;
Q : out std_logic);
end MUX_4_1;

architecture arch of MUX_4_1 is architecture arch of MUX_4_1 is


Component MUX_2_1 is Signal sig1,sig2,sig3,sig4 : std_logic ;
Port ( E0 : in std_logic ; Begin
E1 : in std_logic ; sig1<= E0 AND (NOT(S0 AND S1));
S0 : in std_logic; sig2<= E1 AND S0 AND (NOT(S1));
Y : out std_logic); sig3<= E2 AND (NOT(S0))AND S1 ;
end Component MUX_2_1; sig4<= E3 AND S0 AND S1 ;
Signal sig1, sig2 : std_logic ; Y <= sig1 OR sig2 OR sig3 OR sig4 ;
Begin End arch;
Mux1 : MUX_2_1 port map (E0, E1, S0, sig1) ;
Mux2 : MUX_2_1 port map (E2, E3, S0, sig2) ;
Mux3 : MUX_2_1 port map (sig1, sig2, S1, Q) ;
End arch;

• Encodeur à 8 entrées vers 3 sorties.

library ieee;
use ieee.std_logic_1164.all;

Entity Encodeur_8_1 is
Port ( E : in std_logic_vector (7 downto 0) ;
Q : out std_logic_vector (3 downto 0));
end Encodeur_8_1;

architecture arch of Encodeur_8_1 is


Signal sig1, sig2 : std_logic ;
Begin
With E select
Q <= x"0" when "00000000", -- x"00"
x"1" when "00000001", -- x"01"
x"2" when "00000010", -- x"02"
x"3" when "00000100", -- x"04"
x"4" when "00001000", -- x"05"
x"5" when "00010000", -- x"10"
x"6" when "00100000", -- x"20"
x"7" when "01000000", -- x"40"
x"8" when "10000000", -- x"80"
x"0" when others ;
End arch;

You might also like