8085 features

8085 developed by Intel has the following features:

• It is 8 bit size processor developed as single chip using N-MOS.
• It has multiplexed address and data bus on 8 lines AD0 to AD7.
• The maximum clock frequency used in 8085 is 3 MHz.
• It has 40 pins and runs at 5V power supply.
• There are 5 hardware interrupts viz. TRAP, INTR, RST5.5, RST6.5, RST7.5
• It has about 74 programming instructions with 4 addressing modes.
• It does not house memory, but it has 16 address lines which can access 64K
bytes (2^16) of externally connected memory.
• It has 8 bit lines which can address 256 (~2^8) ports connected externally.
• It has two serial lines viz. SID and SOD. These can be connected with serial
peripherals.
• It consists of ACC, one flag register, 6 general purpose registers and two special
registers(SP-Stack Pointer, PC-Program Counter).
 8051 Micro-controller
8051 is designed by Intel in 1981 and it is an 8-bit microcontroller.

Its on Harvard Architecture and was developed principally for bringing into play Embedded

Systems.

At first, it was created using NMOS technology but as NMOS technology needs more power to

function Intel re-intended Microcontroller 8051 employing CMOS technology

The new edition came into existence with a letter ‘C’ in the title name - 80C51.

These most modern Microcontrollers need a fewer amount of power to function in comparison to

their forerunners.

An on-chip crystal oscillator is integrated in the microcontroller with crystal frequency of 12 MHz.
 Features of 8051 Microcontroller
The 8051 microcontroller comes bundled with the following features −
• 4KB bytes on-chip program memory (ROM)
• 128 bytes on-chip data memory (RAM)
• Four register banks
• 8-bit bidirectional data bus
• 16-bit unidirectional address bus
• 32 general purpose registers each of 8-bit
• Two 16 bit Timers
• Three internal and two external Interrupts
• Four 8-bit ports (short model has two 8-bit ports)
• 8051 may also have a number of special features such as UARTs, ADC, Op-
amp, etc
The system bus connects all the support devices to the CPU.
The system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals.
All other devices like program memory, ports, data memory, serial interface, interrupt
control, timers, and the CPU are all interfaced together through the system bus.
•Pins 1 to 8 − These pins are known as Port 1. This port
doesn’t serve any other functions. It is internally pulled
up, bi-directional I/O port

•Pin 9 − It is a RESET pin, which is used to reset the

MC to its initial values.

•Pins 10 to 17 − These pins are known as Port 3. This

port serves some functions like interrupts, timer input,
control signals, serial communication signals RxD and
TxD, etc.

•Pins 18 & 19 − These pins are used for interfacing an

external crystal to get the system clock.

•Pin 20 − This pin provides the power supply to the

circuit.
•Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus
signals are also multiplexed using this port.

•Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from
the external program memory.

•Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the
external memory interfacing.

•Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to de-multiplex the
address-data signal of port.

•Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and data
bus signals are multiplexed using this port.

•Pin 40 − This pin is used to provide power supply to the circuit.

Internal RAM

IRAM has an 8-bit address space thru addresses 00 through 0xFF.

IRAM from 0x00 to 0x7F can be accessed directly, using an 8-bit absolute address as part of instruction

Alternatively, IRAM can be accessed indirectly: the address is loaded into R0 or R1, and the memory is

accessed using the @R0 or @R1 syntax.

The original 8051 has only 128 bytes of IRAM.

The 8052 added IRAM from 0x80 to 0xFF, which can only be accessed indirectly; direct access to this

address range goes to the special function registers (SFR).

Most 8051 clones also have a full 256 bytes of IRAM.

internal data memory

The internal data memory of 8051 is divided into two groups.

These are a set of eight registers and a scratch pad memory.
These eight registers are R0 toR7.
The address range 00H to 07H is used to access the registers, and the rest are scratch pad memory.
8051 Provides four register bank, but only one register bank can be used at any point in time.
To select the register bank, two bits of PSW (Program Status Word) are used.

Address Range Register Bank

00H to 07H Register Bank 0

08H to 0FH Register Bank 1

10H to 17H Register Bank 2

18H to 1FH Register Bank 3

The above addressing can be used to select register banks.

The concept of four register banks is very useful.
For servicing the interrupts, this feature is very good.
The interrupt program can use one bank, and the interrupt Service Subroutine (ISS) can
access another bank for better performance.
As there are four banks, so for nested interrupts these can be used
• Special function registers
(SFR) are located in the
same address space as
IRAM, at addresses 0x80 to
0xFF, and are accessed
directly using the same
instructions as for the lower
half of IRAM.

• They cannot be accessed

indirectly via @R0 or @R1;

• Sixteen of the SFRs are

also bit-addressable.
Program memory

• Program memory is up to 64 KB of read-only memory, starting at address 0 in a separate address

space.

• It may be on- or off-chip, depending on the particular model of chip being used.

• Program memory is read-only, though some variants of the 8051 use on-chip flash memory and

provide a method of re-programming the memory in-system or in-application.

• In addition to code, it is possible to store read-only data such as lookup tables in program memory.

• The address is computed as the sum of the 8-bit accumulator and a 16-bit register (PC or DPTR).

• Special jump and call instructions (AJMP and ACALL) slightly reduce the size of code that

accesses local (within the same 2 KB) program memory.

External data memory
• External data memory (XRAM) is a third address space, also starting at address 0, and
allowing 16 bits of address space.

• It can also be on- or off-chip; what makes it "external" is that it must be accessed using the
MOVX instruction.

• Many variants of the 8051 include the standard 256 bytes of IRAM plus a few kilobytes of
XRAM on the chip.

• The first 256 bytes of XRAM may be accessed using the MOVX A,@R0, MOVX A,@R1,
MOVX @R0,A, and MOVX @R1,A instructions.

• The full 64KB may be accessed using MOVX A,@DPTR and MOVX @DPTR,A.
Registers
• The only register on an 8051 that is not memory-mapped is the 16-bit program counter

(PC).

• This specifies the address of the next instruction to execute.

• Relative branch instructions supply an 8-bit signed offset which is added to the PC.

• Eight general-purpose registers R0–R7 may be accessed with instructions

• They are mapped to IRAM between 0x00 and 0x1F.

• Only eight bytes of that range are used at any given time, determined by the two bank

select bits in the PSW.

 This is an 8-bit register used by subroutine call and return instructions.
The stack grows upward; the SP is incremented before pushing, and decremented after
popping a value.
Data pointer, DP (0x82–83)
This is a 16-bit register that is used for accessing PMEM and XRAM.
Program status word, PSW (0xD0): This contains important status flags, by bit number:
1. Parity, P. Gives the parity (XOR of the bits) of the accumulator, A.
2. User defined, UD. May be read and written by software; not otherwise affected by
hardware.
3. Overflow flag, OV. Set when addition produces a signed overflow.
4. Register select 0, RS0.
5. Register select 1, RS1.
6. Flag 0, F0. May be read and written by software; not otherwise affected by
hardware.
 This register is used by most instructions.

B register (0xF0)

This is used as an extension to the accumulator for multiply and divide instructions.
256 single bits are directly addressable.
These are the 16 IRAM locations from 0x20–0x2F, and the 16 special function registers
0x80, 0x88, 0x90, ..., 0xF8.
Any bit of these bytes may be directly accessed by a variety of logical operations and
conditional branches.
Note that the PSW does not contain the common negative (N), or zero (Z) flags.
For the former, the most significant bit of the accumulator can be addressed directly, as it is
a bit-addressable SFR.
Interrupts is a sub-routine call raised by the microcontroller when some other program with

high priority is request for acquiring the system buses & the interrupts occur in current running

program.

Interrupts provide a method to postpone or delay the current process, performs a sub-routine

task and then restart the standard program again.

Types of interrupt in 8051 Microcontroller:

Let's see the five sources of interrupts in 8051 Microcontroller:

•Timer 0 overflow interrupt - TF0

•Timer 1 overflow interrupt - TF1

•External hardware interrupt - INT0

I/O Ports and their Functions

8051 microcontrollers have 4 I/O ports namely P0, P1, P2, and P3, each of 8-bit, which can
be configured as input or output.
Hence, total 32 input/output pins allow the microcontroller to be connected with the peripheral
devices.

• Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the
logic state.
• Upon RESET, all the ports are configured as inputs, ready to be used as input ports.
Port 0 (Pin No 32 – Pin No 39)

It has 8 pins (32 to 39).

It can be used for input or output.
Unlike P1, P2, and P3 ports, we normally connect P0 to 10K-ohm pull-up resistors to
use it as an input or output port being an open drain.

The P0 (zero) port is characterised by two functions :

• When the external memory is used then the lower address byte (addresses A0-A7) is
applied on it, else all bits of this port are configured as input/output.

• When P0 port is configured as an output then other ports consisting of pins with built-
in pull-up resistor connected by its end to 5V power supply, the pins of this port have
this resistor left out.
Input Configuration

If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the
input has unlimited input resistance and in-determined potential.

Output Configuration

When the pin is configured as an output, then it acts as an “open drain”. By applying
logic 0 to a port bit, the appropriate pin will be connected to ground (0V), and
applying logic 1, the external output will keep on “floating”.

In order to apply logic 1 (5V) on this output pin, it is necessary to build an external
pullup resistor.
Port 1 (Pin 1 through 8)

It is an 8-bit port (pin 1 through 8) and can be used either as input or output.
It doesn't require pull-up resistors because they are already connected internally.
Upon reset, Port 1 is configured as an input port.
The following code can be used to send alternating values of 55H and AAH to Port 1.

;Toggle all bits continuously

MOV A,#55
BACK: MOV P1,A
ACALL DELAY
CPL A ;complement(invert) reg. A
SJMP BACK
If Port 1 is configured to be used as an output port, then to use it as an input
port again, program it by writing 1 to all of its bits as in the following code.

;Toggle all bits of continuously

MOV A ,#0FFH ;A = FF hex

MOV P1,A ;Make P1 an input port
MOV A,P1 ;get data from P1
MOV R7,A ;save it in Reg R7
ACALL DELAY ;wait

MOV A,P1 ;get another data from P1

MOV R6,A ;save it in R6
Port 2 (Pins 21 through 28)

Port 2 occupies a total of 8 pins (pins 21 through 28) and can be used for both input and

output operations.

Just as P1, P2 also doesn't require external Pull-up resistors because they are already

connected internally.

i.e. P0 is designated as (A0–A7), while P2 as (A8- a15) as shown in the pin diagram.

When the 8051 is connected to an external memory, it provides path for upper 8-bits of 16-

bits address, and it cannot be used as I/O.

Upon reset, Port 2 is configured as an input port.

The following code can be used to send alternating values of 55H and AAH to port 2.

;Toggle all bits of continuously

MOV A,#55
BACK: MOV P2,A
ACALL DELAY
CPL A ; complement(invert) reg. A
SJMP BACK
If Port 2 is configured to be used as an output port, then to use it as an input port
again, program it by writing 1 to all of its bits as in the following code.
;Get a byte from P2 and send it to P1
MOV A,#0FFH ;A = FF hex
MOV P2,A ;make P2 an input port
BACK:
MOV A,P2 ;get data from P2
MOV P1,A ;send it to Port 1
SJMP BACK ;keep doing that
Port 3 (Pins 10 through 17)
• It is of 8 bits and can be used as Input/Output.
This port provides some extremely important
signals. P3.0 and P3.1 are RxD (Receiver) and
TxD (Transmitter) used for Serial Communication.
• P3.2 and P3.3 pins are used for external
interrupts.
• P3.4 and P3.5 are used for timers T0 and T1.
• P3.6 and P3.7 are Write (WR) and Read (RD)
pins.
• These are active low pins, means they will be
active when 0 is given to them and these are used
to provide Read and Write operations to External
ROM in 8051 based systems.
Dual Role of Port 0 and Port 2
•Dual role of Port 0 − Port 0 is also designated as AD0–AD7, as it can be used for both data
and address handling.
•While connecting an 8051 to external memory, Port 0 can provide both address and data.
The 8051 microcontroller then multiplexes the input as address or data in order to save pins.
•Dual role of Port 2 − Besides working as I/O, Port P2 is also used to provide 16-bit address
bus for external memory along with Port 0.
• Port P2 is also designated as (A8– A15), while Port 0 provides the lower 8-bits via A0–A7.
•In other words, we can say that when an 8051 is connected to an external memory (ROM)
which can be maximum up to 64KB and this is possible by 16 bit address bus because we
know 216 = 64KB.
•Port2 is used for the upper 8-bit of the 16 bits address, and it cannot be used for I/O and this
is the way any Program code of external ROM is addressed.
Hardware Connection of Pins
•Vcc − Pin 40 provides supply to the Chip and it is +5 V.
•Gnd − Pin 20 provides ground for the Reference.
•XTAL1, XTAL2 (Pin no 18 & Pin no 19) − 8051 has on-chip
oscillator but requires external clock to run it. A quartz crystal is
connected between the XTAL1 & XTAL2 pin of the chip.
• This crystal also needs two capacitors of 30pF for generating
a signal of desired frequency.
•8051 IC is available in various speeds and it all depends on
this Quartz crystal, for example, a 20 MHz microcontroller
requires a crystal with a frequency no more than 20 MHz.
•RST (Pin No. 9) − It is an Input pin and active High. Upon applying a high pulse on this

pin, that is 1, the microcontroller will reset and terminate all activities. This process is known

as Power-On Reset. Activating a power-on reset will cause all values in the register to be

lost. It will set a program counter to all 0's. To ensure a valid input of Reset, the high pulse

must be high for a minimum of two machine cycles before it is allowed to go low, which

depends on the capacitor value and the rate at which it charges. (Machine Cycle is the

minimum amount of frequency a single instruction requires in execution).

•EA' or External Access (Pin No. 31) − It is an input pin. This pin is an active low pin. In

case of microcontroller (8051/52) having on-chip ROM, the EA (bar) pin is connected to Vcc.
•PSEN or Program store Enable (Pin No 29) − This is also an active low pin, i.e.,

it gets activated after applying a low pulse. It is an output pin and used along with

the EA pin in 8031 based (i.e. ROMLESS) Systems to allow storage of program

code in external ROM.

•ALE or (Address Latch Enable) − This is an Output Pin and is active high. It is

especially used to connect it to the external memory. It can be used while deciding

whether P0 pins will be used as Address bus or Data bus. When ALE = 1, then the

P0 pins work as Data bus and when ALE = 0, then the P0 pins act as Address bus.
I/O Ports and Bit Addressability

It is a most widely used feature of 8051 while writing code for 8051.

Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8-bits.

8051 provides the capability to access individual bits of the ports.

While accessing a port in a single-bit manner, we use the syntax "SETB X. Y" where X is

the port number (0 to 3), and Y is a bit number (0 to 7) for data bits D0-D7 where D0 is

the LSB and D7 is the MSB.

For example, "SETB P1.5" sets high bit 5 of port 1.

The following code shows how we can toggle the bit P1.2 continuously.

AGAIN: SETB P1.2

ACALL DELAY
CLR P1.2
ACALL DELAY
SJMP AGAIN
Single-Bit Instructions

Instructions Function

SETB bit Set the bit (bit = 1)

CLR bit clear the bit (bit = 0)

CPL bit complement the bit (bit = NOT bit)

JB bit, target jump to target if bit = 1 (jump if bit)

JNB bit, target jump to target if bit = 0 (jump if no bit)

JBC bit, target jump to target if bit = 1, clear bit (jump if bit, then clear)
Interrupts

These are the events that temporarily suspend the main program, pass the control to the
external sources and execute their task.

It then passes the control to the main program where it had left off.

8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI of which INT0 & INT1 are
external interrupts while others are internal interrupts

Each interrupt can be enabled or disabled by setting bits of the IE register and the whole
interrupt system can be disabled by clearing the EA bit of the same register.
IE (Interrupt Enable) Register
This register is responsible for enabling and disabling the interrupt.
EA bit is set to one for enabling interrupts and set to 0 for disabling the interrupts.
IE register bit sequence and their meanings are shown in the following figure.

It disables all interrupts. When EA = 0 no interrupt will be

EA IE.7
acknowledged and EA = 1 enables the interrupt individually.

- IE.6 Reserved for future use.

- IE.5 Reserved for future use.

ES IE.4 Enables/disables serial port interrupt.

ET1 IE.3 Enables/disables timer1 overflow interrupt.

EX1 IE.2 Enables/disables external interrupt1.

ET0 IE.1 Enables/disables timer0 overflow interrupt.

EX0 IE.0 Enables/disables external interrupt0.

The priority level of the 8051 external interrupt

Source Priority Level

- External Interrupt 0 - Highest

- Timer 0 Overflow
- External Interrupt 1
- Timer 1 Overflow
- Serial Port - Lowest

- When two or more interrupt requests come at the same time and all the interrupts at the
same priority level the 8051 will select an interrupt for servicing based on above.
IP (Interrupt Priority) Register

We can change the priority levels of the interrupts by changing the corresponding bit in
the Interrupt Priority (IP) register as shown in the following figure.
• A low priority interrupt can only be interrupted by the high priority interrupt, but not by
another low priority interrupt.

• If two interrupts of different priority levels are received simultaneously, the request of
higher priority level is served.

• If the requests of the same priority levels are received simultaneously, then the
internal polling sequence determines which request is to be serviced.
 - IP.7 & Reserved for future use.
IP. 6

PT2 IP.5 Increases the priority of timer 2 (for 8052 only)

PS IP.4 It defines the serial port interrupt priority level.

PT1 IP.3 It defines the timer interrupt of 1 priority.

PX1 IP.2 It defines the external interrupt priority level.

PT0 IP.1 It defines the timer0 interrupt priority level.

PX0 IP.0 It defines the external interrupt of 0 priority level.

 Interrupt vector Table

ROM location of Flag

Interrupt Pin
its ISR clearing

Reset 0000H 9 Auto

External hardware interrupt

0003H P3.2(12) Auto
0(INT0)

Timer 0 interrupt(TF0) 000BH Auto

External hardware interrupt

0013H P3.3(13) Auto
1(INT1)

Timer 1 interrupt(TF1) 001BH Auto

Serial communication Programmer

0023H
interrupt(RI and TI) clears it

The Reset interrupt’s ISR, occupies only 3 bytes. All other ISRs occupy 8 bytes of space.