1.

The 2’s complement signed data contents of AL equal ‘-1’ and the contents of CL are
‘-2’. What result is produced in AX by executing the following instructions: [4]
i) MUL CL
AX=______________________H
ii) IMUL CL
AX=______________________H

2. Answer the following each question. [8]

i. __________________ is the address of counter 2, if the chip select line of 8254
is generated using
̅̅̅̅ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑪𝑺 𝑨𝟕 𝑨̅ 𝟔 𝑨𝟓 𝑨𝟒 𝑨
̅ 𝟑 𝑨𝟐

ii. 8254 is operating at 2Mhz clock. The count value N=_______________ must be
loaded in to counter to generate 1Khz square wave
iii. _________________ operation would be performed to read the count value of
the 8254 counter while counting is going on
iv. The arithmetic operation _____________________________will be done by the
following set of instructions?
SHL AX,1
MOV BX,AX
MOV CL,2
SHL AX,CL
ADD AX,BX

3. i. Find the address map for the following memory system. Use only the address lines
given in the figure [4]
ii. What would be the address map if two chips of 16K×8 EPROM and two chips of 32K×8
RAM are interfaced with 8086 CPU? Assume RAM address starts at 00000H and EPROM
starts at F8000H. [4]

4. An 8086-8255 based microcomputer is required to drive an LED connected to bit 2 of

Port B based on two switch inputs connected to bit 6 and 7 of port A. If both switches
are either high or low, LED will turn on ; otherwise, it will remain OFF. Assume base
address of 60H. A2 and A1 of 8086 is connected to A1 and A0 of 8255 respectively.
Fill in the blanks in the 8086 assembly language program given below which
accomplishes this. (all the ports are having 8 bits from bit 0 to bit 7) (6 Marks)

PORTA EQU 60H

PORTB EQU _____________
CONTR EQU ______________
MOV AL, ______________
OUT CNTRL, AL;
MAIN : IN AL, PORTA;
AND AL, ______________ (Hint: Masking unwanted data.)
JPE LEADON; (JPE= Jump if parity even, p=1)
MOV AL, __________
 OUT PORTB, AL;
JMP MAIN;
LEDON : MOV AL, _____________
OUT PORTB, AL;
JMP MAIN;

5. Fill in the blanks in the ALP given below which generates a 1 KHz square wave from
Counter1 of 8254 Timer. Use binary count in counter. Assume the gate of counter1 is tied to
+5V through a 10K resistor. Clock frequency is 2 MHz.
(6 Marks)

CNT1 EQU 8001H

CNTR EQU 8003H
MOV AL, ___________
OUT CNTR, AL
MOV AL, ___________
OUT CNT1, AL
MOV AL,__________
OUT CNT1, AL ( It will requires some calculation hence 6 marks)

6. Frame the command words ICW1, ICW2, ICW3, ICW4 and OCW1 for initializing
8259 to niigataite INT 40H to Int 47H (Hint: IR0 = 40H) in 8086. The desired features are level
triggered interrupt, Not fully nested , non-buffered and Automatic end of interrupt. If any ICW
is not required indicate as N/A. OCW is required. (10 Marks)

ICW1: _____________
ICW2: __________
ICW3: ___________
ICW4: ____________
OCW1:_____________

7. (a) Write down the port addresses of the three counters and the control word register of
8254 Timer. The CS’ signal is derived on the basis of A7 – A4 = 1111 and A3 – A2 = 00.
(2 Marks)

Counter 0 : __________
Counter 1 :____________
Counter 2 : ___________
Control Word Register:_____________

(b) Write down the Control Word so that Counter 1 operates in Mode 0 in binary
sequence. Assume that Counter 1 is to be loaded with a 2-byte count. (2 Marks)

Control word : ______________

8. Find the addresses of Port A, Port B, Port C and the control/status register of the
8255 whose
address decoding circuitry is as shown in Fig below:- (4 Marks)

Port A _________________
Port B _______________
Port C ___________________
Control register ________________

9. (a) MOV AL, 34H

MOV CL, 67H
ADD AL, CL
DAA
What are the contents of AL and CF?
[2]
AL=________________
CF=____________

(b) Let the current physical address of the stack top memory location is 60000H and SS =
6000H. The contents of the stack from the top locations, before the execution of the instruction,
are 12 and 34 respectively. What is the value of SP after the execution of the following
instruction?

POP AX [2]

SP=_________________
 (c) What will be the value of N in Hexadecimal in the following ALP segment, if a delay of
42 ms is to be incorporated using an 8086 system that runs on 5 MHz frequency?

MOV CX, N
WAIT: DEC CX
NOP
JNZ WAIT
RET
[3]
N=_________________H

10. Design an 8088 based system interface with the following memory requirements.
SRAM: 32 KB starting from 00000H
ROM: 32 KB starting from 08000H
The available memory chips are SRAM: 4KB, ROM: 4 KB (8 units each)
Available decoder: 74138 (3 units)
Using minimum number of decoders design and draw the memory interface.
[8]

11. (i) Specify the value of the ICW1 needed to configure an 8259A as follows: ICW4
not required, single device interface, and edge-triggered inputs. Assume all
other unused bits are 0. Write the final answer in hexadecimal format only i.e.
XXh.
ICW1=_____________H
[4]
(ii) Specify the value of ICW4 such that the 8259A is configured for use in an 8086
system, with normal EOI, buffered-mode master, and special fully nested-
mode disabled. Write the final answer in hexadecimal format only i.e. XXh.
ICW4 =______________H [4]

(iii) What interrupt will have the lowest priority if OCW2 = 67h? If your answer is
‘IRX’ write the value ‘IRX’ only.
Interrupt= IR____________ [2]

12. Consider the following interfacing between 8086 and 8254. What should be the control/
mode words to setup the counters with following operation.

Counter 0: Binary counter operating in mode 0 with an initial value of 1234h.

Counter 1: BCD counter operating in mode 2 with an initial value of 0100h.
Counter 2: Binary counter operating in mode 4 with an initial value of 1FFFh.

Write your answer only in the following starting for counter 0.

XXh, YYh, ZZh (where XX, YY and ZZ are your answers). [10]
 Control/Mode word for counter 0 = ______________________H
Control/Mode word for counter 1 = ______________________H
Control/Mode word for counter 2 = ______________________H

13. Consider the following interfacing between 8086 and 8255. Note that there are multiple
PPIs are connected to the microprocessor.

Now assume that the PPI 14 is configured in the following way.

Port A is an output port; both Port B and Port C are input ports; all the three ports are
setup for mode 0 operation. The addresses of Port A in hexadecimal format is 38.
 Write an ALP that will input the data at ports B and C, find the difference (Port C) –
(Port B), and output this difference to port A. [10]

14. Using 8255 BSR generate a square waveform of frequency of 2 KHz on PC0. 8255 base address
is 00H.Write the software segment for programming 8255 to generate the waveform. You can
assume that there is a delay routine (delay250) available for generating a delay of 250 s. You
need not show the hardware interfacing circuit. [10]

15. For the following instructions determine the addressing mode and the Machine code.
Assume instructions are in 16 bit mode of operation. [6M]
(i) MOV EAX, [BX+DI+4020]
Addressing mode=________________
Machine code=________________________
(ii) MOV BX, [EBX+2*ECX]
Addressing mode=________________
Machine code=________________________

16. From the 8 byte 80386 descriptor given below (a) ________________________will be the
starting address of the segment in memory and (b) ___________________is the size of the
segment in bytes? (Descriptor is given in BIG ENDIAN FORMAT (i.e.) MSB onwards) [4]
A2 5F B7 00 00 00 FF FF

17. For an 80286 processor having the Access right byte 0B9H, give the description of the
nature of the segment. Write the privilege levels of the application that are allowed to
access this segment. [3]

18. For an 80386 descriptor that contains a base address of 00280000H, a limit of 00010H,
and G=1, the starting and ending locations addressed by this descriptor are
_____________and ________________________respectively. [2]