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MICROPROCESSOR PROGRAMMING
AND INTERFACING

Lecture 3

Introduction & Overview

ISA Continued…

What is Operand?
✔ An operand is a value that an instruction operates on.
✔ By giving an instruction type and an addressing mode, we have somehow specified some
operands for the instruction.

Various Operand Types

❑ Integers: 8-bit (characters), 16-bit (words), 32-bit (doubleword), 64-bit (quadword).

❑ Single or double precision floating point numbers: Generally 32 or 64-bit.
❑ Binary coded decimal or BCD: Packed or Unpacked.
❑ Strings: Variable length (not all ISA supports).

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ISA Continued…

Types of Instructions
✔ Data transfer instructions.
✔ Arithmetic and logical instructions.
✔ Control transfer instructions.
✔ Floating point instructions.

Instructions Encoding

⮚ We shall take an example: MIPS Instruction Set.

⮚ The instruction set is 32-bit long (Consider 0 to be LSB and 31 to be MSB)
⮚ 32 integer registers with most of them being general purpose.
⮚ Register R0 is always set to 0.
⮚ First 6 bits and bits 31-26 specify an opcode giving information about what instruction is
supposed to be executed.
⮚ MIPS register and addresses are 64-bit.
⮚ MIPS is byte-addressable and requires aligned access with the capability to switch between
Big or Little Endian.

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ISA Continued…

Instructions Encoding Continued…

⮚ I-type Instruction: Instructions with immediate operand.

⮚ R-type Instruction: Register-Register Arithmetic and logic instructions.
⮚ J-type Instruction: Jump to PC-relative address.

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ISA Continued…

Instructions Encoding Continued…

Similar examples can be given for I-type and J-type instructions.

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Flynn’s Classification of Computers

 Introduced by Micheal Flynn in 1972

 Classification based on notions of instructions and data streams.
 4 types of architecture
 Single instruction stream over single data (SISD): Conventional Sequential Machine
 Single instruction stream over multiple data (SIMD): Vector Computers
 Multiple instruction stream over single data (MISD): Systolic Arrays
 Multiple instruction stream over multiple data (MIMD): Parallel Computers

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Flynn’s Taxonomy: Parallel Computing

SISD SIMD

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Flynn’s Taxonomy: Parallel Computing

MISD MIMD

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CISC and RISC Processors

Brief Idea

⮚ RISC: Reduced Instruction Set Computer

⮚ It has simpler instructions and thus simple instruction decoding.
⮚ More general-purpose registers.
⮚ Instruction takes one clock cycle in order to get executed.
⮚ Instruction comes under the size of a single word.
⮚ Pipeline can be easily achieved.
⮚ Few data types and thus simpler addressing modes.

⮚ CISC: Complex Instruction Set Computer

⮚ Instructions are complex, and thus complex instruction decoding.
⮚ Instructions may take more than one clock cycle in order to get executed.
⮚ Instruction is larger than a one-word size.
⮚ Lesser general-purpose registers since the operations get performed only in the
memory.
⮚ More data types and thus complex addressing modes.

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CISC and RISC Processors

Goal: Multiply data in mem A with B Available memories

and put it back in A

CISC:
MUL A,B

RISC:
LDA R0,A
Available registers
LDA R1,B
MUL R0,R1
STR A,R0

Set of available operations

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CISC and RISC Processors

Execution Time
𝑆𝑒𝑐𝑜𝑛𝑑𝑠 𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝐶𝑦𝑐𝑙𝑒𝑠 𝑆𝑒𝑐𝑜𝑛𝑑𝑠
𝐶𝑃𝑈 𝑇𝑖𝑚𝑒 = = × ×
𝑃𝑟𝑜𝑔𝑟𝑎𝑚 𝑃𝑟𝑜𝑔𝑟𝑎𝑚 𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝐶𝑦𝑐𝑙𝑒

• RISC: Reduce the cycles per instructions (Instructions per program )

• CISC: Reduce the no. of instructions (No. of cycles per program )

How can we improve the execution time even more?

 Pipelining
 Branch Prediction
 Superscalar Execution
 Data flow analysis
 Speculative execution

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Basic Parallel Techniques

How to improve computational speed?

⮚ Usage of faster circuitry, multiple registers, cache memory etc.

⮚ Instruction pipelining.
⮚ New inputs are accepted at one end before previously accepted inputs appear as
outputs at the other end.
⮚ Improves speed dramatically
⮚ Susceptible to hazards like resource, data, and control.

Example: Parallel Execution

Serial Execution

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Basic Parallel Techniques Continued…

Instruction Pipelining Operations

1. Fetching the instruction from memory (IF)

2. Decoding the obtained instruction (ID)
3. Calculating the effective address (EA)
4. Fetching the operands from the given memory (OF)
5. Execution of the instruction (EX or IE)
6. Storing the result in a proper place (WB or OS)

Example:

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Amdahl’s Law
Improvement in system performance can be achieved by incorporating by parallel
processors, use of memory cache hierarchy, speedup in memory access and I/O
transfer rate, etc.
𝑇𝑖𝑚𝑒 𝑡𝑜 𝑒𝑥𝑒𝑐𝑢𝑡𝑒 𝑝𝑟𝑜𝑔𝑟𝑎𝑚 𝑜𝑛 𝑎 𝑠𝑖𝑛𝑔𝑙𝑒 𝑝𝑟𝑜𝑐𝑒𝑠𝑠𝑜𝑟
𝑆𝑝𝑒𝑒𝑑𝑢𝑝 =
𝑇𝑖𝑚𝑒 𝑡𝑜 𝑒𝑥𝑒𝑐𝑢𝑡𝑒 𝑜𝑛 𝑁 𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑝𝑟𝑜𝑐𝑒𝑠𝑠𝑜𝑟

𝑇 1 − 𝑓 + 𝑇𝑓 1
= =
𝑇𝑓 𝑓
𝑇 1−𝑓 + 𝑁 1−𝑓 +𝑁

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End of Lecture-3

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