Data converters

d/a converters
 d/a converters
 The input is an n-bit binary word ‘D’ and is combined with a reference voltage 𝑉𝑅 to
give an analog output signal.
 The output of the DAC can be either a voltage or current.
 For a voltage output DAC, the D/A converter is mathematically described as
 d/a converters

 There are various ways to implement the above equation.

1. Weighted resistor DAC
2. R-2R Ladder Circuit
3. Inverted R-2R Ladder Circuit
 Weighted resistor d/a converters
 One of the simplest circuit is given below uses summing amplifier with a binary
weighted resistor network.
 It has n-electronic switches 𝑑1 , 𝑑2 , 𝑑2 , … … … … … . 𝑑𝑛 controlled by the binary word
‘D’.
 If the binary input to a particular switch is 1, it connects the resistance to the
reference voltage −𝑉𝑅 .
 If the input bit is 0, the switch connects the resistor to the ground.
Weighted resistor d/a converters
Weighted resistor d/a converters
 The output current 𝐼0 is
 Weighted resistor d/a converters
 Comparing the above equation with the equation (1),

 it can be seen that if R f = R then K = 1 and VFS = VR ,

 The circuit uses a negative reference voltage.
 The analog output voltage is positive staircase as shown in below and the figure for a
3-bit weighted resistor DAC.
Weighted resistor d/a converters
 Weighted resistor d/a converters
 The accuracy and stability of a DAC depends upon the accuracy of the resistors and
the tracking of each other with temperature.
 One of the disadvantages of the binary weighted type DAC is the wide range of
resistor values required.
 For better resolution, the input binary word length has to be increased i.e, the number
of bit increases. The range of the resistance value increases.
 For 8-bit DAC, the resistors required are 20 𝑅, 21 𝑅, 22 𝑅, … … … … 27 𝑅.
 The largest resistor is 128 times of the smallest one for only 8-bit DAC.
 Weighted resistor d/a converters

 For the 12-bit DAC, the largest resistance is 5.12MΩ if the smallest resistor is 2.5KΩ .
 The fabrication of such a large resistance in IC is not practical.
 Also there will be a loading effect due to this large resistance values, the choice of
smallest resistor value as 2.5KΩ is reasonable.
 This can be avoided by using R-2R ladder circuit.
 R-2r d/A converters
 A DAC converter uses an op amp and R-2R ladder resistors. The R-2R network consists of
resistors with only two values R and 2R.
 If each input is supplied either 0 volts or reference voltage, the output voltage will be an
analog equivalent of the binary value of the three bits. D2 corresponds to the most
significant bit (MSB) while D0 corresponds to the least significant bit (LSB).
 The Analog output voltage of 3-bit R-2R ladder D/A Converter is calculated using
𝑫𝟏 (𝑴𝑺𝑩) 𝑫𝟐 𝑫𝟑 (𝑳𝑺𝑩)
𝑽𝒐𝒖𝒕 = 𝑽𝑹 ( + + )
𝟐 𝟒 𝟖

 For n-bit R-2R ladder converter output is

𝑫𝟏 (𝑴𝑺𝑩) 𝑫𝟐 𝑫𝒏 (𝑳𝑺𝑩)
 𝑽𝒐𝒖𝒕 = 𝑽𝑹 + +………….. +
𝟐 𝟐𝟐 𝟐𝒏
R-2r d/a converters
R 2r dac converters
R-2r dac converters
 R-2r dac converters
 For the input binary word 001 in 3 bit DAC output
Inverted R-2r dac converter
Inverted R-2r dac converter
 Inverted R-2r dac converter
 In weighted resistor type DAC and R-2R ladder type DAC, current flowing in the resistor
changes as the input data changes. More power dissipation causes heating, which in turn
creates non-linearity in DAC.
 This problem completely avoided in Inverted R-2R Ladder Type DAC.
 Here each input binary word connects the corresponding switch either to ground or to the
inverting input terminal of the op-amp which is also at virtual ground.
 Since both the terminals of switches 𝑑𝑖 are at ground potential, current flowing in the
resistances is constant and independent of switch position. i.e independent of input binary
word.
 Inverted R-2r dac converter
 when switch 𝑑𝑖 is at logical ‘0’, the current through 2R resistor flows to the ground.
 when the switch 𝑑𝑖 is at logical ‘1’, the current through the 2R resistor sinks to the virtual
ground.
 The circuit has important property that the currents divides equally at each of the nodes and
this is because of the equivalent resistance to the right or to the left of any node is exactly
2R.
 Inverted R-2r dac converter
 Consider the reference current of 2mA. Just right of the node A, the equivalent resistance
is 2R.
 Thus 2 mA of reference input current divides equally to value 1 mA at node A. Similarly
to the right of the node B, the equivalent resistance is 2R. Thus 1 mA of the current
further divides to value 0.5mA at node B.
 Similarly, current divides equally at node C to 0.25 mA.
 The equal division of current in successive nodes remains the same in the inverted R-2R
ladder irrespective of the input binary word.
 The current remains constant in each branch of the ladder.
 Inverted R-2r dac converter
 Since constant current implies constant voltage, the ladder node voltages remain constant at
𝑉𝑅 20 , 𝑉𝑅 21 , 𝑉𝑅 22 .
 The most important advantage of the current mode or inverted ladder is that since the ladder
node voltages remain constant even with changing input binary words.
 Since the switch gets connected either to ground for 𝑑𝑖 = 0 or to −𝑉𝑅 for 𝑑𝑖 =1 .
 The current flowing through the input inverting terminal to −𝑉𝑅 for 𝑑𝑖 =1 and from ground
to −𝑉𝑅 for 𝑑𝑖 = 0 .
 The currents in the resistive branches of the inverted ladder circuit remains constant and
current through the feedback resistor R is the summing current depending upon the input
word.
 dac Specifications
Some important terms in DAC
• Resolution
• Accuracy
• Stability
• Settling Time
• Conversion Time
 dac Specifications
• Resolution
 Definition: Resolution of a DAC may be defined as the number of different analog output
values that the DAC can provide.
 For a n-bit input word, the number of possible outputs =2𝑛 . Resolution = 𝟐𝒏
 For a 4-bit DAC, resolution = 24 =16 and 8-bit DAC, resolution = 28 = 256

 Definition: resolution may be defined as the change in the output voltage of ne DAC
caused by a change of 1 LSB of the digital input.
𝑽𝑭𝑺
 For a n-bit DAC: Resolution= 𝒏
𝟐 −𝟏

where 𝑉𝐹𝑆 is the full scale output voltage

 dac Specifications
• Resolution
 Let 8-bit DAC full scale output voltage 𝑽𝑭𝑺 =5.1.

The Resolution=𝟐𝟓.𝟏
𝟖 −𝟏 = 𝟐𝟎 𝒎𝑽/𝑳𝑺𝑩

This implies that a change in the digital input by 1 LSB causes the change of 20 mV analog
Output.
Let the decimal equivalent of input binary word be denoted as D.
The output voltage 𝑽𝟎 = 𝑹𝒆𝒔𝒐𝒍𝒖𝒕𝒊𝒐𝒏 × 𝑫
 dac Specifications
• Accuracy
 ldeally, the output voltage of a DAC should not differ from the expected output or at the
1
worst, the difference should not exceed ± of its LSB.
2
𝑉𝐹𝑆
The accuracy = ± 𝑛 .
2(2 −1)

• Stability
 Changes of temperature, variations in power supply, and long usage affects the performance
of a DAC. The device parameters like gain, linearity error, offset which are liable to change,
must therefore be specified over the range of variations of power supply and temperature.
 These parameters provide a measure of the stability of the DAC.
 dac Specifications
• Settling Time

 The settling time of a DAC is defined as the time required for the output to settle
1
to within ± LSB of the final value, for a given digital input.
2

• Conversion Time

 It may be defined as the time needed for the conversion of a digital input signal to its
equivalent analog signal.
 It is affected by the response time of the switches and amplifier output.
 Analog to Digital converters
ADC: It accepts an analog voltage Va and produces an
output binary word D.

where d1, is the most significant bit and dn, is the least
significant bit.

 An ADC usually has two additional control lines: the

START input to tell the ADC when to start the
conversion and the EOC (end of conversion) output to
announce when the conversion is complete.
 Analog to Digital converters
 Depending upon the type of application ADCs are
classified broadly into two groups according to their
conversion technique.

 Direct type ADCs and Integrating type ADCs.

 Direct type ADCs compare a given analog signal with

the internally generated equivalent signal. This group
includes

 Flash (Parallel comparator) type converter

 Counter type converter
 Tracking or servo converter
 Successive approximation type converter
 Analog to Digital converters
 Integrating type ADCs perform conversion in an indirect
manner by first changing the analog input signal to a
linear function of time or frequency and then to a digital
code.

 The two most widely used integrating type converters

are:
 Charge balancing ADC
 Dual slope ADC
 Parallel Comparator (Flash) A/D converters
 This is the simplest possible AD converter. It is at the same time, the fastest and most
expensive technique.

 The given circuit consists of a resistive divider network, 8 op-amp comparators and a 8-line
to 3-line encoder (3-bit priority encoder).

 Small amount of hysteresis is built into the comparator to resolve any problems that might
occur if both inputs were of equal voltage as shown in the truth table.

 At a each node of the resistive divider, a comparison voltage is available.

 Since all the resistor are of equal value, the voltage levels available at the nodes are equally
divided between e reference voltage VR and the ground.

 The purpose of the circuit is to compare the analog input voltage Va With each of the node
voltages.
 Parallel Comparator (Flash) A/D converters

 This is the simplest possible AD converter. It is at the same time, the fastest and most
expensive technique.
 The given circuit consists of a resistive divider network, 8 op-amp comparators and a 8-
line to 3-line encoder (3-bit priority encoder).
 Small amount of hysteresis is built into the comparator to resolve any problems that might
occur if both inputs were of equal voltage as shown in the truth table.
 At a each node of the resistive divider, a comparison voltage is available.
 Since all the resistor are of equal value, the voltage levels available at the nodes are
equally divided between e reference voltage VR and the ground.
 Parallel Comparator (Flash) A/D converters
 The purpose of the circuit is to compare the analog input voltage Va With each of the
node voltages.
 The circuit has the advantage of high speed as the conversion take place simultaneously
rather than sequentially.
 Typical conversion time is 100 ns or less.
 Conversion time is limited only by the speed of the comparator and of the priority
encoder.
 Parallel Comparator (Flash) A/D converters

 This type of ADC has the disadvantage that the number of comparators required almost
doubles for each added bit.
 A 2-bit ADC requires 3 comparators, 3-bit ADC needs 7, whereas 4-bit requires 15
comparators.
 In general, the number of comparators required are 2𝑛 − 1. where n is the desired number
of bits.
 Hence the number of comparators approximately doubles for each added bit.
 Also the larger the value of n, the more complex is the priority encoder.
Parallel Comparator (Flash) A/D converters
Parallel Comparator (Flash) A/D converters
 Counter Type A/D Converters
 The D to A converter can easily be turned around to provide the inverse function A to D
conversion.
 3-bit counting ADC is shown in Fig. (a).

 The counter is reset to zero count by the reset pulse. Upon the release of RESET, the clock
pulses are counted by the binary counter.

 These pulses go through the AND gate which is enabled by the voltage comparator high
output. The number of pulses counted increase with time.
 Counter Type A/D Converters
 The binary word representing this count is used as the input of a D/A converter whose
output is a staircase of the type shown in Fig. (b).
 The analog output Vd of DAC is compared to the analog input Va, by the comparator.
 If Va > Vd, the output of the comparator becomes high and the AND gate is enabled to
allow the transmission of the clock pulses to the counter.
 When Va< Vd, the output of the comparator becomes low and the AND gate is disabled.
 This stops the counting at the time 𝑉𝑎 ≤ 𝑉𝑑 and the digital output of the counter represents
the analog input voltage Va.
 For a new value of analog input Va, a second reset pulse is applied to clear the counter.
Upon the end of the reset, the counting begins again.
 Counter Type A/D Converters
 The counter frequency must be low enough to give sufficient time for the DAC to settle and
for the comparator to respond.
 Low speed is the most serious drawback of this method.
 The conversion time can be as long as (2"- 1) clock periods depending upon the magnitude
of input voltage Va.
 For instance, a 12-bit system with 1 MHz clock frequency, the counter will take (212 −
Counter Type A/D Converters
Counter Type A/D Converters
 successive approximation ADc

 The successive approximation technique uses a very efficient code search strategy to
complete n-bit conversion in just n-clock periods.
 An eight bit converter would require eight clock pulses to obtain a digital output.
 Figure shows an eight bit converter.
 The circuit uses a successive approximation register (SAR) to find the required value of
each bit by trial and error.
 successive approximation ADc

 The circuit operates as follows.

1. With the arrival of the START command, the SAR sets the MSB d1 = 1 with all other
bits to zero so that the trial code is 10000000.
2. The output Vd, of the DAC is now compared with analog input Va,.
3. If Va, is greater than the DAC output Vd then 10000000 is less than the correct digital
representation.
 successive approximation ADc
 The circuit operates as follows.
4. The MSB is left at '1' and the next lower significant bit is made 1 and further tested.
5. However, if Va, is less than the DAC output, then 10000000 is greater than the correct
digital representation.
6. So reset MSB to 0 and go on to the next lower significant bit. This procedure is
repeated for all subsequent bits, one at a time, until all bit positions have been tested.
7. Whenever the DAC output crosses Va, the comparator changes state and this can be
taken as the end of conversion (EOC) command.
 successive approximation ADc

Functional diagram of the successive approximation ADC

 successive approximation ADc

Successive approximation conversion sequence for a typical analog input

 Dual-Slope ADC
 Figure (a) shows the functional diagram of the dual-slope or dual-ramp converter.
 The Analog part of the circuit consists of a high input impedance buffer A1,, precision
integrator A2 and a voltage comparator.
 The converter first integrates the analog input signal Va, for fixed duration of 2" clock
periods as shown in Figure (b).
 Then it integrates an internal reference voltage Vr of opposite polarity until the
integrator output is zero.
 The number N of clock cycles required to return the integrator to zero is proportional
to the value of Va, averaged over the integration period.
 Hence N represents the desired output code.
 Dual-Slope ADC

 The circuit operations as follows:

 Before the START command arrives, the switch SW1, is connected to ground and
Sw2, is closed.
 Any offset voltage present in the A1, A2, and comparator loop after integration,
appears across the capacitor CAZ till the threshold of the comparator is achieved.
 The capacitor CAZ. thus provides automatic compensation for the input-offset
voltages of all the three amplifiers.
 Later, when SW2, opens, CAZ acts as a memory to hold the voltage required to keep
the offset nulled.
 Dual-Slope ADC
 The circuit operations as follows:
 At the arrival of the START command at t = t1, the control logic opens SW2, and
connects SW1, to Va, and enables the counter starting from zero.
 The circuit uses an n-stage ripple counter and therefore the counter resets to zero after
counting 2" pulses.
 The analog voltage Va, is integrated for a fixed number 2" counts of clock pulses after
which the counter resets to zero.
 If the clock period is T the integration takes place for a time T, = 2" x T and the output
is a ramp going downwards as shown in Fig. (b).
 Dual-Slope ADC
 The circuit operations as follows:
 The counter resets itself to zero at the end of the interval T, and the switch SW1, is
connected to the reference voltage (-VR).
 The output voltage V0, will now have a positive slope. As long as V0, is negative, the
output of the comparator is positive and the control logic allows the clock pulse to be
counted.
 However, when V0, becomes just zero at time t = t3, the control logic issues an end of
conversion (EOC) command and no further clock pulses enter the counter.
 It can be shown that the reading of the counter at t3, is proportional to the analog input
voltage Va.
Dual-Slope ADC
Dual-Slope ADC
Dual-Slope ADC