74HC132; 74HCT132

Quad 2-input NAND Schmitt trigger

Rev. 8 — 11 March 2024 Product data sheet

1. General description
The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined
jitter-free output signals.

2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Unlimited input rise and fall times
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Applications
• Wave and pulse shapers
• Astable multivibrators
• Monostable multivibrators

4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC132D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1
74HCT132D body width 3.9 mm
74HC132PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
74HCT132PW body width 4.4 mm
74HC132BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

5. Functional diagram
1A
1
1Y
3
1B
2

2A
4
2Y 1
6 & 3
2B 2
5

4
3A & 6
9 5
3Y
8
3B 9
10 & 8
10
A
4A
12
12 Y
4Y & 11
11 B
4B 13
13 mna409
mna407 mna408
Fig. 3. Logic diagram
Fig. 1. Logic symbol Fig. 2. IEC logic symbol (one Schmitt trigger)

6. Pinning information

6.1. Pinning

D package BQ package
SOT108-1 (SO14) SOT762-1 (DHVQFN14)
14 VCC

terminal 1
1A

1A 1 14 VCC PW package index area

SOT402-1 (TSSOP14)
1

1B 2 13 4B 1B 2 13 4B

1Y 3 12 4A 1A 1 14 VCC 1Y 3 12 4A
1B 2 13 4B 2A 4 11 4Y
2A 4 11 4Y
1Y 3 12 4A
2B 5 GND(1) 10 3B
2B 5 10 3B 2A 4 11 4Y
2Y 6 9 3A
2B 5 10 3B
7

2Y 6 9 3A
2Y 6 9 3A
GND

3Y

GND 7 8 3Y GND 7 8 3Y aaa-036072

aaa-036070 aaa-036071 Transparent top view

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder
the pad. In case soldered, the solder land should remain floating or connected to GND.

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Product data sheet Rev. 8 — 11 March 2024 2 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

6.2. Pin description

Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A 1, 4, 9, 12 data input
1B, 2B, 3B, 4B 2, 5, 10, 13 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage

7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level
Input Output
nA nB nY
L L H
L H H
H L H
H H L

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA
IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.

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Product data sheet Rev. 8 — 11 March 2024 3 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

9. Recommended operating conditions

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC132 74HCT132 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C

10. Static characteristics

Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit
+85 °C +125 °C
Min Typ Max Min Max Min Max
74HC132
VOH HIGH-level output VI = VT+ or VT-
voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level output VI = VT+ or VT-
voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 2.0 - 20 - 40 μA
VCC = 6.0 V
CI input capacitance - 3.5 - - - - - pF
74HCT132
VOH HIGH-level output VI = VT+ or VT-; VCC = 4.5 V
voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level output VI = VT+ or VT-; VCC = 4.5 V
voltage IO = 20 μA; - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V

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Product data sheet Rev. 8 — 11 March 2024 4 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit

+85 °C +125 °C
Min Typ Max Min Max Min Max
II input leakage VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 2.0 - 20 - 40 μA
VCC = 5.5 V
ΔICC additional supply per input pin; VI = VCC - 2.1 V; - 30 108 - 135 - 147 μA
current other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
CI input capacitance - 3.5 - - - - - pF

11. Dynamic characteristics

Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Fig. 5.
Symbol Parameter Conditions 25 °C −40 °C −40 °C to Unit
to +85 °C +125 °C
Min Typ Max Min Max Min Max
74HC132
tpd propagation nA, nB to nY; see Fig. 4 [1]
delay VCC = 2.0 V - 36 125 - 155 - 190 ns
VCC = 4.5 V - 13 25 - 31 - 38 ns
VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns
VCC = 6.0 V - 10 21 - 26 - 32 ns
tt transition time see Fig. 4 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
CPD power per package; [3] - 24 - - - - - pF
dissipation VI = GND to VCC
capacitance
74HCT132
tpd propagation nA, nB to nY; see Fig. 4 [1]
delay VCC = 4.5 V - 20 33 - 41 - 50 ns
VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns
tt transition time VCC = 4.5 V; see Fig. 4 [2] - 7 15 - 19 - 22 ns
CPD power per package; [3] - 20 - - - - - pF
dissipation VI = GND to VCC - 1.5 V
capacitance

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
2 2
PD = CPD × VCC × fi × N + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
∑ (CL × VCC × fo) = sum of outputs.

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Product data sheet Rev. 8 — 11 March 2024 5 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

11.1. Waveforms and test circuit

VI

nA, nB input VM

GND
tPHL tPLH
VOH
VY
nY output VM
VX
VOL
tTHL tTLH
001aai814

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 4. Input to output propagation delays

Table 8. Measurement points

Type Input Output
VM VM VX VY
74HC132 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT132 1.3 V 1.3 V 0.1VCC 0.9VCC

tW
VI
90 %
negative
VM VM
pulse
10 %
GND
tf tr
tr tf
VI
90 %
positive
VM VM
pulse
10 %
GND tW

VCC

VI VO
G DUT

RT CL

001aah768

Test data is given in Table 9.

Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig. 5. Test circuit for measuring switching times

Table 9. Test data

Type Input Load Test
VI tr, tf CL
74HC132 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT132 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL

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Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

12. Transfer characteristics

Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for waveforms see Fig. 6 to Fig. 9.
Symbol Parameter Conditions Tamb = 25 °C Tamb = −40 °C Tamb = −40 °C Unit
to +85 °C to +125 °C
Min Typ Max Min Max Min Max
74HC132
VT+ positive-going threshold VCC = 2.0 V 0.7 1.18 1.5 0.7 1.5 0.7 1.5 V
voltage VCC = 4.5 V 1.7 2.38 3.15 1.7 3.15 1.7 3.15 V
VCC = 6.0 V 2.1 3.14 4.2 2.1 4.2 2.1 4.2 V
VT- negative-going threshold VCC = 2.0 V 0.3 0.63 1.0 0.3 1.0 0.3 1.0 V
voltage VCC = 4.5 V 0.9 1.67 2.2 0.9 2.2 0.9 2.2 V
VCC = 6.0 V 1.2 2.26 3.0 1.2 3.0 1.2 3.0 V
VH hysteresis voltage VCC = 2.0 V 0.2 0.55 1.0 0.2 1.0 0.2 1.0 V
VCC = 4.5 V 0.4 0.71 1.4 0.4 1.4 0.4 1.4 V
VCC = 6.0 V 0.6 0.88 1.6 0.6 1.6 0.6 1.6 V
74HCT132
VT+ positive-going threshold VCC = 4.5 V 1.2 1.41 1.9 1.2 1.9 1.2 1.9 V
voltage VCC = 5.5 V 1.4 1.59 2.1 1.4 2.1 1.4 2.1 V
VT- negative-going threshold VCC = 4.5 V 0.5 0.85 1.2 0.5 1.2 0.5 1.2 V
voltage VCC = 5.5 V 0.6 0.99 1.4 0.6 1.4 0.6 1.4 V
VH hysteresis voltage VCC = 4.5 V 0.4 0.56 - 0.4 - 0.4 - V
VCC = 5.5 V 0.4 0.60 - 0.4 - 0.4 - V

12.1. Transfer characteristics waveforms

VO
VT+
VI VH
VT-

VI VO
VH
VT- VT+ mna207 mna208

Fig. 6. Transfer characteristics Fig. 7. Transfer characteristics definitions

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Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

aaa-003889 aaa-003890
50 500
ICC ICC
(µA) (µA)
40 400

30 300

20 200

10 100

0 0
0 1 2 0 1 2 3 4 5
VIN (V) VIN (V)

a. VCC = 2.0 V b. VCC = 4.5 V

aaa-003892
1.0
ICC
(mA)
0.8

0.6

0.4

0.2

0
0 1.2 2.4 3.6 4.8 6.0
VIN (V)

c. VCC = 6.0 V

Fig. 8. Typical 74HC132 transfer characteristics

aaa-003893 aaa-003895
1.5 1.8
ICC ICC
(mA) (mA)
1.5
1.2

1.2
0.9

0.9

0.6
0.6

0.3
0.3

0 0
0 1 2 3 4 5 0 1 2 3 4 5 6
VIN (V) VIN (V)

a. VCC = 4.5 V b. VCC = 5.5 V

Fig. 9. Typical 74HCT132 transfer characteristics

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Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

13. Application information

The slow input rise and fall times cause additional power dissipation, this can be calculated using
the following formula:
Padd = fi × (tr × ΔICC(AV) + tf × ΔICC(AV)) × VCC where:
Padd = additional power dissipation (μW);
fi = input frequency (MHz);
tr = rise time (ns); 10 % to 90 %;
ΔICC(AV) = average additional supply current (μA).
tf = fall time (ns); 90 % to 10 %;
Average ΔICC(AV) differs with positive or negative input transitions, as shown in Fig. 10 and Fig. 11.
An example of a relaxation circuit using the 74HC132; 74HCT132 is shown in Fig. 12.

aaa-003897
400
average
ICC
(µA)
300

200

positive-going
edge

100

negative-going
edge

0
0 2 4 6
VCC (V)

Fig. 10. Average additional supply current as a function of VCC for 74HC132;
linear change of VI between 0.1VCC to 0.9VCC.

aaa-003899
500
average
ICC
(µA)
400 positive-going
edge

300

200 negative-going
edge

100

0
0 2 4 6
VCC (V)

Fig. 11. Average additional supply current as a function of VCC for 74HCT132;
linear change of VI between 0.1VCC to 0.9VCC.

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Product data sheet Rev. 8 — 11 March 2024 9 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

VCC VCC

R
A
Y
B

001aac440

For 74HC132 and 74HCT132:

Typical K-factor for relaxation oscillator, see Fig. 13 and Fig. 14
Fig. 12. Relaxation oscillator

aaa-004609 aaa-004610
2.0 1.2

K K
1.0
1.5
0.8

1.0 0.6

0.4
0.5
0.2

0 0
2 3 4 5 6 4.5 5.0 5.5
VCC (V) VCC (V)

Fig. 13. K-factor for 74HC132 Fig. 14. K-factor for 74HCT132

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Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

14. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

c
y HE v M A

14 8

A2
A3 A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 5 mm
scale

Dimensions (inch dimensions are derived from the original mm dimensions)

Unit A A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y θ

max 1.75 0.25 0.51 0.25 8.75 4.0 6.2 1.27 8°

mm nom 0.25 1.27 1.05 0.2 0.25 0.1
min 0.10 1.25 0.31 0.10 8.55 3.8 5.8 0.4 0°
max 0.069 0.010 0.020 0.010 0.344 0.16 0.244 0.05 8°
inches nom 0.01 0.05 0.041 0.008 0.01 0.004
min 0.004 0.049 0.012 0.004 0.337 0.15 0.228 0.016 0°
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. sot108-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
03-02-19
SOT108-1 MS-012
23-10-27

Fig. 15. Package outline SOT108-1 (SO14)

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Product data sheet Rev. 8 — 11 March 2024 11 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

D E A
X

y HE v M A

14 8

A2 A3
A
A1
pin 1 index

θ
Lp
L
1 7
detail X
w M
e bp

0 5 mm

scale

Dimensions (mm are the original dimensions)

Unit A A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y θ

max 1.20 0.15 1.05 0.30 0.2 5.1 4.5 6.6 0.75 8°
mm nom 0.25 0.65 1 0.2 0.1 0.1
min 0.05 0.80 0.19 0.09 4.9 4.3 6.2 0.45 0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. sot402-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
03-02-18
SOT402-1 MO-153
23-10-27

Fig. 16. Package outline SOT402-1 (TSSOP14)

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Product data sheet Rev. 8 — 11 March 2024 12 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1

D B A

A
A1
E c

terminal 1 detail X
index area

terminal 1 C
e1
index area v C A B
e b y1 C y
w C
2 6
L

1 7
Eh e
14 8
k

13 9
Dh
X
k

0 2 4 mm
scale
Dimensions (mm are the original dimensions)

Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1

max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5

mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1
min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
15-04-10
SOT762-1 MO-241 15-05-05

Fig. 17. Package outline SOT762-1 (DHVQFN14)

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Product data sheet Rev. 8 — 11 March 2024 13 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

15. Abbreviations
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model

16. Revision history

Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT132 v.8 20240311 Product data sheet - 74HC_HCT132 v.7
Modifications: • Fig. 15, Fig. 16: Aligned SO and TSSOP package outline drawings to JEDEC MS-012 and
MO-153.
• Section 2: ESD specification updated according to the latest JEDEC standard.
74HC_HCT132 v.7 20210813 Product data sheet - 74HC_HCT132 v.6
Modifications: • Section 2 updated.
• Type numbers 74HC132DB and 74HCT132DB (SOT337-1/SSOP16) removed.
74HC_HCT132 v.6 20190716 Product data sheet - 74HC_HCT132 v.5
Modifications: • Type number 74HC132BQ (SOT762-1) added.
• Table 4: Derating values for Ptot total power dissipation have changed.
74HC_HCT132 v.5 20180612 Product data sheet - 74HC_HCT132 v.4
Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT132 v.4 20151201 Product data sheet - 74HC_HCT132 v.3
Modifications: • Type numbers 74HC132N and 74HCT132N (SOT27-1) removed.
74HC_HCT132 v.3 20120830 Product data sheet - 74HC_HCT132_CNV v.2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Fig. 13 and Fig. 14 added (typical K-factor for relaxation oscillator).
74HC_HCT132_CNV v.2 19970826 Product specification - -

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Product data sheet Rev. 8 — 11 March 2024 14 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
injury, death or severe property or environmental damage. Nexperia and its

17. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
Data sheet status product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product Definition Applications — Applications that are described herein for any of these
[1][2] status [3] products are for illustrative purposes only. Nexperia makes no representation
Objective [short] Development This document contains data from or warranty that such applications will be suitable for the specified use
data sheet the objective specification for without further testing or modification.
product development. Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
Preliminary [short] Qualification This document contains data from
any assistance with applications or customer product design. It is customer’s
data sheet the preliminary specification.
sole responsibility to determine whether the Nexperia product is suitable
Product [short] Production This document contains the product and fit for the customer’s applications and products planned, as well as
data sheet specification. for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
[1] Please consult the most recently issued document before initiating or
completing a design. Nexperia does not accept any liability related to any default, damage, costs
[2] The term 'short data sheet' is explained in section "Definitions". or problem which is based on any weakness or default in the customer’s
[3] The product status of device(s) described in this document may have applications or products, or the application or use by customer’s third party
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of an Nexperia product can reasonably be expected to result in personal

74HC_HCT132 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 8 — 11 March 2024 15 / 16

Nexperia 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description............................................................. 3
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 6
12. Transfer characteristics............................................. 7
12.1. Transfer characteristics waveforms........................... 7
13. Application information............................................. 9
14. Package outline........................................................ 11
15. Abbreviations............................................................ 14
16. Revision history........................................................14
17. Legal information......................................................15

© Nexperia B.V. 2024. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 11 March 2024

74HC_HCT132 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 8 — 11 March 2024 16 / 16