LD2982
LD2982
Features
■ Very low dropout voltage (120 mV at 50 mA
and 7 mV at 1 mA load)
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■ Very low quiescent current (375 mA typ. at
50 mA load and 75 mA at 1 mA)
■ Output current up to 50 mA
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■ Logic controlled electronic shutdown
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■ Output voltage of 1.8 V r
SOT23-5L
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■ Internal current and thermal limit
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■ Available in ± 1 % tolerance
(at 25 °C, A version)
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Typical application are in cellular phone,
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palmtop/laptop computer, personal digital
■ Supply voltage rejection: 45 dB (typ)
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camera.
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assistant (PDA), personal stereo, camcorder and
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■ Only 1 µF for stability
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■ Low output noise voltage 30 µVrms
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■ Smallest package SOT23-5L
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■ Temperature range: -40 °C to 125 °C
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Description
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The LD2982 is a 50 mA fixed output voltage
regulator. The ultra low drop voltage and the low
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quiescent current make them particularly suitable
for low noise, low power applications, and in
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battery powered systems. In sleep mode
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quiescent current is less than 1 µA when INHIBIT
pin is pulled low. Shutdown logic control function
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is available on pin 3 (TTL compatible). This
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means that when the device is used as local
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regulator, it is possible to put a part of the board in
standby, decreasing the total power consumption.
LD2982BM18R 1.8 V
Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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5
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Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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6.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2
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Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3
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Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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6.4
- O e P
Important . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
et
6.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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6.6 Reverse current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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c data . . . . . . .b. .s. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
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Package mechanical
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Revision rhistory . . . . . . )
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8
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1 Diagram
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2 Pin configuration
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Table 2. Pin description
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Pin n° Symbol Name and function
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1 IN Input port
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2 GND Ground pin
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3 INHIBIT
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Control switch ON/OFF. Inhibit is not internally pulled-up; it cannot be left floating.
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Disable the device when connected to GND or to a positive voltage less than 0.18V
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Bypass Pin: Capacitor to be connected to GND in order to improve the thermal noise
4 Bypass
performances
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5 OUT Output port
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Table 3. Thermal data
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Symbol Parameter SOT23-5L Unit
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RthJC
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RthJA e d u
Thermal resistance junction-case
Thermal resistance junction-ambient
81
255
°C/W
°C/W
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3 Maximum ratings
VI DC input voltage 16 V
VINH INHIBIT input voltage 16 V
IO Output current Internally limited
PD Power dissipation Internally limited
TSTG Storage temperature range -65 to 150
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°C
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TOP Operating junction temperature range -40 to 125
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Note:
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Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
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4 Electrical characteristics
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V
IO = 1 to 50mA, TJ= -40 to 125°C
VI = 2.8V
1.447
1.773 1.8
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1.553
1.827
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VO Output voltage IO = 1 to 50mA 1.764 1.836 V
Pr
IO = 1 to 50mA, TJ= -40 to 125°C 1.737 1.863
VI = 3.5V
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2.462 2.5 2.537
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VO Output voltage IO = 1 to 50mA
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2.55
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IO = 1 to 50mA, TJ= -40 to 125°C 2.412 2.587
VI = 3.8V 2.758 2.8
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VO Output voltage IO = 1 to 50mA
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IO = 1 to 50mA, TJ= -40 to 125°C 2.702 2.898
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VI = 3.85V 2.807 2.85 2.893
VO Output voltage
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IO = 1 to 50mA
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2.793 2.907 V
u c VI = 4.0V b s
IO = 1 to 50mA, TJ= -40 to 125°C 2.750
2.955 3.0
2.950
3.045
VO Output voltage
o d IO = 1 to 50mA
- O 2.94 3.06 V
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IO = 1 to 50mA, TJ= -40 to 125°C 2.895 3.105
VI = 4.1V 3.053 3.1 3.146
VO
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Output voltage
uc IO = 1 to 50mA 3.038 3.162 V
O b VO P Output voltage
VI = 4.2V
IO = 1 to 50mA
3.152
3.136
3.2 3.248
3.264 V
VI = 6.0V 4.925 5
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5.075
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VO Output voltage IO = 1 to 50mA 4.9 5.1 V
IO = 0
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IO = 0, TJ= -40 to 125°C 5
let
IO = 1mA 7 10
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IO = 1mA, TJ= -40 to 125°C 15
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VDROP Dropout voltage mV
IO = 10mA
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IO = 10mA, TJ= -40 to 125°C
40 60
90
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IO = 50mA 120 150
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IO = 50mA, TJ= -40 to 125°C 225
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IO = 0 80 100
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IO = 0, TJ= -40 to 125°C 150
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so
IO = 1mA 100 150
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Quiescent current IO = 1mA, TJ= -40 to 125°C 200
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ON MODE IO = 10mA 200 300
IQ µA
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IO = 50mA 600 900
O SVR
OFF MODE
5 Typical characteristics
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Figure 5. Dropout voltage vs. output current Figure 6.
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Quiescent current vs. load current
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Figure 7.
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Quiescent current vs. temperature Figure 8. Supply voltage rejection vs. temp.
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Figure 9. Supply voltage rejection vs. output Figure 10. Supply voltage rejection vs. output
current current
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Figure 11. Supply voltage rejection vs. P
Figure 12. Supply voltage rejection vs.
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frequency
t
frequency
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Figure 13. Line transient
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VO = 2.5V, IO = 50mA, no CI, CO = 4.7µF, tr=tf=2ns VO = 2.5V, IO = 50mA, no CI, CO = 4.7µF, tr=tf=1µs
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VO = 2.5V, IO = 0 to 50mA, no CI, CO = 10µF, tr=tf=2ns
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VO = 2.5V, IO = 0 to 50mA, no CI, CO = 4.7µF, tr=tf=2ns
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6 Application notes
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0.5" from the input pin of the device and returned to a clean analog ground. Any good quality
ceramic, tantalum or film capacitors can be used for this capacitor.
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6.3 Output capacitor
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The LD2982 is designed specifically to work with ceramic output capacitors. It may also be
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possible to use tantalum capacitors, but these are not as attractive for reasons of size and
cost. By the way, the output capacitor must meet both the requirement for minimum amount
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of capacitance and ESR (equivalent series resistance) value. Due to the different loop gain,
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the stability improves for higher output versions and so the suggested minimum output
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capacitor value, if low ESR ceramic type is used, is 1 µF for output voltages equal or major
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than 3.8 V, 2.2 µF for VO going from 1.8 to 3.3 V, and 3.3 µF for the other versions. However,
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if an output capacitor lower than the suggested one is used, it's possible to make stable the
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regulator adding a resistor in series to the capacitor.
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6.4 P
Important
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The output capacitor must maintain its ESR in the stable region over the full operating
s o r o d
temperature to assure stability. Also, capacitor tolerance and variation with temperature
must be considered to assure the minimum amount of capacitance is provided at all times.
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This capacitor should be located not more than 0.5" from the output pin of the device and
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returned to a clean analog ground.
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6.5 o Inhibit input operation
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O The inhibit pin can be used to turn OFF the regulator when pulled low, so drastically
reducing the current consumption down to less than 1 µA. When the inhibit feature is not
used, this pin must be tied to VI to keep the regulator output ON at all times. To assure
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section under VIH
VIL. Any slew rate can be used to drive the inhibit.
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mm. mils.
Dim.
Min. Typ. Max. Min. Typ. Max.
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A2 0.90 1.30 35.4 51.2
d uc 19.7
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D 2.80 3.00 110.2 118.1
l e t c t(
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E 1.50 1.75 59.0 68.8
o d
e 0.95
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37.4
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H 2.60 3.00 102.3 118.1
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L 0.10
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3.9 23.6
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7049676D
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 180 7.086
D 20.2 0.795
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N 60 2.362
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T 14.4 0.567
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Ao 3.13 3.23 3.33 0.123 0.127 0.131
Pr
Bo 3.07 3.17 3.27 0.120 0.124 0.128
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Ko 1.27 1.37 1.47 0.050 0.054 0.0.58
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Po 3.9 4.0 4.1 0.153 0.157 0.161
bs
0.153
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0.157
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8 Revision history
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