Features BlueCore® CSR8640™ BGA

■ 80MHz RISC MCU and 80MIPS Kalimba DSP Stereo Headset Solution
■ Internal ROM, serial flash memory and EEPROM
interfaces
■ Stereo codec with 2 microphone inputs Low-power Solution for
■ Radio includes integrated balun
■ 5-band fully configurable EQ
DSP Intensive Audio Applications
■ CSR's latest CVC technology for narrow-band
and wideband voice connections including wind 2-mic CVC Audio Enhancement
noise reduction
■ HFP v1.6 includes wideband speech and mSBC
codec Fully Qualified Single-chip
■ Voice recognition support for answering a call,
enables true hands-free use Bluetooth® v3.0 System
■ Multipoint HFP connection to 2 phones for voice Advance Information
■ Multipoint A2DP connection enables a headset CSR8640A03
(A2DP) connection to 2 A2DP source devices for Issue 1
music playback
■ Secure simple pairing, CSR's proximity pairing

CSR8640 BGA Data Sheet

Serial Flash /
External Memory
and CSR's proximity connection XTAL ROM EEPROM

■ Audio interfaces: I²S and PCM UART/USB

RAM
■ Serial interfaces: UART, USB 2.0 (full-speed),
2.4GHz
I²C and SPI BT _RF
Radio
Baseband I/O PIO
+
■ SBC, MP3 and AAC decoder support Balun

■ Wired audio support (USB and analogue) MCU Audio In/Out

■ Support for smartphone/tablet applications

Kalimba
■ Integrated dual switch-mode regulators, linear DSP SPI/I2C

regulators and battery charger

■ External crystal load capacitors not required for
typical crystals
■ 3 LED outputs
■ 68‑ball VFBGA 5.5 x 5.5 x 1mm 0.5mm pitch
■ Green (RoHS compliant and no antimony or
halogenated flame retardants)

General Description Applications

The BlueCore® CSR8640™ BGA is a product from ■ Stereo headsets
CSR's Connectivity Centre. It is a single-chip radio and ■ Wired stereo headsets and headphones
baseband IC for Bluetooth 2.4GHz systems. ■ Portable stereo speakers
The integrated peripherals reduce the number of The enhanced Kalimba DSP coprocessor with
external components required, including no 80MIPS supports enhanced audio and DSP
requirement for external codec, battery charger, applications.
SMPS, LDOs, balun or external program memory, The integrated audio codec supports 2 channels of
ensuring minimum production costs. ADC, 2 digital microphone inputs and stereo output, as
The battery charger architecture enables the well as a variety of audio standards.
CSR8640 BGA to independently operate from the See CSR Glossary at www.csrsupport.com.
charger supply, ensuring dependable operation for all
battery conditions.

Advance Information Page 1 of 110

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Device Details
Bluetooth Radio Physical Interfaces
■ On-chip balun (50Ω impedance in TX and RX ■ UART interface for debug
modes) ■ USB 2.0 (full-speed) interface for audio and charger
■ No trimming of external components required in enumeration
production ■ 1-bit SPI flash memory interface
■ Bluetooth v3.0 specification compliant ■ SPI interface for debug and programming
Bluetooth Transmitter ■ I²C interface for EEPROM
■ 9dBm RF transmit power with level control from on- ■ Up to 22 general purpose PIOs
chip 6-bit DAC ■ PCM and I²S interfaces
■ Class 1, Class 2 and Class 3 support without the ■ 3 LED drivers (includes RGB) with PWM flasher
need for an external power amplifier or TX/RX independent of MCU
switch Integrated Power Control and Regulation
Bluetooth Receiver ■ Automatic power switching to charger when present
■ Receiver sensitivity of -90dBm ■ 2 high-efficiency switch-mode regulators with 1.8V
■ Integrated channel filters and 1.35V outputs direct from battery supply
■ Digital demodulator for improved sensitivity and co- ■ 3.3V linear regulator for USB supply

CSR8640 BGA Data Sheet

channel rejection ■ Low-voltage linear regulator for internal digital
■ Real-time digitised RSSI available to application circuits
■ Fast AGC for enhanced dynamic range ■ Low-voltage linear regulator for internal analogue
■ Channel classification for AFH circuits
Bluetooth Synthesiser ■ Power-on-reset detects low supply voltage
■ Fully integrated synthesiser requires no external ■ Power management includes digital shutdown and
VCO, varactor diode, resonator or loop filter wake-up commands for ultra-low power modes
■ Compatible with crystals 16MHz to 32MHz Battery Charger
Kalimba DSP ■ Lithium ion / Lithium polymer battery charger
■ Enhanced Kalimba DSP coprocessor, 80MIPS, ■ Instant-on function automatically selects the power
24‑bit fixed point core supply between battery and USB, which enables
■ 2 single-cycle MACs; 24 x 24-bit multiply and 56-bit operation even if the battery is fully discharged
accumulator ■ Fast charging support up to 200mA with no external
■ 32-bit instruction word, dual 24-bit data memory components
■ 6K x 32-bit program RAM including 1K instruction
■ Higher charge currents using external pass device
cache for executing out of internal ROM ■ Supports USB charger detection
■ 16K x 24-bit + 16K x 24-bit 2-bank data RAM ■ Support for thermistor protection of battery pack
Audio Interfaces
■ Support to enable end product design to PSE law:
■ Audio codec with 2 high-quality dedicated ADCs
■ Design to JIS-C 8712/8714 (batteries)
■ Microphone bias generator and up to 2 analogue
■ Testing based on IEEE 1725
microphone inputs Baseband and Software
■ 2 digital microphone inputs (MEMS) ■ Internal ROM
■ Enhanced side-tone gain control ■ Memory protection unit supporting accelerated VM
■ Supported sample rates of 8, 11.025, 16, 22.05, 32, ■ 56KB internal RAM, enables full-speed data
44.1, 48 and 96kHz (DAC only) transfer, mixed voice/data and full piconet support
Auxiliary Features ■ Logic for forward error correction, header error
■ Crystal oscillator with built-in digital trimming control, access code correlation, CRC,
demodulation, encryption bit stream generation,
Package Option
whitening and transmit pulse shaping
■ 68‑ball VFBGA 5.5 x 5.5 x 1mm 0.5mm pitch ■ Transcoders for A-law, µ-law and linear voice from
host and A-law, µ-law and CVSD voice over air

Advance Information Page 2 of 110

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CSR8640 Stereo Headset Details
Bluetooth Profiles Headset Configurator Tool
■ Bluetooth v3.0 specification support Configures the CSR8640 stereo headset ROM software
■ HFP v1.6 wideband speech (HD voice ready) features:
■ HSP v1.2 ■ Bluetooth v3.0 specification features
■ A2DP v1.2 ■ Reconnection policies, e.g. reconnect on power-on
■ AVRCP v1.4 ■ Audio features, including default volumes
■ Support for smartphone applications (apps) ■ Button events: configuring button presses and
Improved Audio Quality durations for certain events, e.g. double press on
CSR’s latest 2-mic CVC audio enhancements for PIO for last number redial
narrowband and wideband connections including: ■ LED indications for states, e.g. headset connected,
and events, power on etc.
■ 2-mic far-end audio enhancements
■ Indication tones for events and ringtones
■ Near-end audio enhancements (noise suppression
and AEQ)
■ HFP v1.6 supported features
■ Wind noise reduction
■ Battery divider ratios and thresholds, e.g.
thresholds for battery low indication, full battery etc.
■ Packet loss concealment
■ Advanced Multipoint settings
■ Bit error concealment

CSR8640 BGA Data Sheet

■ Automatic gain control and automatic volume CSR8640 Stereo Headset Development Kit
control ■ CSR8640 stereo headset demonstrator board
■ Frequency expansion for improved speech ■ Music and voice dongle
intelligibility ■ Interface adapters and cables are available
■ mSBC codec support for wideband speech ■ Works in conjunction with the CSR8640 stereo
Music Enhancements headset Configurator tool and other supporting
utilities
■ Configurable 5-band EQ for music playback (rock,
pop, classical, jazz, dance etc)
■ For order code details contact CSR
■ SBC, MP3, AAC and Faststream decoder
■ Stereo widening (S3D)
■ Volume Boost
Additional Functionality
■ Support for voice recognition
■ Support for multi-language programmable audio
prompts
■ CSR's proximity pairing and CSR's proximity
connection
■ Multipoint support for HFP connection to 2 handsets
for voice
■ Multipoint support for A2DP connection to 2 A2DP
sources for music playback
■ Talk-time extension

Advance Information Page 3 of 110

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Functional Block Diagram
SPI_DEBUG I2C PIO Serial Flash UART R G B USB XTAL AIO[0]

2
I C/SPI LED PWM
SPI Serial Flash UART USB v2.0
Master Control and Clock
(Debug) Interface 4Mbps Full-speed AUX ADC
/Slave Output Generation
3.3V

PIO Port

DMA ports Bluetooth Modem

TX

DMA ports
Bluetooth Bluetooth Radio
BT_RF
Baseband and Balun
RX

CSR8640 BGA Data Sheet

System
RAM

MIC_AN
High-quality ADC
MIC_AP

Memory MIC_BN
High-quality ADC
Management MIC_BP
Unit
SPKR_LN
High-quality DAC
SPKR_LP
DMA ports

Audio SPKR_RN
High-quality DAC
Interface SPKR_RP

VDD_AUDIO
ROM
VDD_AUDIO_DRV

MIC Bias MIC_BIAS

Voltage / Temperature
Monitor

Switch

PIO Port
VBAT
PM 0.85V to SENSE VBAT_SENSE
80MHz MCU PMU 1.35V 1.35V
Digital 1.2V 1.8V 1.35V
Interface Low-voltage Low-voltage
Microphone 2 Low-voltage Switch- Switch- Bypass Li-ion
DM1 80MHz DSP PCM1 / I S and VDD_ANA VDD_AUX
Inputs VDD_DIG mode mode LDO Charger CHG_EXT
BIST Linear Linear
VM Accelerator (MEMS) Linear Regulator Regulator
Engine Regulator Regulator
DM2 (MPU) Regulator VCHG
SENSE SENSE SENSE SENSE SENSE
2 x Digital MICs

Digital Audio

VREGIN_DIG

VDD_DIG_MEM

VDD_ANA_RADIO

VDD_AUX_1V8

VDD_AUX

LXL_1V8

SMPS_1V8_SENSE

LX_1V35

SMPS_1V35_SENSE

3V3_USB

G-TW-0007440.4.3
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Document History
Revision Date Change Reason

1 13 JUL 11 Original publication of this document.

If you have any comments about this document, email comments@csr.com giving
number, title and section with your feedback.

CSR8640 BGA Data Sheet

Advance Information Page 5 of 110

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Status Information
The status of this Data Sheet is Advance Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information

CSR8640 BGA Data Sheet

Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Life Support Policy and Use in Safety-critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
CSR Green Semiconductor Products and RoHS Compliance
CSR8640 BGA devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the
Council on the Restriction of Hazardous Substance (RoHS).
CSR8640 BGA devices are also free from halogenated or antimony trioxide-based flame retardants and other
hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green
Semiconductor Products.
Trademarks, Patents and Licences
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by CSR plc or its
affiliates. Bluetooth ® and the Bluetooth ® logos are trademarks owned by Bluetooth ® SIG, Inc. and licensed to
CSR. Other products, services and names used in this document may have been trademarked by their respective
owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned
by CSR plc and/or its affiliates.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
Refer to www.csrsupport.com for compliance and conformance to standards information.

Advance Information Page 6 of 110

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Contents
Device Details ................................................................................................................................................. 2
CSR8640 Stereo Headset Details .................................................................................................................. 3
Functional Block Diagram .............................................................................................................................. 4
1 Package Information ..................................................................................................................................... 13
1.1 Pinout Diagram .................................................................................................................................... 13
1.2 Pin Configuration ................................................................................................................................. 14
1.3 Device Terminal Functions .................................................................................................................. 15
1.4 Package Dimensions ........................................................................................................................... 21
1.5 PCB Design and Assembly Considerations ......................................................................................... 22
1.6 Typical Solder Reflow Profile ............................................................................................................... 22
2 Bluetooth Modem .......................................................................................................................................... 23
2.1 RF Ports ............................................................................................................................................... 23
2.1.1 BT_RF .................................................................................................................................... 23
2.2 RF Receiver ......................................................................................................................................... 23
2.2.1 Low Noise Amplifier ............................................................................................................... 23

CSR8640 BGA Data Sheet

2.2.2 RSSI Analogue to Digital Converter ....................................................................................... 23
2.3 RF Transmitter ..................................................................................................................................... 24
2.3.1 IQ Modulator .......................................................................................................................... 24
2.3.2 Power Amplifier ...................................................................................................................... 24
2.4 Bluetooth Radio Synthesiser ............................................................................................................... 24
2.5 Baseband ............................................................................................................................................. 24
2.5.1 Burst Mode Controller ............................................................................................................ 24
2.5.2 Physical Layer Hardware Engine ........................................................................................... 24
3 Clock Generation .......................................................................................................................................... 25
3.1 Clock Architecture ................................................................................................................................ 25
3.2 Input Frequencies and PS Key Settings .............................................................................................. 25
3.3 Crystal Oscillator: XTAL_IN and XTAL_OUT ....................................................................................... 25
3.3.1 Crystal Calibration .................................................................................................................. 25
3.3.2 Crystal Specification ............................................................................................................... 26
4 Bluetooth Stack Microcontroller .................................................................................................................... 27
4.1 VM Accelerator .................................................................................................................................... 27
5 Kalimba DSP ................................................................................................................................................ 28
6 Memory Interface and Management ............................................................................................................. 29
6.1 Memory Management Unit .................................................................................................................. 29
6.2 System RAM ........................................................................................................................................ 29
6.3 Kalimba DSP RAM .............................................................................................................................. 29
6.4 Internal ROM ....................................................................................................................................... 29
6.5 Serial Flash Interface ........................................................................................................................... 29
7 Serial Interfaces ............................................................................................................................................ 30
7.1 USB Interface ...................................................................................................................................... 30
7.2 UART Interface .................................................................................................................................... 30
7.3 Programming and Debug Interface ...................................................................................................... 32
7.3.1 Multi-slave Operation ............................................................................................................. 32
7.4 I²C EEPROM Interface ........................................................................................................................ 32

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8 Interfaces ...................................................................................................................................................... 34
8.1 Programmable I/O Ports, PIO .............................................................................................................. 34
8.2 Analogue I/O Ports, AIO ...................................................................................................................... 34
8.3 LED Drivers ......................................................................................................................................... 34
9 Audio Interface .............................................................................................................................................. 36
9.1 Audio Input and Output ........................................................................................................................ 37
9.2 Audio Codec Interface ......................................................................................................................... 37
9.2.1 Audio Codec Block Diagram .................................................................................................. 38
9.2.2 ADC ........................................................................................................................................ 38
9.2.3 ADC Sample Rate Selection .................................................................................................. 38
9.2.4 ADC Audio Input Gain ............................................................................................................ 39
9.2.5 ADC Pre-amplifier and ADC Analogue Gain .......................................................................... 39
9.2.6 ADC Digital Gain .................................................................................................................... 39
9.2.7 ADC Digital IIR Filter .............................................................................................................. 40
9.2.8 DAC ........................................................................................................................................ 40
9.2.9 DAC Sample Rate Selection .................................................................................................. 40
9.2.10 DAC Digital Gain .................................................................................................................... 40
9.2.11 DAC Analogue Gain ............................................................................................................... 41

CSR8640 BGA Data Sheet

9.2.12 DAC Digital FIR Filter ............................................................................................................. 41
9.2.13 Microphone Input ................................................................................................................... 42
9.2.14 Digital Microphone Inputs ....................................................................................................... 43
9.2.15 Line Input ............................................................................................................................... 43
9.2.16 Output Stage .......................................................................................................................... 44
9.2.17 Mono Operation ..................................................................................................................... 44
9.2.18 Side Tone ............................................................................................................................... 45
9.2.19 Integrated Digital IIR Filter ..................................................................................................... 46
9.3 PCM1 Interface .................................................................................................................................... 47
9.3.1 PCM Interface Master/Slave .................................................................................................. 48
9.3.2 Long Frame Sync ................................................................................................................... 49
9.3.3 Short Frame Sync .................................................................................................................. 49
9.3.4 Multi-slot Operation ................................................................................................................ 49
9.3.5 GCI Interface .......................................................................................................................... 50
9.3.6 Slots and Sample Formats ..................................................................................................... 50
9.3.7 Additional Features ................................................................................................................ 51
9.3.8 PCM Timing Information ........................................................................................................ 52
9.3.9 PCM_CLK and PCM_SYNC Generation ................................................................................ 55
9.3.10 PCM Configuration ................................................................................................................. 56
9.4 Digital Audio Interface (I²S) .................................................................................................................. 56
10 Power Control and Regulation ...................................................................................................................... 60
10.1 1.8V Switch-mode Regulator ............................................................................................................... 63
10.2 1.35V Switch-mode Regulator ............................................................................................................. 63
10.3 1.8V and 1.35V Switch-mode Regulators Combined .......................................................................... 64
10.4 Bypass LDO Linear Regulator ............................................................................................................. 65
10.5 Low-voltage VDD_DIG Linear Regulator ............................................................................................. 66
10.6 Low-voltage VDD_AUX Linear Regulator ............................................................................................ 66
10.7 Low-voltage VDD_ANA Linear Regulator ............................................................................................ 66
10.8 Voltage Regulator Enable .................................................................................................................... 66

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 10.9 External Regulators and Power Sequencing ....................................................................................... 66
10.10Reset, RST# ........................................................................................................................................ 66
10.10.1 Digital Pin States on Reset .................................................................................................... 67
10.10.2 Status After Reset .................................................................................................................. 68
11 Battery Charger ............................................................................................................................................ 69
11.1 Battery Charger Hardware Operating Modes ...................................................................................... 69
11.1.1 Disabled Mode ....................................................................................................................... 70
11.1.2 Trickle Charge Mode .............................................................................................................. 70
11.1.3 Fast Charge Mode ................................................................................................................. 70
11.1.4 Standby Mode ........................................................................................................................ 70
11.1.5 Error Mode ............................................................................................................................. 70
11.2 Battery Charger Trimming and Calibration .......................................................................................... 71
11.3 VM Battery Charger Control ................................................................................................................ 71
11.4 Battery Charger Firmware and PS Keys .............................................................................................. 71
11.5 External Mode ...................................................................................................................................... 71
12 Example Application Schematic ................................................................................................................... 73
13 Electrical Characteristics .............................................................................................................................. 74
13.1 Absolute Maximum Ratings ................................................................................................................. 74

CSR8640 BGA Data Sheet

13.2 Recommended Operating Conditions .................................................................................................. 75
13.3 Input/Output Terminal Characteristics ................................................................................................. 76
13.3.1 Regulators: Available For External Use ................................................................................. 76
13.3.2 Regulators: For Internal Use Only .......................................................................................... 78
13.3.3 Regulator Enable ................................................................................................................... 79
13.3.4 Battery Charger ...................................................................................................................... 79
13.3.5 USB ........................................................................................................................................ 81
13.3.6 Clocks .................................................................................................................................... 81
13.3.7 Stereo Codec: Analogue to Digital Converter ........................................................................ 82
13.3.8 Stereo Codec: Digital to Analogue Converter ........................................................................ 83
13.3.9 Digital ..................................................................................................................................... 84
13.3.10 LED Driver Pads .................................................................................................................... 85
13.3.11 Auxiliary ADC ......................................................................................................................... 85
13.3.12 Auxiliary DAC ......................................................................................................................... 86
13.4 ESD Protection .................................................................................................................................... 87
14 Power Consumption ..................................................................................................................................... 88
15 CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 90
16 Software ........................................................................................................................................................ 92
16.1 CSR8640 Stereo Headset ................................................................................................................... 92
16.1.1 Advanced Multipoint Support ................................................................................................. 93
16.1.2 A2DP Multipoint Support ........................................................................................................ 93
16.1.3 Wired Audio Mode .................................................................................................................. 93
16.1.4 USB Modes Including USB Audio Mode ................................................................................ 94
16.1.5 Smartphone Applications (Apps) ............................................................................................ 94
16.1.6 Programmable Audio Prompts ............................................................................................... 94
16.1.7 CSR’s Intelligent Power Management ................................................................................... 95
16.1.8 Proximity Pairing .................................................................................................................... 96
16.1.9 Proximity Connection ............................................................................................................. 96
16.2 6th Generation 2-mic CVC Audio Enhancements ................................................................................ 96

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 16.2.1 Wind Noise Reduction ............................................................................................................ 97
16.2.2 Dual-microphone Signal Separation ...................................................................................... 97
16.2.3 Noise Suppression ................................................................................................................. 97
16.2.4 Acoustic Echo Cancellation .................................................................................................... 97
16.2.5 Comfort Noise Generator ....................................................................................................... 98
16.2.6 Equalisation ............................................................................................................................ 98
16.2.7 Automatic Gain Control .......................................................................................................... 98
16.2.8 Packet Loss Concealment ..................................................................................................... 98
16.2.9 Adaptive Equalisation ............................................................................................................. 98
16.2.10 Auxiliary Stream Mix .............................................................................................................. 98
16.2.11 Clipper .................................................................................................................................... 98
16.2.12 Noise Dependent Volume Control .......................................................................................... 99
16.2.13 Fixed Gains ............................................................................................................................ 99
16.2.14 Frequency Enhanced Speech Intelligibility ............................................................................ 99
16.3 Music Enhancements .......................................................................................................................... 99
16.3.1 Audio Decoders ...................................................................................................................... 99
16.3.2 Configurable EQ ................................................................................................................... 100
16.3.3 Stereo Widening (S3D) ........................................................................................................ 100

CSR8640 BGA Data Sheet

16.3.4 Volume Boost ....................................................................................................................... 101
16.4 CSR8640 Stereo Headset Development Kit ...................................................................................... 101
17 Ordering Information ................................................................................................................................... 102
17.1 CSR8640 Stereo Headset Development Kit Ordering Information .................................................... 102
18 Tape and Reel Information ......................................................................................................................... 103
18.1 Tape Orientation ................................................................................................................................ 103
18.2 Tape Dimensions ............................................................................................................................... 103
18.3 Reel Information ................................................................................................................................ 104
18.4 Moisture Sensitivity Level .................................................................................................................. 104
19 Document References ................................................................................................................................ 105
Terms and Definitions .......................................................................................................................................... 106

List of Figures
Figure 1.1 Device Pinout .................................................................................................................................. 13
Figure 1.1 Pin Configuration, Orientation from Top of Device .......................................................................... 14
Figure 2.1 Simplified Circuit BT_RF ................................................................................................................. 23
Figure 3.1 Clock Architecture ........................................................................................................................... 25
Figure 5.1 Kalimba DSP Interface to Internal Functions .................................................................................. 28
Figure 6.1 Serial Flash Interface ...................................................................................................................... 29
Figure 7.1 Universal Asynchronous Receiver .................................................................................................. 30
Figure 7.2 Example I²C EEPROM Connection ................................................................................................. 33
Figure 8.1 LED Equivalent Circuit .................................................................................................................... 35
Figure 9.1 Audio Interface ................................................................................................................................ 36
Figure 9.2 Audio Codec Input and Output Stages ............................................................................................ 38
Figure 9.3 Audio Input Gain ............................................................................................................................. 39
Figure 9.4 Microphone Biasing ......................................................................................................................... 42
Figure 9.5 Differential Input .............................................................................................................................. 43
Figure 9.6 Single-ended Input .......................................................................................................................... 44

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Figure 9.7 Speaker Output ............................................................................................................................... 44
Figure 9.8 Side Tone ........................................................................................................................................ 45
Figure 9.9 PCM Interface Master ..................................................................................................................... 48
Figure 9.10 PCM Interface Slave ....................................................................................................................... 48
Figure 9.11 Long Frame Sync (Shown with 8-bit Companded Sample) ............................................................ 49
Figure 9.12 Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 49
Figure 9.13 Multi-slot Operation with 2 Slots and 8-bit Companded Samples ................................................... 50
Figure 9.14 GCI Interface ................................................................................................................................... 50
Figure 9.15 16-bit Slot Length and Sample Formats .......................................................................................... 51
Figure 9.16 PCM Master Timing Long Frame Sync ........................................................................................... 53
Figure 9.17 PCM Master Timing Short Frame Sync .......................................................................................... 53
Figure 9.18 PCM Slave Timing Long Frame Sync ............................................................................................. 55
Figure 9.19 PCM Slave Timing Short Frame Sync ............................................................................................ 55
Figure 9.20 Digital Audio Interface Modes ......................................................................................................... 57
Figure 9.21 Digital Audio Interface Slave Timing ............................................................................................... 58
Figure 9.22 Digital Audio Interface Master Timing ............................................................................................. 59
Figure 10.1 1.80V and 1.35V Dual-supply Switch-mode System Configuration ................................................ 61
Figure 10.2 1.80V Parallel-supply Switch-mode System Configuration ............................................................. 62

CSR8640 BGA Data Sheet

Figure 10.3 1.8V Switch-mode Regulator Output Configuration ........................................................................ 63
Figure 10.4 1.35V Switch-mode Regulator Output Configuration ...................................................................... 64
Figure 10.5 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration ...................................... 65
Figure 11.1 Battery Charger Mode-to-Mode Transition Diagram ....................................................................... 70
Figure 11.2 Battery Charger External Mode Typical Configuration .................................................................... 72
Figure 16.1 Programmable Audio Prompts in External SPI Flash ..................................................................... 95
Figure 16.2 Programmable Audio Prompts in External I²C EEPROM ................................................................ 95
Figure 16.3 2-mic CVC Block Diagram .............................................................................................................. 97
Figure 16.4 Configurable EQ GUI with Drag Points ......................................................................................... 100
Figure 16.5 Volume Boost GUI with Drag Points ............................................................................................. 101
Figure 18.1 Tape Orientation ........................................................................................................................... 103
Figure 18.2 Tape Dimensions .......................................................................................................................... 103
Figure 18.3 Reel Dimensions ........................................................................................................................... 104

List of Tables
Table 3.1 Crystal Specification ......................................................................................................................... 26
Table 7.1 Possible UART Settings ................................................................................................................... 31
Table 7.2 Standard Baud Rates ....................................................................................................................... 31
Table 8.1 Alternative PIO Functions ................................................................................................................. 34
Table 9.1 Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface ............................. 36
Table 9.2 ADC Audio Input Gain Rate ............................................................................................................. 40
Table 9.3 DAC Digital Gain Rate Selection ...................................................................................................... 41
Table 9.4 DAC Analogue Gain Rate Selection ................................................................................................. 41
Table 9.5 Sidetone Gain ................................................................................................................................... 46
Table 9.6 PCM Master Timing .......................................................................................................................... 52
Table 9.7 PCM Slave Timing ............................................................................................................................ 54
Table 9.8 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 56
Table 9.9 Digital Audio Interface Slave Timing ................................................................................................ 57

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Table 9.10 I²S Slave Mode Timing ..................................................................................................................... 58
Table 9.11 Digital Audio Interface Master Timing .............................................................................................. 59
Table 9.12 I²S Master Mode Timing Parameters, WS and SCK as Outputs ...................................................... 59
Table 10.1 Recommended Configurations for Power Control and Regulation ................................................... 60
Table 10.2 Pin States on Reset .......................................................................................................................... 67
Table 11.1 Battery Charger Operating Modes Determined by Battery Voltage and Current ............................. 69
Table 13.1 ESD Handling Ratings ...................................................................................................................... 87
Table 15.1 Chemical Limits for Green Semiconductor Products ........................................................................ 90

List of Equations
Equation 3.1 Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET .............................................................. 26
Equation 3.2 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402.0168MHz .......................................... 26
Equation 3.3 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz .......................................... 26
Equation 7.1 Baud Rate ....................................................................................................................................... 31
Equation 8.1 LED Current .................................................................................................................................... 35
Equation 8.2 LED PAD Voltage ............................................................................................................................ 35
Equation 9.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 47

CSR8640 BGA Data Sheet

Equation 9.2 IIR Filter Plus DC Blocking Transfer Function, HDC(z) .................................................................... 47
Equation 9.3 PCM_CLK Frequency Generated Using the Internal 48MHz Clock ................................................ 56
Equation 9.4 PCM_SYNC Frequency Relative to PCM_CLK ............................................................................... 56

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1 Package Information
1.1 Pinout Diagram
Orientation from Top of Device

1 2 3 4 5 6 7 8 9 10

A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10

C C1 C2 C9 C10

CSR8640 BGA Data Sheet

D D1 D2 D9 D10

E E1 E2 E5 E6 E9 E10

F F1 F2 F5 F6 F9 F10

G G1 G2 G9 G10

H H1 H2 H9 H10

J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
G-TW-0007438.1.1

K K1 K2 K3 K4 K5 K6 K7 K8 K9 K10

Figure 1.1: Device Pinout

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 1.2 Pin Configuration
1 2 3 4 5 6 7 8 9 10

A VDD_AUX_1V8 VSS_BT_LO_AUX BT_RF SPKR_LP VSS_AUDIO SPKR _RP VDD_AUDIO AU_REF MIC_AP MIC_AN A

B XTAL_OUT VDD_AUX VSS_BT_RF SPKR _LN VDD_AUDIO_DRV SPKR _RN MIC_BP MIC_BN MIC_BIAS LED[2] B

C XTAL_IN VDD_ANA_RADIO PIO[19] PIO[20] C

CSR8640 BGA Data Sheet

D PIO [15] AIO[0] PIO[18] PIO[21] D

E PIO [4] PIO[12] VDD_PADS_1 VDD_PADS_2 PIO[6] PIO[8] E

F PIO [16] PIO[14] PIO[10] VSS_DIG PIO[0] PIO[1] F

G PIO [13] PIO[11] PIO[9] PIO[7] G

G-TW-0008090.2.3
H PIO [2] PIO[17] SMPS_1V8_SENSE USB_P H

J PIO [5] LED [0] RST# SPI_PCM# PIO[3] CHG_EXT VBAT_SENSE VSS_SMPS_1V8 3V3_USB USB_N J

K LED [1] VDD_DIG_MEM VREGIN _DIG VREGENABLE VCHG LX_1V8 VBAT LX_1V35 VSS_SMPS_1V35 SMPS_1V35_SENSE K

1 2 3 4 5 6 7 8 9 10

Figure 1.1: Pin Configuration, Orientation from Top of Device

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1.3 Device Terminal Functions
Radio Ball Pad Type Supply Domain Description

Bluetooth 50Ω transmitter output /

BT_RF A3 RF VDD_ANA_RADIO
receiver input

Oscillator Ball Pad Type Supply Domain Description

XTAL_IN C1 For crystal or external clock input

Analogue VDD_AUX
XTAL_OUT B1 Drive for crystal

USB Ball Pad Type Supply Domain Description

USB data plus with selectable internal

USB_P H10
1.5kΩ pull-up resistor
Bidirectional 3V3_USB

CSR8640 BGA Data Sheet

USB_N J10 USB data minus

SPI/PCM Interface Ball Pad Type Supply Domain Description

SPI/PCM# select input:

Input with weak pull-
SPI_PCM# J4 VDD_PADS_1 ■ 0 = PCM/PIO interface
down
■ 1 = SPI

Note:

SPI and PCM1 interfaces are mapped as alternative functions on the PIO port.

PIO Port Ball Pad Type Supply Domain Description

Bidirectional with weak

PIO[21] D10 VDD_PADS_2 Programmable input / output line 21.
pull-down

Bidirectional with weak

PIO[20] C10 VDD_PADS_2 Programmable input / output line 20.
pull-down

Bidirectional with weak

PIO[19] C9 VDD_PADS_2 Programmable input / output line 19.
pull-down

Bidirectional with weak

PIO[18] D9 VDD_PADS_2 Programmable input / output line 18.
pull-down

Programmable input / output line 17.

Bidirectional with strong Alternative functions:
PIO[17] H2 VDD_PADS_1
pull-down ■ UART_CTS: UART clear to send,
active low

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PIO Port Ball Pad Type Supply Domain Description

Programmable input / output line 16.

Bidirectional with strong Alternative functions:
PIO[16] F1 VDD_PADS_1
pull-up ■ UART_RTS: UART request to
send, active low

Programmable input / output line 15.

Bidirectional with strong
PIO[15] D1 VDD_PADS_1 Alternative functions:
pull-up
■ UART_TX: UART data output

Programmable input / output line 14.

Bidirectional with strong
PIO[14] F2 VDD_PADS_1 Alternative functions:
pull-up
■ UART_RX: UART data input

Programmable input / output line 13.

Bidirectional with strong Alternative function:
PIO[13] G1 VDD_PADS_1
pull-down ■ QSPI_IO[1]: serial quad I/O flash
data bit 1

CSR8640 BGA Data Sheet

Programmable input / output line 12.
Alternative function:
Bidirectional with strong ■ QSPI_FLASH_CS#: serial quad
PIO[12] E2 VDD_PADS_2
pull-up I/O flash chip select
■ I2C_WP: I²C bus memory write
protect line

Programmable input / output line 11.

Alternative function:
Bidirectional with strong
PIO[11] G2 VDD_PADS_1 ■ QSPI_IO[0]: serial quad I/O flash
pull-down
data bit 0
■ I2C_SDA: I²C serial data line

Programmable input / output line 10.

Alternative function:
Bidirectional with strong
PIO[10] F5 VDD_PADS_1 ■ QSPI_FLASH_CLK: serial quad
pull-down
I/O flash clock
■ I2C_SCL: I²C serial clock line

Bidirectional with strong

PIO[9] G9 VDD_PADS_2 Programmable input / output line 9.
pull-down

Bidirectional with strong

PIO[8] E10 VDD_PADS_2 Programmable input / output line 8.
pull-up

Bidirectional with strong

PIO[7] G10 VDD_PADS_2 Programmable input / output line 7.
pull-down

Bidirectional with strong

PIO[6] E9 VDD_PADS_2 Programmable input / output line 6.
pull-down

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PIO Port Ball Pad Type Supply Domain Description

Programmable input / output line 5.

Alternative functions:
Bidirectional with weak
PIO[5] J1 VDD_PADS_1 ■ SPI_CLK: SPI clock
pull-down
■ PCM1_CLK: PCM1 synchronous
data clock

Programmable input / output line 4.

Alternative functions:
Bidirectional with weak ■ SPI_CS#: chip select for SPI, active
PIO[4] E1 VDD_PADS_1
pull-down low
■ PCM1_SYNC: PCM1 synchronous
data sync

Programmable input / output line 3.

Alternative functions:
Bidirectional with weak
PIO[3] J5 VDD_PADS_1 ■ SPI_MISO: SPI data output
pull-down
■ PCM1_OUT: PCM1 synchronous
data output

CSR8640 BGA Data Sheet

Programmable input / output line 2.
Alternative functions:
Bidirectional with weak
PIO[2] H1 VDD_PADS_1 ■ SPI_MOSI: SPI data input
pull-down
■ PCM1_IN: PCM1 synchronous data
input

Bidirectional with strong

PIO[1] F10 VDD_PADS_2 Programmable input / output line 1.
pull-up

Bidirectional with strong

PIO[0] F9 VDD_PADS_2 Programmable input / output line 0.
pull-up

Analogue programmable input / output

AIO[0] D2 Bidirectional VDD_AUX
line 0.

Test and Debug Ball Pad Type Supply Domain Description

Reset if low. Pull low for minimum 5ms to

RST# J3 Input with strong pull-up VDD_PADS_1
cause a reset.

Codec Ball Pad Type Supply Domain Description

MIC_AP A9 Microphone input positive, channel A

Analogue in VDD_AUDIO
MIC_AN A10 Microphone input negative, channel A

MIC_BP B7 Microphone input positive, channel B

Analogue in VDD_AUDIO
MIC_BN B8 Microphone input negative, channel B

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Codec Ball Pad Type Supply Domain Description

MIC_BIAS B9 Analogue out VBAT / 3V3_USB Microphone bias

SPKR_LP A4 Speaker output positive, left

Analogue out VDD_AUDIO_DRV
SPKR_LN B4 Speaker output negative, left

SPKR_RP A6 Speaker output positive, right

Analogue out VDD_AUDIO_DRV
SPKR_RN B6 Speaker output negative, right

Decoupling of audio reference (for high-

AU_REF A8 Analogue in VDD_AUDIO
quality audio)

LED Drivers Ball Pad Type Supply Domain Description

LED driver.
Alternative function: programmable

CSR8640 BGA Data Sheet

output PIO[31]
LED[2] B10 Note:
As output is open-drain, an external
pull-up is required when PIO[31] is
configured as a programmable
output.

LED driver.
Alternative function: programmable
output PIO[30].
LED[1] K1 Bidirectional VDD_PADS_1 Note:
As output is open-drain, an external
pull-up is required when PIO[30] is
configured as a programmable
output.

LED driver.
Alternative function: programmable
output PIO[29].
LED[0] J2 Note:
As output is open-drain, an external
pull-up is required when PIO[29] is
configured as a programmable
output.

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Power Supplies and Control Ball Description

3.3V bypass linear regulator output

3V3_USB J9 Positive supply for USB port
Connect external minimum 2.2µF ceramic decoupling capacitor

External battery charger control

CHG_EXT J6 External battery charger transistor base control when using
external charger boost. Otherwise leave unconnected.

LX_1V35 K8 1.35V switch-mode power regulator inductor connection

LX_1V8 K6 1.8V switch-mode power regulator inductor connection

SMPS_1V35_SENSE K10 1.35V switch-mode power regulator sense input

SMPS_1V8_SENSE H9 1.8V switch-mode power regulator sense input

VBAT K7 Battery positive terminal

CSR8640 BGA Data Sheet

Battery charger sense input
VBAT_SENSE J7
Connect directly to the battery positive pin.

Charger input
VCHG K5
Typically connected to VBUS (USB supply) as Section 12 shows

Bluetooth radio supply

VDD_ANA_RADIO C2
Connect to 1.35V supply, see Section 12 for connections

Positive supply for audio

VDD_AUDIO A7
Connect to 1.35V supply, see Section 12 for connections

Positive supply for audio output amplifiers

VDD_AUDIO_DRV B5
Connect to 1.8V supply

Auxiliary supply
VDD_AUX B2
Connect to 1.35V supply, see Section 12 for connections

Auxiliary LDO regulator input

VDD_AUX_1V8 A1
Connect to 1.8V supply, see Section 12 for connections

VDD_DIG_MEM K2 Digital LDO regulator output, see Section 12 for connections

VDD_PADS_1 E5 1.8V positive supply input for input/output ports

VDD_PADS_2 E6 1.8V positive supply input for input/output ports

Regulator enable input.

Can also be sensed as an input.
VREGENABLE K4 Regulator enable and multifunction button. A high input (tolerant to
VBAT) enables the on-chip regulators, which can then be latched
on internally and the button used as a multifunction input.

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Power Supplies and Control Ball Description

Digital LDO regulator input, see Section 12 for connections

VREGIN_DIG K3
Connect to a 1.35V supply

VSS_AUDIO A5 Ground connection for audio and audio driver

Ground connections for analogue circuitry and Bluetooth radio local

VSS_BT_LO_AUX A2
oscillator

VSS_BT_RF B3 Bluetooth radio ground

VSS_DIG F6 Ground connection for internal digital circuitry

VSS_SMPS_1V35 K9 1.35V switch-mode regulator ground

VSS_SMPS_1V8 J8 1.8V switch-mode regulator ground

CSR8640 BGA Data Sheet

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1.4 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
Top View

a C A 0.8 0.87 1.0 e - 0.5 -

D C A
2X (A3)
(A2)
A A1
A1 0.16 - 0.26 f - 0.10 -

CSR8640 BGA Data Sheet

A2 - 0.21 - g - 0.08 -

A3 - 0.45 - h - 0.15 -
E
a - 0.05 - j - 0.08 -

b 0.27 - 0.37 n - 68 -

a C
3 D 5.45 5.5 5.55 SD - 0.25 -
A1 Corner f C
2X C
Index Area
g C Seating D1 - 4.5 - SE - 0.25 -
Plane
2

E 5.45 5.5 5.55 Ball diam. - 0.3 -

Bottom View
10 9 8 7 6 5 4 3 2 1
Solder land
f E1 - 4.5 - - 0.275 -
A opening
B

SE
C
Notes 1. Dimension b is measured at the maximum solder ball diameter,
parallel to datum plane C.
D
E
E1
F 2. Datum C (seating plane) is defined by the spherical crowns of
G
the solder ball.
e
H 3. Parallelism measurement shall exclude any effect of mark on
J top surface of package.
K
g
Description 68-ball Very Thin, Fine Pitch Ball Grid Array (VFBGA) Package
G-TW-0007437.4.2

SD
h e j nX Øb 1
D1 Øh M C A B Size 5.5 x 5.5 x 1mm JEDEC MO-225
Øj M C

Pitch 0.5mm Units mm

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1.5 PCB Design and Assembly Considerations
This section lists recommendations to achieve maximum board-level reliability of the 5.5 x 5.5 x 1mm VFBGA 68‑ball
package:
■ NSMD lands, i.e. lands smaller than the solder mask aperture, are preferred because of the greater
accuracy of the metal definition process compared to the solder mask process. With solder mask defined
pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which
can cause stress concentration and act as a point for crack initiation.
■ Ideally, use via-in-pad technology to achieve truly NSMD lands. Where this is not possible, a maximum of
one trace connected to each land is preferred and this trace should be as thin as possible, this needs to
take into consideration its current carrying and the RF requirements.
■ 35µm thick (1oz) copper lands are recommended rather than 17µm thick (0.5oz). This results in a greater
standoff which has been proven to provide greater reliability during thermal cycling.
■ Land diameter should be the same as that on the package to achieve optimum reliability.
■ Solder paste is preferred to flux during the assembly process because this adds to the final volume of solder
in the joint, increasing its reliability.
■ When using a nickel gold plating finish, the gold thickness should be kept below 0.5µm to prevent brittle
gold/tin intermetallics forming in the solder.

1.6 Typical Solder Reflow Profile

CSR8640 BGA Data Sheet

See Typical Solder Reflow Profile for Lead-free Devices for information.

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2 Bluetooth Modem
2.1 RF Ports
2.1.1 BT_RF
CSR8640 BGA contains an on-chip balun which combines the balanced outputs of the PA on transmit and produces
the balanced input signals for the LNA required on receive. No matching components are needed as the receive
mode impedance is 50Ω and the transmitter has been optimised to deliver power in a 50Ω load.

VDD

_ On-chip Balun
PA BT_RF
+
VSS_BT_RF

CSR8640 BGA Data Sheet

G-TW-0005523.2.2
+
LNA
_

Figure 2.1: Simplified Circuit BT_RF

2.2 RF Receiver
The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die.
Sufficient out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to
GSM and W‑CDMA cellular phone transmitters without being desensitised. A digital FSK discriminator means that
no discriminator tank is needed and its excellent performance in the presence of noise enables CSR8640 BGA to
exceed the Bluetooth requirements for co‑channel and adjacent channel rejection.
For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed
to the EDR modem.

2.2.1 Low Noise Amplifier

The LNA operates in differential mode and takes its input from the balanced port of the on-chip balun.

2.2.2 RSSI Analogue to Digital Converter

The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference-limited environments.

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2.3 RF Transmitter
2.3.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.

2.3.2 Power Amplifier

The internal PA output power is software controlled and configured through a PS Key. The internal PA on the
CSR8640 BGA has a maximum output power that enables it to operate as a Class 1, Class 2 and Class 3
Bluetooth radio without requiring an external RF PA.

2.4 Bluetooth Radio Synthesiser

The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening
can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time
across the guaranteed temperature range to meet the Bluetooth v3.0 specification.

2.5 Baseband
2.5.1 Burst Mode Controller

CSR8640 BGA Data Sheet

During transmission the BMC constructs a packet from header information previously loaded into memory-mapped
registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception,
the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer
in RAM. This architecture minimises the intervention required by the processor during transmission and reception.

2.5.2 Physical Layer Hardware Engine

Dedicated logic performs:
■ Forward error correction
■ Header error control
■ Cyclic redundancy check
■ Encryption
■ Data whitening
■ Access code correlation
■ Audio transcoding
Firmware performs the following voice data translations and operations:
■ A-law/µ-law/linear voice data (from host)
■ A-law/µ-law/CVSD (over the air)
■ Voice interpolation for lost packets
■ Rate mismatch correction
The hardware supports all optional and mandatory features of the Bluetooth v3.0 specification including AFH and
eSCO.

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3 Clock Generation
CSR8640 BGA requires a Bluetooth reference clock frequency of 16MHz to 32MHz from an externally connected
crystal.
All CSR8640 BGA internal digital clocks are generated using a phase locked loop, which is locked to the frequency
of the external reference clock source or safely free-runs at a reduced frequency if clock not present.

3.1 Clock Architecture

Bluetooth
Reference Clock
Radio

G-TW-0000189.3.3
Auxiliary Digital
PLL Circuitry

CSR8640 BGA Data Sheet

Figure 3.1: Clock Architecture

3.2 Input Frequencies and PS Key Settings

CSR8640 BGA is configured to operate with a chosen reference frequency. PSKEY_ANA_FREQ sets this reference
frequency for all frequencies using an integer multiple of 250kHz. The input frequency default setting for
CSR8640 BGA is 26MHz depending on the software build. Full details are in the software release note for the specific
build from www.csrsupport.com.

3.3 Crystal Oscillator: XTAL_IN and XTAL_OUT

CSR8640 BGA contains a crystal driver circuit that acts as a transconductance amplifier driving an external crystal
between XTAL_IN and XTAL_OUT. The crystal driver circuit forms a Pierce oscillator with the external crystal. No
external crystal load capacitors are required for typical crystals.

3.3.1 Crystal Calibration

The actual crystal frequency depends on the capacitance of XTAL_IN and XTAL_OUT on the PCB and the
CSR8640 BGA, as well as the capacitance of the crystal. Correct calibration of the Bluetooth radio is done on a per-
device basis on the production line, with the trim value stored in non-volatile memory (PS Key).
Crystal calibration uses a single measurement. The measurement finds the actual offset from the desired frequency
and the offset is stored in PSKEY_ANA_FTRIM_OFFSET. The firmware then compensates for the frequency offset
on the CSR8640 BGA. Typically, a TXSTART radio test is performed to obtain the actual frequency and it is compared
against the output frequency with the requested frequency using an RF analyser. The test station calculates the
offset ratio and programs it into PSKEY_ANA_FTRIM_OFFSET. The value in PSKEY_ANA_FTRIM_OFFSET is a
16-bit 2's complement signed integer which specifies the fractional part of the ratio between the true crystal
frequency, factual, and the value set in PSKEY_ANA_FREQ, fnominal. Equation 3.1 shows the value of
PSKEY_ANA_FTRIM_OFFSET in parts per 220 rounded to the nearest integer.
For more information on TXSTART radio test see BlueTest User Guide.

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 factual
PSKEY_ANA_FTRIM_OFFSET = ( − 1) × 220
fnominal

Equation 3.1: Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET

For a requested frequency of 2402MHz with an actual output of 2402.0168MHz the PSKEY_ANA_FTRIM_OFFSET
value is 7, see Equation 3.2.
2402.0168
PSKEY_ANA_FTRIM_OFFSET = ( − 1) × 220 ≈ 7
2402
Equation 3.2: Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402.0168MHz
For a requested frequency of 2402MHz with an actual output of 2401.9832MHz the PSKEY_ANA_FTRIM_OFFSET
value is -7 (0xfff9), see Equation 3.3.
2401.9832
PSKEY_ANA_FTRIM_OFFSET = ( − 1) × 220 ≈ −7
2402
Equation 3.3: Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz

3.3.2 Crystal Specification

Table 3.1 shows the specification for an external crystal.

CSR8640 BGA Data Sheet

Parameter Min Typ Max Unit

Frequency 16 26 32 MHz

Crystal load capacitance - 9 - pF

Frequency Stability - - 20 ppm

Frequency Tolerance - - ±20 ppm

Pullability 10 15 30 ppm/pF

Transconductance 2 - - mS

Table 3.1: Crystal Specification

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4 Bluetooth Stack Microcontroller
The CSR8640 BGA uses a 16-bit RISC 80MHz MCU for low power consumption and efficient use of memory. It
contains a single-cycle multiplier and a memory protection unit for the VM accelerator, see Section 4.1.
The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and
host interfaces.

4.1 VM Accelerator
CSR8640 BGA contains a VM accelerator alongside the MCU. This hardware accelerator improves the performance
of VM applications.

CSR8640 BGA Data Sheet

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5 Kalimba DSP
The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over-air data
or codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks
within CSR8640 BGA.

Kalimba DSP Core

MCU Register Interface (including Debug)

Memory
Management
Unit
DSP MMU Port
Data Memory Address
Inteface Generators

Registers
Instruction Decode ALU
DSP, MCU and Memory Window Control
Program Flow DEBUG

Clock Select PIO

PIO In/Out
DSP Program Control

Programmable Clock = 80MHz Internal Control Register IRQ to Subsystem

MMU Interface

CSR8640 BGA Data Sheet

Interrupt Controller IRQ from Subsystem
Timer 1µs Timer Clock
DSP RAMs MCU Window

Flash Window
DM2 DSP Data Memory 2 Interface (DM2)

DM1 DSP Data Memory 1 Interface (DM1)

G-TW-0005522.2.2
PM DSP Program Memory Interface (PM)

Figure 5.1: Kalimba DSP Interface to Internal Functions

The key features of the DSP include:
■ 80MIPS performance, 24-bit fixed point DSP core
■ 2 single‑cycle MACs; 24 x 24-bit multiply and 56-bit accumulate
■ 32-bit instruction word
■ Separate program memory and dual data memory, allowing an ALU operation and up to 2 memory accesses
in a single cycle
■ Zero overhead looping, including a very low-power 32-instruction cache
■ Zero overhead circular buffer indexing
■ Single cycle barrel shifter with up to 56-bit input and 56-bit output
■ Multiple cycle divide (performed in the background)
■ Bit reversed addressing
■ Orthogonal instruction set
■ Low overhead interrupt
For more information see Kalimba Architecture 3 DSP User Guide.

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6 Memory Interface and Management
6.1 Memory Management Unit
The MMU provides dynamically allocated ring buffers that hold the data that is in transit between the host, the air or
the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and is performed
by a hardware MMU to minimise the overheads on the processor during data/voice transfers. The use of DMA ports
also helps with efficient transfer of data to other peripherals.

6.2 System RAM

56KB of integrated RAM supports the RISC MCU and is shared between the ring buffers for holding voice/data for
each active connection and the general-purpose memory required by the Bluetooth stack.

6.3 Kalimba DSP RAM

Additional integrated RAM provides support for the Kalimba DSP:
■ 16K x 24-bit for data memory 1 (DM1)
■ 16K x 24-bit for data memory 2 (DM2)
■ 6K x 32-bit for program memory (PM)

CSR8640 BGA Data Sheet

6.4 Internal ROM
Internal ROM is provided for system firmware implementation.

6.5 Serial Flash Interface

CSR8640 BGA supports external serial flash ICs. This enables additional data storage areas for device-specific
data. CSR8640 BGA supports serial single I/O devices with a 1-bit I/O flash-memory interface.
Figure 6.1 shows a typical connection between the CSR8640 BGA and a serial flash IC.

1.8V
Serial Quad I/O Flash
MCU Program VDD

MCU RESET#/HOLD#/IO3

WP#/IO2
MCU Data QSPI_FLASH_CLK
CLK
Memory
Serial Flash

QSPI_FLASH_CS#
Interface

Management CS#
Unit QSPI_IO[0]
DI/IO0
Kalimba DSP Program QSPI_IO[1]
G-TW-0008502.1.2

DO/IO1

Kalimba DSP

Kalimba DSP Data

Figure 6.1: Serial Flash Interface

CSR8640 BGA supports Winbond, Microchip/SST, Macronix and compatible serial flash devices for PS Key and
voice prompt storage up to 64Mb.

Advance Information Page 29 of 110

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7 Serial Interfaces
7.1 USB Interface
CSR8640 BGA has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices.
The USB interface on CSR8640 BGA acts as a USB peripheral, responding to requests from a master host controller.
CSR8640 BGA contains internal USB termination resistors and requires no external resistor matching.
CSR8640 BGA supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification), supports
USB standard charger detection and fully supports the USB Battery Charging Specification, available from http://
www.usb.org. For more information on how to integrate the USB interface on CSR8640 BGA see the Bluetooth and
USB Design Considerations Application Note.
As well as describing USB basics and architecture, the application note describes:
■ Power distribution for high and low bus-powered configurations
■ Power distribution for self-powered configuration, which includes USB VBUS monitoring
■ USB enumeration
■ Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of
ferrite beads
■ USB suspend modes and Bluetooth low-power modes:

CSR8640 BGA Data Sheet

■ Global suspend
■ Selective suspend, includes remote wake
■ Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
■ Suspend mode current draw
■ PIO status in suspend mode
■ Resume, detach and wake PIOs
■ Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend
modes and USB VBUS voltage consideration
■ USB termination when interface is not in use
■ Internal modules, certification and non-specification compliant operation

7.2 UART Interface

CSR8640 BGA has an optional standard UART serial interface that provides a simple mechanism for communicating
with other serial devices using the RS232 protocol, including for test and debug. The UART interface is multiplexed
with PIOs and other functions.
Figure 7.1 shows the 4 signals that implement the UART function.

PIO[15]/UART_TX

PIO[14]/UART_RX

PIO[16]/UART_RTS
G-TW-0008555.1.1

PIO[17]/UART_CTS

Figure 7.1: Universal Asynchronous Receiver

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When CSR8640 BGA is connected to another digital device, UART_RX and UART_TX transfer data between the 2
devices. The remaining 2 signals, UART_CTS and UART_RTS, implement optional RS232 hardware flow control
where both are active low indicators.
UART configuration parameters, such as baud rate and packet format, are set using CSR8640 BGA firmware.
Note:

To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated
serial port adapter card.
Table 7.1 shows the possible UART settings.

Parameter Possible Values

1200 baud (≤2%Error)

Minimum
Baud rate 9600 baud (≤1%Error)

Maximum 4Mbaud (≤1%Error)

Flow control RTS/CTS or None

CSR8640 BGA Data Sheet

Parity None, Odd or Even

Number of stop bits 1 or 2

Bits per byte 8

Table 7.1: Possible UART Settings

Note:

Load the DFU boot loader into the internal ROM before using the UART or USB interface. Use the SPI for this
initial flash programming.
Table 7.2 lists common baud rates and their associated values for the PSKEY_UART_BAUDRATE. There is no
requirement to use these standard values. Any baud rate within the supported range is set in the PS Key according
to the formula in Equation 7.1.
PSKEY_UART_BAUDRATE
Baud Rate =
0.004096
Equation 7.1: Baud Rate

Persistent Store Value

Baud Rate Error
Hex Dec

1200 0x0005 5 1.73%

2400 0x000a 10 1.73%

4800 0x0014 20 1.73%

9600 0x0027 39 -0.82%

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 Persistent Store Value
Baud Rate Error
Hex Dec

19200 0x004f 79 0.45%

38400 0x009d 157 -0.18%

57600 0x00ec 236 0.03%

76800 0x013b 315 0.14%

115200 0x01d8 472 0.03%

230400 0x03b0 944 0.03%

460800 0x075f 1887 -0.02%

921600 0x0ebf 3775 0.00%

CSR8640 BGA Data Sheet

1382400 0x161e 5662 -0.01%

1843200 0x1d7e 7550 0.00%

2764800 0x2c3d 11325 0.00%

3686400 0x3afb 15099 0.00%

Table 7.2: Standard Baud Rates

7.3 Programming and Debug Interface

CSR8640 BGA provides a debug SPI interface for programming, configuring (PS Keys) and debugging the
CSR8640 BGA. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI/PCM# line
are brought out to either test points or a header. To use the SPI interface, the SPI/PCM# line requires the option of
being pulled high externally.
CSR provides development and production tools to communicate over the SPI from a PC, although a level translator
circuit is often required. All are available from CSR.

7.3.1 Multi-slave Operation

Avoid connecting CSR8640 BGA in a multi-slave arrangement by simple parallel connection of slave MISO lines.
When CSR8640 BGA is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, CSR8640 BGA
outputs 0 if the processor is running or 1 if it is stopped.

7.4 I²C EEPROM Interface

CSR8640 BGA supports optional I²C EEPROM for storage of PS Keys and voice prompt data if SPI flash is not used.
Figure 7.2 shows an example I²C EEPROM connection where:
■ PIO[10] is the I²C EEPROM SCL line
■ PIO[11] is the I²C EEPROM SDA line
■ PIO[12] is the I²C EEPROM WP line

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 1.8V C1

R1 R2 R3 10nF
2.2kΩ 2.2kΩ 2.2kΩ U1
8 1
VCC A0
PIO[12]/QSPI_FLASH_CS#/I2C_WP 7 2
WP A1

G-TW-0008557.1.1
PIO[10]/QSPI_FLASH_CLK/I2C_SCL 6 3
SCL A2
PIO[11]/QSPI_IO[0]/I2C_SDA 5 4
SDA VSS
24AAxxx

Figure 7.2: Example I²C EEPROM Connection

Note:

The I²C EEPROM requires external pull-up resistors, see Figure 7.2.
CSR recommends 400kHz capable I²C EEPROMs.

CSR8640 BGA Data Sheet

Advance Information Page 33 of 110

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8 Interfaces
8.1 Programmable I/O Ports, PIO
CSR8640 BGA provides 22 lines of programmable bidirectional I/O, PIO[21:0]. Some of the PIOs on the
CSR8640 BGA have alternative functions, see Table 8.1.

Function

PIO
Debug SPI SPI Flash UART PCM EEPROM
(See Section 7.3) (See Section 6.5) (See Section 7.2) (See Section 9.3) (See Section 7.4)

PIO[2] SPI_MOSI - - PCM1_IN -

PIO[3] SPI_MISO - - PCM1_OUT -

PIO[4] SPI_CS# - - PCM1_SYNC -

PIO[5] SPI_CLK - - PCM1_CLK -

CSR8640 BGA Data Sheet

PIO[10] - QSPI_FLASH_CLK - - I2C_SCL

PIO[11] - QSPI_IO[0] - - I2C_SDA

PIO[12] - QSPI_FLASH_CS# - - I2C_WP

PIO[13] - QSPI_IO[1] - - -

PIO[14] - - UART_RX - -

PIO[15] - - UART_TX - -

PIO[16] - - UART_RTS - -

PIO[17] - - UART_CTS - -

Table 8.1: Alternative PIO Functions

Note:

See the relevant software release note for the implementation of these PIO lines, as they are firmware build-
specific.

8.2 Analogue I/O Ports, AIO

CSR8640 BGA has 1 general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for
battery pack temperature measurements during charge control. See Section 12 for typical connections.

8.3 LED Drivers

CSR8640 BGA includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide range
of colours. All LEDs are controlled by firmware.
The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series
with a current-limiting resistor.

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 LED Supply

LED Forward Voltage, VF

ILED
RLED Resistor Voltage Drop, VR
LED[2, 1 or 0]

G-TW-0005534.2.2
Pad Voltage, VPAD; RON = 20Ω

Figure 8.1: LED Equivalent Circuit

CSR8640 BGA Data Sheet

From Figure 8.1 it is possible to derive Equation 8.1 to calculate ILED. If a known value of current is required through
the LED to give a specific luminous intensity, then the value of RLED is calculated.
VDD − V
F
ILED =
R +R
LED ON

Equation 8.1: LED Current

For the LED pads to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop
across it, VR, keeps VPAD below 0.5V. Equation 8.2 also applies.

VDD = VF + VR + VPAD

Equation 8.2: LED PAD Voltage

Note:

The LED current adds to the overall current. Conservative LED selection extends battery life.

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9 Audio Interface
The audio interface circuit consists of:
■ Stereo/dual-mono audio codec
■ Dual analogue audio inputs
■ Dual analogue audio outputs
■ 3 digital MEMS microphone inputs
■ Configurable PCM (PCM1) and I²S interfaces
Figure 9.1 shows the functional blocks of the interface. The codec supports stereo/dual-mono playback and recording
of audio signals at multiple sample rates with a 16-bit resolution. The ADC and the DAC of the codec each contain
2 independent high-quality channels. Any ADC or DAC channel runs at its own independent sample rate.

Stereo / Dual-mono Codec

PCM1 PCM1 Interface

Digital
MMU Voice Port Voice Port Audio
Memory

CSR8640 BGA Data Sheet

Management
Unit Digital 2 x Digital
MICs MICs

G-TW-0007451.4.3
2 x Differential
Stereo DAC Outputs
Audio
Codec 2 x Differential
Register Interface Registers Driver ADC Inputs

Figure 9.1: Audio Interface

The interface for the digital audio bus shares the same pins as the PCM1 codec interface described in Section
9.3. Table 9.1 lists the alternative functions.
Important Note:

The term PCM in Section 9.3 and its subsections refers to the PCM1 interface.

PCM Interface I²S Interface

PCM_OUT SD_OUT

PCM_IN SD_IN

PCM_SYNC WS

PCM_CLK SCK

Table 9.1: Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface

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9.1 Audio Input and Output
The audio input circuitry consists of:
■ 2 independent 16-bit high-quality ADC channels:
■ Programmable as either microphone or line input
■ Programmable as either stereo or dual-mono inputs
■ Multiplexed with 1 of the digital microphone inputs, see Figure 9.2 and Section 9.2.14
■ Each channel is independently configurable to be either single-ended or fully differential
■ Each channel has an analogue and digital programmable gain stage for optimisation of different
microphones
■ 2 digital microphone inputs (MEMS)
The audio output circuitry consists of a dual differential class A-B output stage.

9.2 Audio Codec Interface

The main features of the interface are:
■ Stereo and mono analogue input for voice band and audio band
■ Stereo and mono analogue output for voice band and audio band
■ Support for I²S stereo digital audio bus standard

CSR8640 BGA Data Sheet

■ Support for PCM interface including PCM master codecs that require an external system clock
Important Note:

To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right
channel for audio output. With respect to audio input, software and any registers, channel 0 or channel A
represents the left channel and channel 1 or channel B represents the right channel.

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9.2.1 Audio Codec Block Diagram
Stereo Audio, Voice Band and Digital Microphone Input Digital Circuitry
Note:
L/R pins on digital microphones
pulled up or down on the PCB

PIO[EVEN] Clock
Digital MIC Interface Digital Mic Digital Codec 16 Input C
PIO[ODD] Data

MIC_BP
High-quality ADC Digital Codec 16 Input B
MIC_BN

MIC_AP
High-quality ADC
MIC_AN

Mux
Digital Codec 16 Input A
PIO[EVEN] Clock
Digital MIC Interface Digital Mic
PIO[ODD] Data

CSR8640 BGA Data Sheet

Stereo Audio and Voice Band Output

G-TW-0007452.3.2
SPKR_LN
High-quality DAC 16
SPKR_LP
Low-pass Filter
SPKR_RN
High-quality DAC 16
SPKR_RP
Low-pass Filter

Figure 9.2: Audio Codec Input and Output Stages

The CSR8640 BGA audio codec uses a fully differential architecture in the analogue signal path, which results in
low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from
a dual power supply, VDD_AUDIO for the audio circuits and VDD_AUDIO_DRV for the audio driver circuits.

9.2.2 ADC
Figure 9.2 shows the CSR8640 BGA consists of 2 high-quality ADCs:
■ Each ADC has a second-order Sigma-Delta converter.
■ Each ADC is a separate channel with identical functionality.
■ There are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital
gain stage, see Section 9.2.4.

9.2.3 ADC Sample Rate Selection

Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz:
■ 8kHz
■ 11.025kHz
■ 16kHz
■ 22.050kHz
■ 24kHz
■ 32kHz
■ 44.1kHz
■ 48kHz

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9.2.4 ADC Audio Input Gain
Figure 9.3 shows that the CSR8640 BGA audio input gain consists of:
■ An analogue gain stage based on a pre-amplifier and an analogue gain amplifier, see Section 9.2.5
■ A digital gain stage, see Section 9.2.6

ADC Pre-amplifier ADC Digital Gain:

and ADC Analogue Gain: -24dB to 21.5dB in alternating
-3dB to 42dB in 3dB steps 2.5dB and 3dB steps

ADC Pre-amplifier: ADC Analogue Gain:

0dB, 9dB, 21dB and 30dB -3dB to 12dB in 3dB steps

Audio Input To Digital Codec

G-TW-0005535.4.3
System Gain = ADC Pre-amplifier + ADC Analogue Gain + ADC Digital Gain

CSR8640 BGA Data Sheet

Figure 9.3: Audio Input Gain

9.2.5 ADC Pre-amplifier and ADC Analogue Gain

CSR8640 BGA has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:
■ The ADC pre-amplifier has 4 gain settings: 0dB, 9dB, 21dB and 30dB
■ The ADC analogue amplifier gain is -3dB to 12dB in 3dB steps
■ The overall analogue gain for the pre-amplifier and analogue amplifier is -3dB to 42dB in 3dB steps, see
Figure 9.3
■ At mid to high gain levels it acts as a microphone pre-amplifier, see Section 9.2.13
■ At low gain levels it acts as an audio line level amplifier

9.2.6 ADC Digital Gain

A digital gain stage inside the ADC varies from -24dB to 21.5dB, see Table 9.2. There is also a fine gain interface
with a 9-bit gain setting allowing gain changes in 1/32 steps, for more infomation contact CSR.
The firmware controls the audio input gain.

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 Digital Gain Selection ADC Digital Gain Setting Digital Gain Selection ADC Digital Gain Setting
Value (dB) Value (dB)

0 0 8 -24

1 3.5 9 -20.5

2 6 10 -18

3 9.5 11 -14.5

4 12 12 -12

5 15.5 13 -8.5

6 18 14 -6

7 21.5 15 -2.5

CSR8640 BGA Data Sheet

Table 9.2: ADC Audio Input Gain Rate

9.2.7 ADC Digital IIR Filter

The ADC contains 2 integrated anti-aliasing filters:
■ A long IIR filter suitable for music (>44.1kHz)
■ G.722 filter is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance
(which is the best selection for 8kHz / 16kHz / voice)
For more information contact CSR.

9.2.8 DAC
The DAC consists of:
■ 2 fourth-order Sigma-Delta converters enabling 2 separate channels that are identical in functionality, as
Figure 9.2 shows.
■ 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.

9.2.9 DAC Sample Rate Selection

Each DAC supports the following sample rates:
■ 8kHz
■ 11.025kHz
■ 16kHz
■ 22.050kHz
■ 32kHz
■ 40kHz
■ 44.1kHz
■ 48kHz
■ 96kHz

9.2.10 DAC Digital Gain

A digital gain stage inside the DAC varies from -24dB to 21.5dB, see Table 9.3. There is also a fine gain interface
with a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR.

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The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and
analogue amplifier settings.

Digital Gain Selection DAC Digital Gain Setting Digital Gain Selection DAC Digital Gain Setting
Value (dB) Value (dB)

0 0 8 -24

1 3.5 9 -20.5

2 6 10 -18

3 9.5 11 -14.5

4 12 12 -12

5 15.5 13 -8.5

6 18 14 -6

CSR8640 BGA Data Sheet

7 21.5 15 -2.5

Table 9.3: DAC Digital Gain Rate Selection

9.2.11 DAC Analogue Gain

Table 9.4 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB steps.
The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue
amplifier settings.

Analogue Gain Selection DAC Analogue Gain Analogue Gain Selection DAC Analogue Gain
Value Setting (dB) Value Setting (dB)

7 3 3 -9

6 0 2 -12

5 -3 1 -15

4 -6 0 -18

Table 9.4: DAC Analogue Gain Rate Selection

9.2.12 DAC Digital FIR Filter

The DAC contains an integrated digital FIR filter with the following modes:
■ A default long FIR filter for best performance at ≥ 44.1kHz.
■ A short FIR to reduce latency.
■ A narrow FIR (a very sharp roll-off at Nyquist) for G.722 compliance. Best for 8kHz / 16kHz.

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9.2.13 Microphone Input
CSR8640 BGA contains an independent low-noise microphone bias generator. The microphone bias generator is
recommended for biasing electret condensor microphones. Figure 9.4 shows a biasing circuit for microphones with
a sensitivity between about ‑40 to ‑60dB (0dB = 1V/Pa).
Where:
■ The microphone bias generator derives its power from VBAT or 3V3_USB and requires no capacitor on its
output.
■ The microphone bias generator maintains regulation within the limits 70μA to 2.8mA, supporting a 2mA
source typically required by 2 electret condensor microphones. If the microphone sits below these limits,
then the microphone output must be pre-loaded with a large value resistor to ground.
■ Biasing resistors R1 and R24 equal 2.2kΩ.
■ The input impedance at MIC_AN, MIC_AP, MIC_BN and MIC_BP is typically 6kΩ.
■ C1, C2, C3 and C4 are 100/150nF if bass roll-off is required to limit wind noise on the microphone.
■ R1 and R2 set the microphone load impedance and are normally around 2.2kΩ.

Microphone Bias
(MIC_BIAS)

C1

CSR8640 BGA Data Sheet

MIC_AP

Input
R1
C2 Amplifier
MIC_AN

+ MIC1

Microphone Bias
(MIC_BIAS)

C3 MIC_BP

G-TW-0008073.2.2
Input
R2
C4 Amplifier
MIC_BN

+ MIC2

Figure 9.4: Microphone Biasing

The microphone bias characteristics include:
■ Power supply:
■ CSR8640 BGA microphone supply is VBAT or 3V3_USB
■ Minimum input voltage = Output voltage + drop-out voltage
■ Maximum input voltage is 4.3V
■ Drop-out voltage:
■ 300mV maximum
■ Output voltage:
■ 1.8V or 2.6V
■ Tolerance 90% to 110%
■ Output current:
■ 70μA to 2.8mA
■ No load capacitor required

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9.2.14 Digital Microphone Inputs
The CSR8640 BGA interfaces to 2 digital microphone inputs (MEMS). Figure 9.2 shows that 1 of the inputs has a
dedicated codec channel and 1 is multiplexed with a high-quality ADC channel.
Figure 9.2 shows that the digital microphone interface on the CSR8640 BGA has:
■ Clock lines linked to any even-numbered PIO as determined by the firmware.
■ Data lines linked to any odd-numbered PIO as determined by the firmware.
Note:

For the digital microphone interface to work in this configuration ensure the microphone uses a tristate
between edges.
■ The left and right selection for the digital microphones are appropriately pulled up or down for selection on
the PCB.

9.2.15 Line Input

Section 9.2.4 states that if the pre-amplifier audio input gain is set at a low gain level it acts as an audio line level
amplifier. In this line input mode the input impedance varies from 6kΩ to 30kΩ, depending on the volume setting.
Figure 9.5 and Figure 9.6 show 2 circuits for line input operation and show connections for either differential or single-
ended inputs.

CSR8640 BGA Data Sheet

C1
MIC_AN

C2
MIC_AP
C3
MIC_BN

G-TW-0008474.1.2
C4
MIC_BP

Figure 9.5: Differential Input

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 C1
MIC_AP

C2
MIC_AN

C3
MIC_AP

G-TW-0008476.1.1
C4
MIC_AN

Figure 9.6: Single-ended Input

9.2.16 Output Stage

CSR8640 BGA Data Sheet

The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling
frequency to bit stream, which is fed into the analogue output circuitry.
The analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB output
stage amplifier. Figure 9.7 shows that the output is available as a differential signal between SPKR_LN and SPKR_LP
for the left channel, and between SPKR_RN and SPKR_RP for the right channel.

SPKR_LP

SPKR_LN
SPKR_RP
G-TW-0005537.1.1

SPKR_RN

Figure 9.7: Speaker Output

9.2.17 Mono Operation

Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono
channel for audio in and audio out. In mono operation, the right channel is the auxiliary mono channel for dual-mono
channel operation.
In single channel mono operation, disable the other channel to reduce power consumption.

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9.2.18 Side Tone
In some applications it is necessary to implement side tone. This side tone function involves feeding a properly
gained microphone signal in to the DAC stream, e.g. earpiece. The side tone routing selects the version of the
microphone signal from before or after the digital gain in the ADC interface and adds it to the output signal before
or after the digital gain of the DAC interface, see Figure 9.8.

DAC

DAC Interface

Digital Input Digital Gain Analogue Output

Side Tone Route Demux

Side Tone

Side Tone Gain

CSR8640 BGA Data Sheet

Side Tone Route Mux

G-TW-0005375.1.1
Digital Output Digital Gain Analogue Input

ADC Interface

ADC

Figure 9.8: Side Tone

The ADC provides simple gain to the side tone data. The gain values range from -32.6dB to 12.0dB in alternating
steps of 2.5dB and 3.5dB, see Table 9.5.

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 Value Sidetone Gain Value Sidetone Gain

0 -32.6dB 8 -8.5dB

1 -30.1dB 9 -6.0dB

2 -26.6dB 10 -2.5dB

3 -24.1dB 11 0dB

4 -20.6dB 12 3.5dB

5 -18.1dB 13 6.0dB

6 -14.5dB 14 9.5dB

7 -12.0dB 15 12.0dB

Table 9.5: Sidetone Gain

CSR8640 BGA Data Sheet

Note:

The values of side tone are shown for information only. During standard operation, the application software
controls the sidetone gain.
The following PS Keys configure the side tone hardware:
■ PSKEY_SIDE_TONE_ENABLE
■ PSKEY_SIDE_TONE_GAIN
■ PSKEY_SIDE_TONE_AFTER_ADC
■ PSKEY_SIDE_TONE_AFTER_DAC

9.2.19 Integrated Digital IIR Filter

CSR8640 BGA has a programmable digital filter integrated into the ADC channel of the codec. The filter is a 2-stage,
second order IIR and is for functions such as custom wind noise reduction. The filter also has optional DC blocking.
The filter has 10 configuration words:
■ 1 for gain value
■ 8 for coefficient values
■ 1 for enabling and disabling the DC blocking
The gain and coefficients are all 12-bit 2's complement signed integer with the format NN.NNNNNNNNNN.

Note:

The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.

Advance Information Page 46 of 110

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For example:

01.1111111111 = most positive number, close to 2

01.0000000000 = 1
00.0000000000 = 0
11.0000000000 = -1
10.0000000000 = -2, most negative number

Equation 9.1 shows the equation for the IIR filter. Equation 9.2 shows the equation for when the DC blocking is
enabled.
The filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and
CodecSetIIRFilterB traps. This requires firmware support. The configuration function takes 10 variables in the
following order:

0 : Gain
1 : b01
2 : b02

CSR8640 BGA Data Sheet

3 : a01
4 :
a02
5 :
b11
6 :
7 : b12
8 : a11
9 : a12
DC Block (1 = enable, 0 = disable)

(1 +b −1 −2 ) (1 +b −1 −2 )
01 z + b02 z 11 z + b12 z
Filter, H(z) = Gain × ×
(1 +a −1 −2 ) (1 +a −1 −2 )
z +a z z +a z
01 02 11 12

Equation 9.1: IIR Filter Transfer Function, H(z)

Filter with DC Blocking, HDC (z) = H(z) × ( 1 − z−1 )

Equation 9.2: IIR Filter Plus DC Blocking Transfer Function, HDC(z)

9.3 PCM1 Interface

There are 2 digital audio interfaces. Each is independently configurable as an I²S, PCM or SPDIF port. The PCM1
interface also shares the same physical set of pins with the SPI interface, see Section 7.3 and Section 8.1. Either
interface is selected using SPI_PCM#:
■ SPI_PCM# = 1 selects SPI
■ SPI_PCM# = 0 selects PCM
Important Note:

The term PCM refers to PCM1.

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The audio PCM interface on the CSR8640 BGA supports:
■ Continuous transmission and reception of PCM encoded audio data over Bluetooth.
■ Processor overhead reduction through hardware support for continual transmission and reception of
PCM data.
■ A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does not
pass through the HCI protocol layer.
■ Hardware on the CSR8640 BGA for sending data to and from a SCO connection.
■ Up to 3 SCO connections on the PCM interface at any one time.
■ PCM interface master, generating PCM_SYNC and PCM_CLK.
■ PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.
■ Various clock formats including:
■ Long Frame Sync
■ Short Frame Sync
■ GCI timing environments
■ 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats.
■ Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC.
The PCM configuration options are enabled by setting the PSKEY_PCM_CONFIG32.

9.3.1 PCM Interface Master/Slave

CSR8640 BGA Data Sheet

When configured as the master of the PCM interface, CSR8640 BGA generates PCM_CLK and PCM_SYNC.

PCM_OUT

PCM_IN

PCM_CLK 128/256/512/1536/2400kHz

G-TW-0000217.3.4
PCM_SYNC 8/48kHz

Figure 9.9: PCM Interface Master

PCM_OUT

PCM_IN

PCM_CLK Up to 2400kHz
G-TW-0000218.3.3

PCM_SYNC 8/48kHz

Figure 9.10: PCM Interface Slave

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9.3.2 Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples.
In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When CSR8640 BGA is
configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8 bits long. When
CSR8640 BGA is configured as PCM Slave, PCM_SYNC is from 1 cycle PCM_CLK to half the PCM_SYNC rate.

PCM_SYNC

PCM_CLK

G-TW-0000219.2.2
PCM_OUT 1 2 3 4 5 6 7 8

PCM_IN Undefined 1 2 3 4 5 6 7 8 Undefined

CSR8640 BGA Data Sheet

Figure 9.11: Long Frame Sync (Shown with 8-bit Companded Sample)
CSR8640 BGA samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge.
PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising
edge.

9.3.3 Short Frame Sync

In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always 1
clock cycle long.

PCM_SYNC

PCM_CLK

G-TW-0000220.2.3

PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined

Figure 9.12: Short Frame Sync (Shown with 16-bit Sample)

As with Long Frame Sync, CSR8640 BGA samples PCM_IN on the falling edge of PCM_CLK and transmits
PCM_OUT on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the
LSB position or on the rising edge.

9.3.4 Multi-slot Operation

More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO connections
are carried over any of the first 4 slots.

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 LONG_PCM_SYNC

Or

SHORT_PCM_SYNC

PCM_CLK

G-TW-0000221.3.2
PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

PCM_IN Do Not Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not Care

Figure 9.13: Multi-slot Operation with 2 Slots and 8-bit Companded Samples

9.3.5 GCI Interface

CSR8640 BGA is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The 2 64kbps B

CSR8640 BGA Data Sheet

channels are accessed when this mode is configured.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

G-TW-0000222.2.3
Do Not Do Not
PCM_IN Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Care

B1 Channel B2 Channel

Figure 9.14: GCI Interface

The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.

9.3.6 Slots and Sample Formats

CSR8640 BGA receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations
are either 8 or 16 clock cycles:
■ 8 clock cycles for 8-bit sample formats.
■ 16 clock cycles for 8-bit, 13-bit or 16-bit sample formats.
CSR8640 BGA supports:
■ 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
■ A sample rate of 8ksps.
■ Little or big endian bit order.
■ For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a
programmable 3-bit audio attenuation compatible with some codecs.

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 Sign
Extension
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
8-bit
Sample
A 16-bit slot with 8-bit companded sample and sign extension selected.

8-bit
Sample
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Zeros
Padding
A 16-bit slot with 8-bit companded sample and zeros padding selected.

Sign
Extension
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CSR8640 BGA Data Sheet

13-bit
Sample
A 16-bit slot with 13-bit linear sample and sign extension selected.

13-bit

G-TW-0000223.2.3
Sample
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Audio
Gain
A 16-bit slot with 13-bit linear sample and audio gain selected.

Figure 9.15: 16-bit Slot Length and Sample Formats

9.3.7 Additional Features

CSR8640 BGA has a mute facility that forces PCM_OUT to be 0. In master mode, CSR8640 BGA is compatible with
some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running.

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9.3.8 PCM Timing Information

Symbol Parameter Min Typ Max Unit

128
4MHz DDS generation.
Selection of frequency
- 256 - kHz
is programmable. See
Section 9.3.10.
512
fmclk PCM_CLK frequency
48MHz DDS
generation. Selection
of frequency is 2.9 - - kHz
programmable. See
Section 9.3.10.

- PCM_SYNC frequency for SCO connection - 8 - kHz

tmclkh (a) PCM_CLK high 4MHz DDS generation 980 - - ns

CSR8640 BGA Data Sheet

tmclkl (a) PCM_CLK low 4MHz DDS generation 730 - - ns

48MHz DDS
- PCM_CLK jitter - - 21 ns pk-pk
generation

Delay time from PCM_CLK high to PCM_SYNC

tdmclksynch - - 20 ns
high

Delay time from PCM_CLK high to valid

tdmclkpout - - 20 ns
PCM_OUT

Delay time from PCM_CLK low to PCM_SYNC

tdmclklsyncl - - 20 ns
low (Long Frame Sync only)

Delay time from PCM_CLK high to PCM_SYNC

tdmclkhsyncl - - 20 ns
low

Delay time from PCM_CLK low to PCM_OUT

tdmclklpoutz - - 20 ns
high impedance

Delay time from PCM_CLK high to PCM_OUT

tdmclkhpoutz - - 20 ns
high impedance

tsupinclkl Set-up time for PCM_IN valid to PCM_CLK low 20 - - ns

thpinclkl Hold time for PCM_CLK low to PCM_IN invalid 0 - - ns

Table 9.6: PCM Master Timing

(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.

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 t dmclklsyncl

t dmclksynch t dmclkhsyncl

PCM_SYNC

f mlk

t mclkh t mclkl

PCM_CLK

t dmclklpoutz

t dmclkpout tr ,t f t dmclkhpoutz

PCM_OUT MSB (LSB) LSB (MSB)

G-TW-0000224.2.3

CSR8640 BGA Data Sheet

t supinclkl t hpinclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 9.16: PCM Master Timing Long Frame Sync

t dmclksynch t dmclkhsyncl

PCM_SYNC

f mlk

t mclkh t mclkl

PCM_CLK

t dmclklpoutz

t dmclkpout tr ,t f t dmclkhpoutz

PCM_OUT MSB (LSB) LSB (MSB)

G-TW-0000225.3.3

t supinclkl t hpinclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 9.17: PCM Master Timing Short Frame Sync

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Symbol Parameter Min Typ Max Unit

fsclk PCM clock frequency (Slave mode: input) 64 - (a) kHz

fsclk PCM clock frequency (GCI mode) 128 - (b) kHz

tsclkl PCM_CLK low time 200 - - ns

tsclkh PCM_CLK high time 200 - - ns

thsclksynch Hold time from PCM_CLK low to PCM_SYNC high 2 - - ns

tsusclksynch Set-up time for PCM_SYNC high to PCM_CLK low 20 - - ns

Delay time from PCM_SYNC or PCM_CLK,

tdpout whichever is later, to valid PCM_OUT data (Long - - 20 ns
Frame Sync only)

CSR8640 BGA Data Sheet

tdsclkhpout Delay time from CLK high to PCM_OUT valid data - - 15 ns

Delay time from PCM_SYNC or PCM_CLK low,

tdpoutz whichever is later, to PCM_OUT data line high - - 15 ns
impedance

tsupinsclkl Set-up time for PCM_IN valid to CLK low 20 - - ns

thpinsclkl Hold time for PCM_CLK low to PCM_IN invalid 2 - - ns

Table 9.7: PCM Slave Timing

(a) Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
(b) Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK

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 f sclk

t sclkh t tsclkl

PCM_CLK

t hsclksynch t susclksynch

PCM_SYNC

t dpoutz

t dpout t dsclkhpout tr ,t f t dpoutz

PCM_OUT MSB (LSB) LSB (MSB)

G-TW-0000226.3.2
t supinsclkl t hpinsclkl

CSR8640 BGA Data Sheet

PCM_IN MSB (LSB) LSB (MSB)

Figure 9.18: PCM Slave Timing Long Frame Sync

f sclk

t sclkh t tsclkl

PCM_CLK

t susclksynch t hsclksynch

PCM_SYNC

t dpoutz
t dpoutz
t dsclkhpout tr ,t f

PCM_OUT MSB (LSB) LSB (MSB)

G-TW-0000227.3.2

t supinsclkl t hpinsclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 9.19: PCM Slave Timing Short Frame Sync

9.3.9 PCM_CLK and PCM_SYNC Generation

CSR8640 BGA has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:

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 ■ Generating these signals by DDS from CSR8640 BGA internal 4MHz clock. Using this mode limits
PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
■ Generating these signals by DDS from an internal 48MHz clock (which enables a greater range of
frequencies to be generated with low jitter but consumes more power). To select this second method set
bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync,
the length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN
in PSKEY_PCM_CONFIG32.
Equation 9.3 describes PCM_CLK frequency when generated from the internal 48MHz clock:
CNT_RATE
f = × 24MHz
CNT_LIMIT

Equation 9.3: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 9.4:
PCM_CLK
f =
SYNC_LIMIT × 8

Equation 9.4: PCM_SYNC Frequency Relative to PCM_CLK

CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_USE_LOW_JITTER_MODE.

9.3.10 PCM Configuration

CSR8640 BGA Data Sheet

Configure the PCM by using PSKEY_PCM_CONFIG32 and PSKEY_PCM_USE_LOW_JITTER_MODE, see your
PS Key file. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e. first slot following sync is active, 13-bit
linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock
with no tristate of PCM_OUT.

9.4 Digital Audio Interface (I²S)

The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface
shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table
9.8 lists these alternative functions. Figure 9.20 shows the timing diagram.

PCM Interface I²S Interface

PCM_OUT SD_OUT

PCM_IN SD_IN

PCM_SYNC WS

PCM_CLK SCK

Table 9.8: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
Configure the digital audio interface using PSKEY_DIGITAL_AUDIO_CONFIG, see the PS Key file.

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 WS Left Channel Right Channel

SCK

SD_IN/OUT MSB LSB MSB LSB

Left -justified Mode

WS Left Channel Right Channel

SCK

SD_IN/OUT MSB LSB MSB LSB

CSR8640 BGA Data Sheet

Right -justified Mode

WS Left Channel Right Channel

SCK

G-TW-0000230.3.2
SD_IN/OUT MSB LSB MSB LSB
I2 S Mode

Figure 9.20: Digital Audio Interface Modes

The internal representation of audio samples within CSR8640 BGA is 16-bit and data on SD_OUT is limited to 16-
bit per channel.

Symbol Parameter Min Typ Max Unit

- SCK Frequency - - 6.2 MHz

- WS Frequency - - 96 kHz

tch SCK high time 80 - - ns

tcl SCK low time 80 - - ns

Table 9.9: Digital Audio Interface Slave Timing

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 Symbol Parameter Min Typ Max Unit

WS valid to SCK high set-up

tssu 20 - - ns
time

SCK high to WS invalid hold

tsh 2.5 - - ns
time

SCK low to SD_OUT valid delay

topd - - 20 ns
time

SD_IN valid to SCK high set-up

tisu 20 - - ns
time

SCK high to SD_IN invalid hold

tih 2.5 - - ns
time

Table 9.10: I²S Slave Mode Timing

CSR8640 BGA Data Sheet

WS(Input)

t ssu t sh

t ch t cl

SCK(Input)

topd

SD_OUT

t isu t ih G-TW-0000231.2.2

SD_IN

Figure 9.21: Digital Audio Interface Slave Timing

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 Symbol Parameter Min Typ Max Unit

- SCK Frequency - - 6.2 MHz

- WS Frequency - - 96 kHz

Table 9.11: Digital Audio Interface Master Timing

Symbol Parameter Min Typ Max Unit

tspd SCK low to WS valid delay time - - 39.27 ns

SCK low to SD_OUT valid delay

topd - - 18.44 ns
time

SD_IN valid to SCK high set-up

tisu 18.44 - - ns
time

CSR8640 BGA Data Sheet

SCK high to SD_IN invalid hold
tih 0 - - ns
time

Table 9.12: I²S Master Mode Timing Parameters, WS and SCK as Outputs

WS(Output)

t spd

SCK(Output)

t opd

SD_OUT
G-TW-0000232.2.2

t isu t ih

SD_IN

Figure 9.22: Digital Audio Interface Master Timing

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10 Power Control and Regulation
For greater power efficiency the CSR8640 BGA contains 2 switch-mode regulators:
■ 1 generates a 1.80V supply rail with an output current of 185mA, see Section 10.1.
■ 1 generates a 1.35V supply rail with an output current of 160mA, see Section 10.2.
■ Combining the 2 switch-mode regulators in parallel generates a single 1.80V supply rail with an output
current of 340mA, see Section 10.3.
CSR8640 BGA contains 4 LDO linear regulators:
■ 3.30V bypass regulator, see Section 10.4.
■ 0.80V to 1.25V VDD_DIG linear regulator, see Section 10.5.
■ 1.35V VDD_AUX linear regulator, see Section 10.6.
■ 1.35V VDD_ANA linear regulator, see Section 10.7.
The recommended configurations for power control and regulation on the CSR8640 BGA are:
■ 3 switch-mode configurations:
■ A 1.80V and 1.35V dual-supply rail system using the 1.80V and 1.35V switch-mode regulators, see
Figure 10.1. This is the default power control and regulation configuration for the CSR8640 BGA.
■ A 1.80V single-supply rail system using the 1.80V switch-mode regulator.
■ A 1.80V parallel-supply rail system for higher currents using the 1.80V and 1.35V switch-mode

CSR8640 BGA Data Sheet

regulators with combined outputs, see Figure 10.2.
■ A linear configuration using an external 1.8V rail omitting all regulators
Table 10.1 shows settings for the recommended configurations for power control and regulation on the
CSR8640 BGA.

Regulators
Supply Rail
Supply
Switch-mode VDD_AUX VDD_ANA
Configuration
Linear Linear
1.8V 1.35V Regulator Regulator 1.8V 1.35V

Dual-supply
ON ON OFF OFF SMPS SMPS
SMPS

Single-supply
ON OFF ON ON SMPS LDO
SMPS

Parallel-
ON ON ON ON SMPS LDO
supply SMPS

Linear supply OFF OFF ON ON External LDO

Table 10.1: Recommended Configurations for Power Control and Regulation

For more information on CSR8640 BGA power supply configuration see the Configuring the Power Supplies on
CSR8670 application note.

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 VCHG 1.8V 1.35V 3.3V

EN
VBAT_SENSE Charger Charge Bypass Linear
OUT
50 to 200mA Reference Regulator 3V3_USB
SENSE
VBAT

IN 1.35V OUT
Switch-mode LX_1V35
Regulator
EN SENSE
SMPS_1V35_SENSE
Reference

IN 1.8V OUT

Switch-mode LX_1V8
Regulator
EN SENSE
SMPS_1V8_SENSE

VREGENABLE Analogue and Auxiliary

IN

CSR8640 BGA Data Sheet

VDD_AUX OUT VDD_AUX_1V8
Regulator VDD_AUX
EN SENSE

Auxiliary Circuits

IN
VDD_ANA OUT
Regulator VDD_ANA_RADIO
EN SENSE

Bluetooth
VDD_BT_LO

VDD_PADS_1
I/O
VDD_PADS_2
VDD_PADS_3

Audio Circuits

Mic Bias
MIC_BIAS

Audio Driver
VDD_AUDIO_DRV

Audio Core
VDD_AUDIO

Digital Core Circuits

EN IN
G-TW-0008074.3.2

VDD_DIG VREGIN_DIG
OUT
Regulator VDD_DIG_MEM
SENSE

Figure 10.1: 1.80V and 1.35V Dual-supply Switch-mode System Configuration

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 VCHG 1.8V 1.35V 3.3V

EN
VBAT_SENSE Charger Charge Bypass Linear
50 to 200mA Reference Regulator OUT
3V3_USB
SENSE
VBAT

IN SENSE
1.35V SMPS_1V35_SENSE
Switch-mode
EN
Regulator OUT
LX_1V35
Reference

IN 1.8V OUT

Switch-mode LX_1V8
Regulator
EN SENSE
SMPS_1V8_SENSE

VREGENABLE Analogue and Auxiliary

CSR8640 BGA Data Sheet

IN
VDD_AUX OUT VDD_AUX_1V8
Regulator VDD_AUX
EN SENSE

Auxiliary Circuits

IN
VDD_ANA
OUT
Regulator VDD_ANA_RADIO
EN SENSE

Bluetooth
VDD_BT_LO

VDD_PADS_1
I/O
VDD_PADS_2
VDD_PADS_3

Audio Circuits

Mic Bias
MIC_BIAS

Audio Driver
VDD_AUDIO_DRV

Audio Core
VDD_AUDIO

Digital Core Circuits

EN IN
G-TW-0008075.3.2

VDD_DIG VREGIN_DIG
OUT
Regulator VDD_DIG_MEM
SENSE

Figure 10.2: 1.80V Parallel-supply Switch-mode System Configuration

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10.1 1.8V Switch-mode Regulator
CSR recommends the integrated switch-mode regulator to power the 1.80V supply rail.
Figure 10.3 shows that an external LC filter circuit of a low-resistance series inductor, L1 (4.7µH), followed by a low
ESR shunt capacitor, C3 (2.2µF), are required between the LX_1V8 terminal and the 1.80V supply rail. A connection
between the 1.80V supply rail and the VDD_AUX_1V8 pin is required.

L1
4.7µH
VBAT LX_1V8 1.8V Supply Rail
LX

G-TW-0008945.1.2
1.8V Switch-mode
3V3_USB Regulator SMPS_1V8_SENSE C3
SENSE 2.2µF
C1 C2 VSS_SMPS_1V8
2.2µF 2.2µF
To 1.35V Switch-mode
Regulator Input

Figure 10.3: 1.8V Switch-mode Regulator Output Configuration

CSR8640 BGA Data Sheet

Ensure the series resistance of the tracks is minimised between the regulator input, VBAT and 3V3_USB, ground
terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power
conversion and low supply ripple.
Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V8.
Also minimise the collective parasitic capacitance on the track between LX_1V8 and the inductor L1, to maximise
efficiency.
For the regulator to meet the specifications in Section 13.3.1.1 requires a total resistance of <1.0Ω (<0.5Ω
recommended) for the following:
■ The track between the battery and VBAT.
■ The track between LX_1V8 and the inductor.
■ The inductor, L1, ESR.
■ The track between the inductor, L1, and the sense point on the 1.80V supply rail.
The following enable the 1.80V switch-mode regulator:
■ VREGENABLE pin
■ The CSR8640 BGA firmware with reference to PSKEY_PSU_ENABLES
■ VCHG pin
The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET,
which also affects the 1.35V switch-mode regulator.

When the 1.80V switch-mode regulator is not required, leave unconnected:

■ The regulator input VBAT and 3V3_USB
■ The regulator output LX_1V8

10.2 1.35V Switch-mode Regulator

CSR recommends the integrated switch-mode regulator to power the 1.35V supply rail.
Figure 10.4 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7µH), followed by a low
ESR shunt capacitor, C3 (4.7µF), are required between the LX_1V35 terminal and the 1.35V supply rail. A connection
between the 1.35V supply rail and the SMPS_1V35_SENSE pin is required.

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 L1
4.7µH
VBAT LX_1V35 1.35V Supply Rail
LX

G-TW-0008946.1.2
1.35V Switch-
3V3_USB mode Regulator SMPS_1V35_SENSE C3
SENSE 4.7µF
C1 C2 VSS_SMPS_1V35
2.2µF 2.2µF
To 1.8V Switch-mode
Regulator Input

Figure 10.4: 1.35V Switch-mode Regulator Output Configuration

Ensure the series resistance of the tracks is minimised between the regulator input, VBAT and 3V3_USB, ground
terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power
conversion and low supply ripple.
Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V35.
Also minimise the collective parasitic capacitance on the track between LX_1V35 and the inductor L1, to maximise
efficiency.

CSR8640 BGA Data Sheet

For the regulator to meet the specifications in Section 13.3.2.1 requires a total resistance of <1.0Ω (<0.5Ω
recommended) for the following:
■ The track between the battery and VBAT.
■ The track between LX_1V8 and the inductor.
■ The inductor, L1, ESR.
■ The track between the inductor, L1, and the sense point on the 1.35V supply rail.
The following enable the 1.35V switch-mode regulator:
■ VREGENABLE pin
■ The CSR8640 BGA firmware with reference to PSKEY_PSU_ENABLES
■ VCHG pin
The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET,
which also affects the 1.80V switch-mode regulator.
When the 1.35V switch-mode regulator is not required, leave unconnected:
■ The regulator input VBAT and 3V3_USB
■ The regulator output LX_1V35

10.3 1.8V and 1.35V Switch-mode Regulators Combined

For applications that require a single 1.80V supply rail with higher currents CSR recommends combining the outputs
of the integrated 1.80V and 1.35V switch-mode regulators in parallel to power a single 1.80V supply rail, see Figure
10.5.
Figure 10.5 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7µH), followed by a low
ESR shunt capacitor, C3 (2.2µF), are required between the LX_1V8 terminal and the 1.80V supply rail. A connection
between the 1.80V supply rail and the VDD_AUX_1V8 pin is required and the SMPS_1V35_SENSE pin is grounded.

Advance Information Page 64 of 110

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 VBAT LX_1V35
LX
1.35V Switch-
3V3_USB mode Regulator SMPS_1V35_SENSE
SENSE
C1 C2 VSS_SMPS_1V35
2.2µF 2.2µF

L1
4.7µH
LX
LX_1V8 1.8V Supply Rail
1.8V Switch-mode

G-TW-0008947.1.2
Regulator SMPS_1V8_SENSE C3
SENSE 2.2µF
VSS_SMPS_1V8

Figure 10.5: 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration

CSR8640 BGA Data Sheet

Ensure the series resistance of the tracks is minimised between the regulator input VBAT and 3V3_USB, ground
terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power
conversion and low supply ripple.
Ensure a solid ground plane between C1, C2, C3, VSS_SMPS_1V8 and VSS_SMPS_1V35.
Also minimise the collective parasitic capacitance on the track between LX_1V8, LX_1V35 and the inductor L1, to
maximise efficiency.
For the regulator to meet the specifications in Section 13.3.1.2 requires a total resistance of <1.0Ω (<0.5Ω
recommended) for the following:
■ The track between the battery and VBAT.
■ The track between LX_1V8, LX_1V35 and the inductor.
■ The inductor L1, ESR.
■ The track between the inductor, L1, and the sense point on the 1.80V supply rail.
The following enable the 1.80V switch-mode regulator:
■ VREGENABLE pin
■ The CSR8640 BGA firmware with reference to PSKEY_PSU_ENABLES
■ VCHG pin
The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET.
When the 1.80V switch-mode regulator is not required, leave unconnected:
■ The regulator input VBAT and 3V3_USB
■ The regulator output LX_1V8

10.4 Bypass LDO Linear Regulator

The integrated bypass LDO linear regulator is available as a 3.30V supply rail and is an alternative supply rail to the
battery supply. This is especially useful when the battery has no charge and the CSR8640 BGA needs to power up.
The input voltage should be between 4.75 / 3.10V and 5.25V.
Note:

The integrated bypass LDO linear regulator can operates down to 3.0V with a reduced performance.

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Externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 2.2µF to the 3V3_USB
pin.
The output voltage is switched on when VCHG gets above 3.0V.

10.5 Low-voltage VDD_DIG Linear Regulator

The integrated low-voltage VDD_DIG linear regulator powers the digital circuits on CSR8640 BGA. Externally
decouple the output of this regulator using a low ESR MLC capacitor of 470nF.

10.6 Low-voltage VDD_AUX Linear Regulator

The integrated low-voltage VDD_AUX linear regulator is optionally available to provide a 1.35V auxiliary supply rail
when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_AUX linear
regulator, externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 470nF to
the VDD_AUX pin.

10.7 Low-voltage VDD_ANA Linear Regulator

The integrated low-voltage VDD_ANA linear regulator is optionally available to power an optional 1.35V analogue
supply rail when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_ANA
linear regulator, externally decouple the output of this regulator using a 2.2µF low ESR MLC capacitor to the

CSR8640 BGA Data Sheet

VDD_ANA pin.

10.8 Voltage Regulator Enable

When using the integrated regulators the voltage regulator enable pin, VREGENABLE, enables the CSR8640 BGA
and the following regulators:
■ 1.8V switch-mode regulator
■ 1.35V switch-mode regulator
■ Low-voltage VDD_DIG linear regulator
■ Low-voltage VDD_AUX linear regulator
The VREGENABLE pin is active high, with a weak pull-down.
CSR8640 BGA boots-up when the voltage regulator enable pin is pulled high, enabling the regulators. The firmware
then latches the regulators on, it is then permitted to release the voltage regulator enable pin.
The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also
works as an input line.

10.9 External Regulators and Power Sequencing

CSR recommends that the integrated regulators supply the CSR8640 BGA and it is configured based on the
information in this data sheet.
If any of the supply rails for the CSR8640 BGA are supplied from an external regulator, then it should match or be
better than the internal regulator available on CSR8640 BGA. For more information see regulator characteristics in
Section 13.
Note:

The internal regulators described in Section 10.1 to Section 10.7 are not recommended for external circuitry
other than that shown in Section 12.
For information about power sequencing of external regulators to supply the CSR8640 BGA contact CSR.

10.10 Reset, RST#

CSR8640 BGA is reset from several sources:

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 ■ RST# pin
■ Power-on reset
■ USB charger attach reset
■ Software configured watchdog timer
The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. CSR
recommends applying RST# for a period >5ms.
At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.

10.10.1 Digital Pin States on Reset

Table 10.2 shows the pin states of CSR8640 BGA on reset.

Pin Name / Group I/O Type Full Chip Reset

USB_DP Digital bidirectional N/A

USB_DN Digital bidirectional N/A

PIO[0] Digital bidirectional PUS

CSR8640 BGA Data Sheet

PIO[1] Digital bidirectional PUS

PIO[2] Digital bidirectional PDW

PIO[3] Digital bidirectional PDW

PIO[4] Digital bidirectional PDW

PIO[5] Digital bidirectional PDW

PIO[6] Digital bidirectional PDS

PIO[7] Digital bidirectional PDS

PIO[8] Digital bidirectional PUS

PIO[9] Digital bidirectional PDS

PIO[10] Digital bidirectional PDS

PIO[11] Digital bidirectional PDS

PIO[12] Digital bidirectional PUS

PIO[13] Digital bidirectional PDS

PIO[14] Digital bidirectional PUS

PIO[15] Digital bidirectional PUS

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 Pin Name / Group I/O Type Full Chip Reset

PIO[16] Digital bidirectional PUS

PIO[17] Digital bidirectional PDS

PIO[18] Digital bidirectional PDW

PIO[19] Digital bidirectional PDW

PIO[20] Digital bidirectional PDW

PIO[21] Digital bidirectional PDW

Table 10.2: Pin States on Reset

Note:

PUS = Strong pull-up

CSR8640 BGA Data Sheet

PDS = Strong pull-down
PUW = Weak pull-up
PDW = Weak pull-down

10.10.2 Status After Reset

The status of CSR8640 BGA after a reset is:
■ Warm reset: baud rate and RAM data remain available
■ Cold reset: baud rate and RAM data not available

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11 Battery Charger
11.1 Battery Charger Hardware Operating Modes
The battery charger hardware is controlled by the VM, see Section 11.3.The battery charger has 5 modes:
■ Disabled
■ Trickle charge
■ Fast charge
■ Standby: fully charged or float charge
■ Error: charging input voltage, VCHG, is too low
The battery charger operating mode is determined by the battery voltage and current, see Table 11.1 and Figure
11.1.
The internal charger circuit can provide up to 200mA of charge current, for currents higher than this the
CSR8640 BGA can control an external pass transistor, see Section 11.5.

Mode Battery Charger Enabled VBAT_SENSE

Disabled No X

CSR8640 BGA Data Sheet

Trickle charge Yes >0 and <Vfast

Fast charge Yes >Vfast and <Vfloat

Standby Yes Iterm (a) and >(Vfloat - Vhyst)

Error Yes >(VCHG - 50mV)

Table 11.1: Battery Charger Operating Modes Determined by Battery Voltage and Current
(a) Iterm is 10% of Ifast for a given Ifast setting

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Figure 11.1 shows the mode-to-mode transition voltages. These voltages are fixed and calibrated by CSR, see
Section 11.2. The transition between modes can occur at any time.
Charge Current

Fast Charge Mode

Constant Current
Ifast

Fast Charge Mode

Constant Voltage

Standby Mode

G-TW-0005583.3.2
Trickle Charge Mode Iterm
Itrickle Vhyst
Battery Voltage

Vfast
Vfloat

CSR8640 BGA Data Sheet

Figure 11.1: Battery Charger Mode-to-Mode Transition Diagram

11.1.1 Disabled Mode

In the disabled mode the battery charger is fully disabled and draws no active current on any of its terminals.

11.1.2 Trickle Charge Mode

In the trickle charge mode, when the voltage on VBAT_SENSE is lower than the Vfast threshold, a current of
approximately 10% of the fast charge current, Ifast, is sourced from the VBAT pin.

The Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes.

11.1.3 Fast Charge Mode

When the voltage on VBAT_SENSE is greater than Vfast, the current sourced from the VBAT pin increases to Ifast.
Ifast is between 10mA and 200mA set by PS Key or a VM trap. In addition, Ifast is calibrated in production test to
correct for process variation in the charger circuit.
The current is held constant at Ifast until the voltage at VBAT_SENSE reaches Vfloat, then the charger reduces the
current sourced to maintain a constant voltage on the VBAT_SENSE pin.
When the current sourced is below the termination current, Iterm, the charging stops and the charger enters standby
mode. Iterm is typically 10% of the fast charge current.

11.1.4 Standby Mode

When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery voltage
on the VBAT_SENSE pin is monitored, and when it drops below a threshold set at Vhyst below the final charging
voltage, Vfloat, the charger re-enters fast charge mode.

11.1.5 Error Mode

The charger enters the error mode if the voltage on the VCHG pin is too low to operate the charger correctly
(VBAT_SENSE is greater than VCHG - 50mV (typical)).

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In this mode, charging is stopped, the battery charger does not require a reset to resume normal operation.

11.2 Battery Charger Trimming and Calibration

The battery charger default trim values are written by CSR into internal ROM when each IC is characterised. CSR
provides various PS Keys for overriding the default trims, see Section 11.4.

11.3 VM Battery Charger Control

The VM charger code has overall supervisory control of the battery charger and is responsible for:
■ Responding to charger power connection/disconnection events
■ Monitoring the temperature of the battery
■ Monitoring the temperature of the die to protect against silicon damage
■ Monitoring the time spent in the various charge states
■ Enabling/disabling the charger circuitry based on the monitored information
■ Driving the user visible charger status LED(s)

11.4 Battery Charger Firmware and PS Keys

The battery charger firmware sets up the charger hardware based on the PS Key settings and call traps from the
VM charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the

CSR8640 BGA Data Sheet

battery capacity and type, which are set by the user in the PS Keys.
For more information on the CSR8640 BGA, including details on setting up, calibrating, trimming and the PS Keys,
see Lithium Polymer Battery Charger Calibration and Operation for CSR8670 application note.

11.5 External Mode

The external mode is for charging higher capacity batteries using an external pass device. The current is controlled
by sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop
across a resistor, Rsense, connected in series with the external pass device, see Figure 11.2. The voltage drop is
determined by looking at the difference between the VBAT_SENSE and VBAT pins. The voltage drop across
Rsense is typically 200mV. The value of the external series resistor determines the charger current. This current can
be trimmed with a PS Key.
In Figure 11.2, R1 (220mΩ) and C1 (4.7µF) form a RC snubber that is required to maintain stability across all battery
ESRs. The battery ESR must be <1.0Ω

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 VCHG

CHG_EXT TR 1
External Pass Device

VBAT_SENSE

Rsense
VBAT

R1

G-TW-0005585.2.3
BAT 1
220mΩ Li+ Cell
C1
4.7µF

CSR8640 BGA Data Sheet

Figure 11.2: Battery Charger External Mode Typical Configuration

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12 Example Application Schematic
VBAT VBUS VBAT 3V3_USB 1V8_SMPS 1V35_SMPS 1V8_SMPS

V BAT_SENSE
CHG_EXT
S1
MFB

C1 C2 C3 L1 C4 C5 C6 L2 C7 C8 C9 C10 C11
2u2 2u2 2u2 4u7 2u2 10n 10n 4u7 4u7 15p 2u2 470n 100n

K 10
K4

K5

K7

K6

H9
A1

A7

K8

K3

K2
B5

B2

C2

E5

E6
J6

J7

J9

LX_1V35
VREGENA BLE

VCHG

VBAT_SENSE

LX_1V8

SM PS_1V8_SENSE
V DD_AUX_1V8

VDD_A UDIO

SMPS_1V35_SENSE

VDD_ANA _RADIO

V REGIN_DIG

VDD_PADS_1

VDD_PADS_2
3V3_USB
CHG_EXT

VBAT

VDD_DIG_MEM
VDD_AUDIO_DRV

VDD_A UX
XT1
26MHz

C1
XTAL_IN

VBAT 1V8 SMPS B1

CHARGER XTAL_OUT

AUX LDO 1V35

J2 LED_0
PIO[29]/LED[0]
3V3
ANA LDO 1V35
K1 LED_1
BYPASS REG 1V35 SMPS DIG LDO PIO[30]/LED[1]
B10 LED_2 LED Outputs
PIO[31]/LED[2]

1V35 F9 PIO_0
PIO[0]
F10 PIO_1
PIO[1]
E9 PIO_6
U2 PIO[6]
G10 PIO_7
PIO[7]
ANT 2 4 BT_RF A3 E10 PIO_8
OUT IN BT_RF PIO[8]
G9 PIO_9 PIO

CSR8640 BGA Data Sheet

PIO[9]
D9 PIO_18
Bluetooth RF PIO[18]
C9 PIO_19
PIO[19]
3 1 C10 PIO_20
GND GND PIO[20]
D10 PIO_21

CSR8640 BGA
PIO[21]
2.45GHz

PCB Layout Notes

H1 PIO_2
PIO[2]/PCM1_IN/SPI_MOSI
J5 PIO_3
PIO[3]/PCM1_OUT/SPI_MISO
E1 PIO_4
Ensure the following components are placed next to CSR8640 BGA PIO[4]/PCM1_SYNC/SPI_CS#
PIO[5]/PCM1_CLK/SPI_CLK
J1 PIO_5 PIO / PCM1 / Debug SPI / I2S
and have good low impedance connections both to signal and GND
J4 SPI_PCM# SPI / PCM# High For SPI. Low For All Other Functions
SPI_PCM#
C2 and C3
E2 PIO_12
PIO[12] / QSPI_FLASH_CS# / I2C_WP
Ensure the following tracks have good low impedance connections PIO[10] / QSPI_FLASH_CLK / I2C_SCL
F5 PIO_10
(no via share and short thick tracks) PIO[11] / QSPI_IO[0] / I2C_SDA
G2 PIO_11 PIO / Serial Flash / I2C
G1 PIO_13
PIO[13] / QSPI_IO[1]

VSS_SMPS_1V8 to Battery Ground F2 PIO_14

VSS_SMPS_1V35 to Battery Ground PIO[14] / UART_RX
D1 PIO_15
PIO[15] / UART_TX
PIO[16] / UART_RTS
F1 PIO_16 PIO / UART
H2 PIO_17
LX_1V8 to Inductor PIO[17] / UART_CTS

LX_1V35 to Inductor
D2 AIO_0
MIC BIAS AIO[0] Analogue Input / Output
L1 to C4 Track
V SS_BT_LO_AUX

V SS_SMPS_1V35

H10 USB_P
V SS_SMPS_1V8

L2 to C7 Track USB_P
J10 USB_N USB (12Mbps)
USB_N
V SS_AUDIO
V SS_BT_RF

MIC_BIA S

SPK R_RN
SPK R_LN

SPK R_RP
SPK R_L P
VSS_DIG

A U_REF

MIC_AN
C4 to GND

MIC_AP

MIC_BN
MIC_BP
C7 to GND J3 RSTB
RST# Reset
A2
B3
F6

A5

J8

K9

A8

MIC_1N A10

MIC_1P A9

MIC_BIA S B9

B7

MIC_2N B8

B4
A4

B6
A6
VBAT to Battery and C2 should be <1Ω from battery SP100

VCHG to charger connector and C1 STAR

MIC_2P
C12

SPK R_RN
SPK R_LN

SPK R_RP
SPK R_LP
2u2

VDD_DIG to Ground C13 C14 C15 C16

2u2 2u2 2u2 2u2
Ensure good low impedance ground return path through GND plane
for SMPSU current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35
L4 R1 R2
MIC_1
Ensure routing from L2 to ball K3 and from L2 to C8/C9 and ball C2 are kept separate 15nH 2k2 2k2
Mic1 C17
15p
CSR recommends low Rdc inductors (<0.5Ω) for L1 and L2 for optimum power efficiency
For example Taiyo Yuden CB2012T4R7M
Left Right
Dual-microphone Inputs
L5 Speakers (16Ω to 32Ω)
MIC_2
Suggest analogue and digital grounds are separated if possible 15nH Values of C13 to C16 can be reduced
Mic2 C18
15p at trade-off of bass response
or to minimise wind noise
and star connected near VSS_AUDIO as shown
Ensure analogue tracks stay over Analogue ground as much as possible

Optional Ancilliary Circuits

Optional Fast Charge USB / Charger Interface Lithium Polymer Battery Battery Temperature Sensor VBAT VBUS Typical LEDs and Buttons Optional I2C EEPROM Memory Optional 1 x SPI Flash Memory
400mΩ = 500mA (Built-in Battery Protection)
D100 1V8_SMPS C100 1V8_SMPS
BAT54C
VBUS CON100 VBUS PIO_5 1V8 1V8 1V8 1V8 1V8 C101
USB MINI-B R105 R106 R107 10n 10n 1V8_SMPS
1 VBAT R100 2k2 2k2 2k2 U101 U100
VBUS
GREEN

9k1
3

BLUE

2 USB_N 8 1 8 CLOCK PIO_n (even)

RED

Q100 D- D101 D102 D103 VCC A0 VDD

CHG_EXT 1 3 USB_P AIO_0 PIO_12 7 2
BCX51 D+
4 CON101 S100 S101 S102 S103 S104 PIO_10 6
WP A1
3 PIO_11 5 1 PIO_12 Digital
ID 3.7V F4 F3 F2 VOL+ VOL- SCL A2 SI/SIO0 CE
5 Li+ CELL PIO_11 5 4 PIO_13 2 6 PIO_10
C105 GND SDA VSS SO/SIO1 SCK Mic(s)
2

VBAT_SENSE 4u7 R101 R102 R103 3 DATA PIO_n (odd)

WP/SIO2
GND

GND

THERM100 220R 330R 330R 24AAxxx 7

G-TW-0007441.6.2
R104 R108 10k HOLD/SIO3
1V8_SMPS 4
1% VSS
220mR
LED_2

LED_1

LED_0
7

PIO_n

PIO_n

PIO_n

PIO_n

PIO_n

VBAT 400mR SPI Flash

Size of EEPROM Depends on Voice Prompt Requirements

Connect VBAT_SENSE to VBAT

If Not Using This Circuit

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13 Electrical Characteristics
13.1 Absolute Maximum Ratings
Rating Min Max Unit

Storage temperature -40 105 °C

Supply Voltage

Charger VCHG -0.4 5.75 V

LEDs LED[2:0] -0.4 4.40 V

VBAT_SENSE -0.4 4.20 V

Battery
VREGENABLE -0.4 4.20 V

VDD_AUDIO_DRV -0.4 1.95 V

CSR8640 BGA Data Sheet

VDD_AUX_1V8 -0.4 1.95 V

1.8V VDD_PADS_1 -0.4 3.60 V

VDD_PADS_2 -0.4 3.60 V

VDD_AUX_1V8 -0.4 1.95 V

SMPS_1V35_SENSE -0.4 1.45 V

1.35V VDD_AUDIO -0.4 1.45 V

VREGIN_DIG -0.4 1.95 V

Other terminal voltages VSS - 0.4 VDD + 0.4 V

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13.2 Recommended Operating Conditions
Rating Min Typ Max Unit

Operating temperature range -40 20 85 °C

Supply Voltage

Charger VCHG 4.75 / 3.10 5.00 5.25 V

LEDs LED[2:0] 1.10 3.70 4.25 V

VBAT_SENSE 0 3.70 4.20 V

Battery
VREGENABLE 0 3.70 4.20 V

VDD_AUDIO_DRV 1.70 1.80 1.95 V

VDD_AUX_1V8 1.70 1.80 1.95 V

CSR8640 BGA Data Sheet

1.8V VDD_PADS_1 1.70 1.80 3.60 V

VDD_PADS_2 1.70 1.80 3.60 V

VDD_AUX_1V8 1.25 1.80 1.95 V

SMPS_1V35_SENSE 1.30 1.35 1.40 V

1.35V VDD_AUDIO 1.30 1.35 1.40 V

VREGIN_DIG 1.30 1.35 or 1.80 1.95 V

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13.3 Input/Output Terminal Characteristics
Note:
For all I/O terminal characteristics:
■ Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.

13.3.1 Regulators: Available For External Use

13.3.1.1 1.8V Switch-mode Regulator

1.8V Switch-mode Regulator Min Typ Max Unit

Input voltage 2.70 3.70 4.25 V

Output voltage 1.70 1.80 1.90 V

Normal Operation

Transient settling time - 30 - μs

CSR8640 BGA Data Sheet

Load current - - 185 mA

Current available for external use, stereo audio with 16Ω load(a) - - 25 mA

Peak conversion efficiency(b) - 90 - %

Switching frequency 3.63 4.00 4.00 MHz

Inductor saturation current, stereo and 16Ω load 250 - - mA

Inductor ESR 0.1 0.3 0.8 Ω

Low-power Mode, Automatically Entered in Deep Sleep

Transient settling time - 200 - μs

Load current 0.005 - 5 mA

Current available for external use - - 5 mA

Peak conversion efficiency - 85 - %

Switching frequency 100 - 200 kHz

(a) More current available for audio loads above 16Ω.

(b) Conversion efficiency depends on inductor selection.

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13.3.1.2 Combined 1.8V and 1.35V Switch-mode Regulator

Combined 1.8V and 1.35V Switch-mode Regulator Min Typ Max Unit

Input voltage 2.70 3.60 4.25 V

Output voltage 1.70 1.80 1.90 V

Normal Operation

Transient settling time - 30 - μs

Load current - - 340 mA

Current available for external use, stereo audio with 16Ω load(a) - - 25 mA

Peak conversion efficiency(b) - 90 - %

Switching frequency 3.63 4.00 4.00 MHz

CSR8640 BGA Data Sheet

Inductor saturation current, stereo and 16Ω load 400 - - mA

Inductor ESR 0.1 0.3 0.8 Ω

Low-power Mode, Automatically Entered in Deep Sleep

Transient settling time - 200 - μs

Load current 0.005 - 5 mA

Current available for external use - - 5 mA

Peak conversion efficiency - 85 - %

Switching frequency 100 - 200 kHz

(a) More current available for audio loads above 16Ω.

(b) Conversion efficiency depends on inductor selection.

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13.3.1.3 Bypass LDO Regulator

Normal Operation Min Typ Max Unit

Input voltage(a) 4.75 / 3.10 5.00 5.25 V

Output voltage (Vin > 4.75V) 3.00 3.30 3.60 V

Output current (Vin > 4.75V) - - 250 mA

(a) Minimum input voltage of 4.75V is required for full specification, regulator operates at reduced load current from 3.1V.

13.3.2 Regulators: For Internal Use Only

13.3.2.1 1.35V Switch-mode Regulator

1.35V Switch-mode Regulator Min Typ Max Unit

Input voltage 2.70 3.60 4.25 V

CSR8640 BGA Data Sheet

Output voltage 1.30 1.35 1.40 V

Normal Operation

Transient settling time - 30 - μs

Load current - - 160 mA

Current available for external use, stereo audio with 16Ω load - - 0 mA

Peak conversion efficiency(a) - 88 - %

Switching frequency 3.63 4.00 4.00 MHz

Inductor saturation current, stereo and 16Ω load 220 - - mA

Inductor ESR 0.1 0.3 0.8 Ω

Low-power Mode, Automatically Entered in Deep Sleep

Transient settling time - 200 - μs

Load current 0.005 - 5 mA

Current available for external use - - 0 mA

Peak conversion efficiency - - 85 %

Switching frequency 100 - 200 kHz

(a) Conversion efficiency depends on inductor selection.

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13.3.2.2 Low-voltage VDD_DIG Linear Regulator

Normal Operation Min Typ Max Unit

Input voltage 1.30 1.35 or 1.80 1.95 V

Output voltage(a) 0.80 0.90 / 1.20 1.25 V

Internal load current - - 80 mA

(a) Output voltage level is software controlled

13.3.2.3 Low-voltage VDD_AUX Linear Regulator

Normal Operation Min Typ Max Unit

Input voltage 1.70 1.80 1.95 V

Output voltage 1.30 1.35 1.45 V

CSR8640 BGA Data Sheet

Internal load current - - 5 mA

13.3.2.4 Low-voltage VDD_ANA Linear Regulator

Normal Operation Min Typ Max Unit

Input voltage 1.70 1.80 1.95 V

Output voltage 1.30 1.35 1.45 V

Load current - - 60 mA

13.3.3 Regulator Enable

VREGENABLE, Switching Threshold Min Typ Max Unit

Rising threshold 1.0 - - V

13.3.4 Battery Charger

Battery Charger Min Typ Max Unit

Input voltage, VCHG(a) 4.75 / 3.10 5.00 5.25 V

(a) Reduced specification from 3.1V to 4.75V. Full specification >4.75V.

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Trickle Charge Mode Min Typ Max Unit

Charge current Itrickle, as percentage of fast charge current 8 10 12 %

Vfast rising threshold - 2.9 - V

Vfast rising threshold trim step size - 0.1 - V

Vfast falling threshold - 2.8 - V

Fast Charge Mode Min Typ Max Unit

I-CTRL = 0x1f,
194 200 206 mA
headroom > 0.55V
Charge current during constant
current mode, Ifast
I-CTRL = 0x00,
43 45 47 mA
headroom > 0.55V

Reduced headroom charge current, I-CTRL = 0x0f,

CSR8640 BGA Data Sheet

50 - 100 %
as a percentage of Ifast headroom = 0.15V

I-CTRL charge current step size - 5 - mA

Vfloat threshold, calibrated 4.16 4.20 4.24 V

Standby Mode Min Typ Max Unit

Voltage hysteresis on VBAT, Vhyst 100 - 150 mV

Error Charge Mode Min Typ Max Unit

Headroom(a) error rising threshold 30 - 50 mV

Headroom(a) error threshold hysteresis 20 - 30 mV

(a) Headroom = VCHG - VBAT

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External Charge Mode(a) Min Typ Max Unit

Fast charge current, Ifast 200 - 500 mA

Control current into CHG_EXT 0 - 20 mA

Voltage on CHG_EXT 0 - 5.75 V

External pass device hfe - 50 - -

Sense voltage, between VBAT_SENSE and VBAT at maximum

195 200 205 mV
current

(a) In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical
characteristics are listed in this table.

13.3.5 USB

Min Typ Max Unit

CSR8640 BGA Data Sheet

3V3_USB for correct USB operation 3.0 3.3 3.6 V

Input Threshold

VIL input logic level low 0.3 x

- - V
3V3_USB

VIH input logic level high 0.7 x

- - V
3V3_USB

Output Voltage Levels to Correctly Terminated USB Cable

VOL output logic level low 0 - 0.2 V

VOH output logic level high 2.8 - 3V3_USB V

13.3.6 Clocks

Crystal Oscillator Min Typ Max Unit

Frequency 16 26 32 MHz

Crystal load capacitance - 9 - pF

Frequency stability - - 20 ppm

Frequency tolerance - - ±20 ppm

Pullability 10 15 30 ppm/pF

Transconductance 2 - - mS

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13.3.7 Stereo Codec: Analogue to Digital Converter

Analogue to Digital Converter

Parameter Conditions Min Typ Max Unit

Resolution - - - 16 Bits

Input Sample Rate,

- 8 - 48 kHz
Fsample

Fsample

fin = 1kHz 8kHz - 92 - dB

B/W = 20Hz→Fsample/2
(20kHz max) 16kHz - 89 - dB
SNR
A-Weighted
32kHz - 88 - dB
THD+N < 1%
1.6Vpk-pk input
44.1kHz - 88 - dB

CSR8640 BGA Data Sheet

48kHz - 88 - dB

fin = 1kHz Fsample

B/W = 20Hz→Fsample/2
THD+N 8kHz - 0.0036 - %
(20kHz max)
1.6Vpk-pk input
48kHz - 0.0052 - %

Digital gain Digital gain resolution = 1/32 -24 - 21.5 dB

Pre-amplifier setting = 0dB, 9dB, 21dB or

30dB
Analogue gain -3 - 42 dB
Analogue setting = -3dB to 12dB in 3dB
steps

Stereo separation (crosstalk) - -86 - dB

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13.3.8 Stereo Codec: Digital to Analogue Converter

Digital to Analogue Converter

Parameter Conditions Min Typ Max Unit

Resolution - - - 16 Bits

Output Sample
- 8 - 96 kHz
Rate, Fsample

Fsample Load
fin = 1kHz
B/W = 20Hz→20kHz 48kHz 100kΩ - 92 - dB
SNR A-Weighted
THD+N < 0.1% 48kHz 32Ω - 93 - dB
0dBFS input
48kHz 16Ω - 93 - dB

Fsample Load

CSR8640 BGA Data Sheet

8kHz 100kΩ - 0.0019 - %

8kHz 32Ω - 0.0024 - %

fin = 1kHz
THD+N B/W = 20Hz→20kHz 8kHz 16Ω - 0.0032 - %
0dBFS input
48kHz 100kΩ - 0.0026 - %

48kHz 32Ω - 0.0036 - %

48kHz 16Ω - 0.0052 - %

Digital Gain Digital Gain Resolution = 1/32 -24 - 21.5 dB

Analogue Gain Analogue Gain Resolution = 3dB -21 - 0 dB

Stereo separation (crosstalk) - -88 - dB

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13.3.9 Digital

Digital Terminals Min Typ Max Unit

Input Voltage

VIL input logic level low -0.4 - 0.4 V

VIH input logic level high 0.7 x VDD - VDD + 0.4 V

Tr/Tf - - 25 ns

Output Voltage

VOL output logic level low, lOL = 4.0mA - - 0.4 V

VOH output logic level high, lOH = -4.0mA 0.75 X VDD - - V

Tr/Tf - - 5 ns

CSR8640 BGA Data Sheet

Input and Tristate Currents

Strong pull-up -150 -40 -10 μA

Strong pull-down 10 40 150 μA

Weak pull-up -5 -1.0 -0.33 μA

Weak pull-down 0.33 1.0 5.0 μA

CI Input Capacitance 1.0 - 5.0 pF

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13.3.10 LED Driver Pads

LED Driver Pads Min Typ Max Unit

High impedance state - - 5 µA

Current, IPAD
Current sink state - - 10 mA

LED pad voltage, VPAD IPAD = 10mA - - 0.55 V

LED pad resistance VPAD < 0.5V - - 40 Ω

VOL output logic level low(a) - 0 - V

VOH output logic level high(a) - 0.8 - V

VIL input logic level low - 0 - V

VIH input logic level high - 0.8 - V

CSR8640 BGA Data Sheet

(a) LED output port is open-drain and requires a pull-up

13.3.11 Auxiliary ADC

Auxiliary ADC Min Typ Max Unit

Resolution - - 10 Bits

Input voltage range(a) 0 - VDD_AUX V

INL -1 - 1 LSB
Accuracy
(Guaranteed monotonic)
DNL 0 - 1 LSB

Offset -1 - 1 LSB

Gain error -0.8 - 0.8 %

Input bandwidth - 100 - kHz

Conversion time 1.38 1.69 2.75 µs

Sample rate(b) - - 700 Samples/s

(a) LSB size = VDD_AUX/1023

(b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.

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13.3.12 Auxiliary DAC

Auxiliary DAC Min Typ Max Unit

Resolution - - 10 Bits

Supply voltage, VDD_DAC 1.30 1.35 1.40 V

Output voltage range 0 - VDD_AUX V

Full-scale output voltage 1.30 1.35 1.40 V

LSB size 0 1.32 2.64 mV

Offset -1.32 0 1.32 mV

Integral non-linearity -1 0 1 LSB

Settling time(a) - - 250 ns

CSR8640 BGA Data Sheet

(a) The settling time does not include any capacitive load

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13.4 ESD Protection
Apply ESD static handling precautions during manufacturing.
Table 13.1 shows the ESD handling maximum ratings.

Condition Class Max Rating

Human Body Model Contact Discharge per TBDV (all pins except RF),
TBD
JEDEC EIA/JESD22‑A114 TBDV (for RF pins)

Machine Model Contact Discharge per TBDV (all pins except for RF and USB),
TBDV TBDV (for RF pins), TBDkV (for USB_DP
JEDEC EIA/JESD22‑A115 and USB_DN)

Charged Device Model Contact Discharge per TBDV (all pins except RF), TBDV (for RF
TBD
JEDEC EIA/JESD22‑C101 pins)

Table 13.1: ESD Handling Ratings

CSR8640 BGA Data Sheet

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14 Power Consumption
Average
DUT Role Connection Packet Type Packet Size Unit
Current

Slave SCO HV3 30 TBD mA

Slave eSCO EV3 30 TBD mA

Slave eSCO 2EV3 60 TBD mA

Slave eSCO 2EV3 30 TBD mA

Slave SCO 2-mic CVC HV3 30 TBD mA

Slave eSCO 2-mic CVC 2EV3 60 TBD mA

Slave eSCO 2-mic CVC 2EV3 30 TBD mA

CSR8640 BGA Data Sheet

Stereo high quality:
■ SBC
Slave TBD TBD TBD mA
■ 350kbps
■ No sniff

Stereo high quality:

■ SBC
Slave TBD TBD TBD mA
■ 350kbps
■ Sniff

Stereo high quality:

■ MP3
Slave TBD TBD TBD mA
■ 128kbps
■ No sniff

Stereo high quality:

■ MP3
Slave TBD TBD TBD mA
■ 128kbps
■ Sniff

Slave ACL Sniff = 100ms - - TBD mA

Slave ACL Sniff = 500ms - - TBD mA

Slave ACL Sniff = 1280ms - - TBD mA

Master SCO HV3 30 TBD mA

Master eSCO EV3 30 TBD mA

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 Average
DUT Role Connection Packet Type Packet Size Unit
Current

Master eSCO 2EV3 60 TBD mA

Master eSCO 2EV3 30 TBD mA

Master SCO 2-mic CVC HV3 30 TBD mA

Master eSCO 2-mic CVC 2EV3 60 TBD mA

Master eSCO 2-mic CVC 2EV3 30 TBD mA

Master ACL Sniff = 100ms - - TBD mA

Master ACL Sniff = 500ms - - TBD mA

Master ACL Sniff = 1280ms - - TBD mA

CSR8640 BGA Data Sheet

Note:
Current consumption values are taken with:
■ VBAT pin = 3.7V
■ RF TX power set to 0dBm
■ No RF retransmissions in case of eSCO
■ Microphones and speakers disconnected, with internal microphone bias circuit set to minimum current
level
■ Audio gateway transmits silence when SCO/eSCO channel is open
■ LEDs disconnected

Advance Information Page 89 of 110

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15 CSR Green Semiconductor Products and RoHS Compliance
CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements:
■ Restriction on Hazardous Substances directive guidelines in the EU RoHS Directive 2002/95/EC. This
includes compliance with the requirements for Deca BDE, as per removal of exemption, implementation
date 01-Jul-08
EU REACH, Regulation (EC) No 1907/2006:
■ List of substances subject to authorisation (Annex XIV)
■ Restrictions on the manufacture, placing on the market and use of certain dangerous substances,
preparations and articles (Annex XVII). This Annex now includes requirements that were contained
within EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including,
but not limited to, the control of use of Perfluorooctane sulfonates (PFOS).
■ Substances identified on candidate list as Substances of Very High Concern (SVHC), 46 substances
as per update published 15 December 2010.
■ EU Commission Decision 2009/251/EC:
■ Products containing dimethylfumarate (DMF) are not placed or made available on the market.
■ EU Packaging and Packaging Waste, Directive 94/62/EC
■ Montreal Protocol on substances that deplete the ozone layer
Additionally, Table 15.1 shows that CSR Green semiconductor products are free from bromine, chlorine or antimony

CSR8640 BGA Data Sheet

trioxide and other hazardous chemicals.

Material Maximum Allowable Amount

Cadmium (Cd) 100ppm

Lead (Pb) 1000ppm (solder), 100pm (plastic)

Mercury (Hg) 1000ppm

Hexavalent-Chromium (Cr VI) 1000ppm

Polybrominated biphenyls (PBB) 1000ppm

Polybrominated diphenyl ethers (PBDE) 1000ppm

Bromine, Chlorine 900ppm, <1500ppm combined

Antimony Trioxide (Sb2O3) 900ppm

Benzene 1000ppm

Beryllium and compounds (other than Beryllium Oxide (BeO) 1000ppm

Halogenated Diphenyl Methanes 1000ppm

(Monomethyltetrachloro Diphenyl Methane (CAS# 76253-60-6),
Monomethyldichloro Diphenyl Methane (CAS# 81161-70-8),
Monomethyldibromo Diphenyl Methane (CAS# 99788-47-8)

Red phosphorous 1000ppm

1,1,1-trichloroethane Banned

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Material Maximum Allowable Amount

Aliphatic CHCs (chlorohydrocarbons) Banned

Benzotriazole (2-3',5'-Di-tert-butyl-2'-hydroxyphenyl) Banned

Beryllium Oxide Banned

Chlorinated paraffin (including short chain chlorinated paraffins – carbon Banned

chain length 10-13 and medium chain chlorinated paraffins – carbon chain
length 14-17)

Formaldehyde Banned as described

(Banned in wooden, adhesive and plastic products)

Hydrofluorocarbon (HFC) Banned

NPs (nonylphenols) and NPEs (nonylphenol ethoxylates) Banned as described

(Banned in textile, leather, metal, pulp and paper parts)

CSR8640 BGA Data Sheet

Organic tin compounds Banned

Perfluorocarbon (PFC) Banned

Polychlorinated napthalenes (PCN) Banned

Polychlorinated terphenyls (PCT) Banned

Polychlorinated biphenyls (PCB) Banned

Polyvinyl Chloride (PVC) Banned

Sulfur hexafluoride Banned

Tetrachloromethane (CAS# 56-23-5) Banned

Asbestos Banned as intentionally introduced

Phthalates Banned as intentionally introduced

Radioactive substances Banned as intentionally introduced: reportable

Tributyl tin (TBT) / Triphenyl tin (TPT) / Tributyl Tin Oxide (TBTO) Banned as intentionally introduced
Dibutyl Tin (DBT) and Dioctyl Tin Compounds (DOT)

Table 15.1: Chemical Limits for Green Semiconductor Products

Products and shipment packaging are marked and labelled with applicable environmental marking symbols in
accordance with relevant regulatory requirements.
CSR has defined this Green standard based on current regulatory and customer requirements. For more information
contact product.compliance@csr.com.

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16 Software
CSR8640 BGA:
■ Includes integrated Bluetooth v3.0 specification qualified HCI stack firmware
■ Includes integrated CSR8640 Stereo Headset, with 6th generation 2-mic CVC audio enhancements and a
configurable EQ
■ Can be shipped with CSR’s CSR8640 stereo headset development kit for CSR8640 BGA, order code
DK-8640-10061-1A
The CSR8640 BGA software architecture enables Bluetooth processing and the application program to run on the
internal RISC MCU, and the audio enhancements on the Kalimba DSP.

16.1 CSR8640 Stereo Headset

The CSR stereo headset ROM software supports:
■ 6th generation 2-mic CVC audio enhancements
■ WNR
■ PLC / BEC
■ mSBC wideband speech codec
■ A2DP v1.2

CSR8640 BGA Data Sheet

■ HFP v1.6 and HSP v1.2
■ Bluetooth v3.0 specification is supported in the ROM software
■ Secure simple pairing
■ Proximity pairing (headset-initiated pairing) for greatly simplifying the out-of-box pairing process, for more
information see Section 16.1.8
■ For connection to more than 1 mobile phone, advanced Multipoint is supported. This enables a user to take
calls from a work and personal phone or a work phone and a VoIP dongle for Skype users. This has minimal
impact on power consumption and is easy to configure.
■ Most of the CSR8640 stereo headset ROM software features are configured on the CSR8640 BGA using
the Headset Configurator tool. The tool reads and writes headset configurations directly to the EEPROM,
serial flash or alternatively to a PSR file. Configurable headset features include:
■ Bluetooth v3.0 specification features
■ Reconnection policies, e.g. reconnect on power-on
■ Audio features, including default volumes
■ Button events: configuring button presses and durations for certain events, e.g. double press on
PIO[1] for last number redial
■ LED indications for states, e.g. headset connected, and events, e.g. power on
■ Indication tones for events and ringtones
■ HFP v1.6 supported features
■ Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc.
■ Advanced Multipoint settings
■ Configurable 5-band EQ for music playback (rock, pop, classical, jazz, dance etc)
■ SBC, MP3 and Faststream decoder
■ Stereo widening (S3D)
■ Volume Boost
■ USB audio mode for streaming high-quality music from a PC whilst charging, enables the headset to:
■ Playback high-quality stereo music, e.g. iTunes
■ Use bidirectional audio in conversation mode, e.g. for Skype

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 ■ Wired audio mode for pendant-style headsets supports music playback using a line-in jack. Enables non
Bluetooth operation in low battery modes or when using the headset in an airplane-mode.
■ Support for smartphone applications (apps)
■ The CSR8640 stereo headset has undergone extensive interoperability testing to ensure it works with the
majority of phones on the market

16.1.1 Advanced Multipoint Support

Advanced Multipoint enables the connection of 2 devices to a CSR8640 BGA headset at the same time, examples
include:
■ 2 phones connected to a CSR8640 BGA headset
■ Phone and a VoIP dongle connected to a CSR8640 BGA headset
The CSR8640 stereo headset:
■ Supports a up to 2 simultaneous connections (either HFP or HSP)
■ Enables multiple-call handling from both devices at the same time
■ Treats all headset buttons:
■ During a call from 1 device, as if there is 1 device connected
■ During multiple calls (1 on each device), as if there is a single AG with multiple calls in progress (three-
way calling)
■ During multiple calls (more than 1 on each device), as if there are multiple calls on a single device
enabling the user to switch between the active and held calls

CSR8640 BGA Data Sheet

16.1.2 A2DP Multipoint Support
A2DP Multipoint support enables the connection of 2 A2DP source devices to CSR8640 BGA at the same time,
examples include:
■ 2 A2DP-capable phones connected to a CSR8640 BGA headset
■ A2DP-capable phone and an A2DP-only source device, e.g. a PC or an iPod touch
The CSR8640 stereo headset enables:
■ Music streaming from either of the connected A2DP source devices where the music player is controlled
on the source device
■ Advanced HFP Multipoint functions to interrupt music streaming for calls, and resume music streaming on
the completion of the calls
■ AVRCP v1.4 connections to both connected devices, enabling the headset to remotely control the primary
device, i.e. the device currently streaming audio

16.1.3 Wired Audio Mode

CSR8640 BGA supports a wired audio mode for playing music over a wired connection. This enables the headset
to operate when the battery is too low for Bluetooth operation or in environments where the use of wireless
technologies is not permitted, e.g. airplane-mode.
The CSR8640 stereo headset automatically routes the wired audio input to the headphone output when
CSR8640 BGA is not powered.
If CSR8640 BGA is powered, the audio path is routed through CSR8640 BGA, including via the DSP, this enables
the headset to:
■ Mix audio sources, e.g. tones and programmable audio prompts
■ Control the volume of the audio, i.e. volume up and volume down
■ Utilise the 5 band EQ
The wired audio mode can be used in conjunction with the USB audio mode, see Section 16.1.4. USB audio has
priority if attached and is routed to the headset speaker if CSR8640 BGA is powered.

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In wired audio mode, if required, the headset is still available for Bluetooth audio. This enables seamless transition
from wired audio mode to Bluetooth audio mode and back again. This transition is configurable to occur automatically
as the battery voltage of the headset reduces to a point at which Bluetooth audio is no longer possible.
The additional development board CNS11010 enables support for the wired input mode and is available as part of
the development kit.

16.1.4 USB Modes Including USB Audio Mode

CSR8640 BGA supports a variety of USB modes which enables the USB interface to extend the functionality of a
CSR8640 BGA based stereo headset.
CSR8640 BGA supports:
■ USB charger enumeration
■ USB soundcard enumeration (USB audio mode)
■ USB mass storage enumeration
USB audio mode enables the headset to enumerate as a soundcard while charging from a USB master device,
e.g. a PC. In this mode, the headset enumerates as either a stereo music soundcard (for high quality music playback)
or a bidirectional voice quality soundcard. This enables the headset for either listening to music streaming from the
USB host device or for voice applications, e.g. Skype.
The USB audio mode operates at the same time as the wired audio mode and the USB audio interrupts the wired

CSR8640 BGA Data Sheet

audio mode if USB audio is attached. This enables a headset to have both wired audio and USB modes connected
at the same time.
In USB audio mode, if required, the headset is still available for Bluetooth audio.

16.1.5 Smartphone Applications (Apps)

CSR8640 BGA includes CSR’s proprietary mechanism for communicating with smartphone apps, it enables full
UI control of the headset from within the application running on a smartphone, e.g. Google Android OS-based
handset. For more information on this feature contact CSR.

16.1.6 Programmable Audio Prompts

CSR8640 BGA enables a user to configure and load pre-programmed audio prompts from:
■ An external EEPROM, in this implementation the prompts are stored in the same EEPROM as the PS
Keys, see Figure 16.2. A larger EEPROM is necessary for programmable audio prompts. This
implementation supports EEPROMs up to 512Kb. An EEPROM of 512Kb enables approximately 15
seconds of audio storage.
■ An external SPI flash, in this implementation the prompts are stored in the same SPI flash as the PS
Keys, see Figure 16.1.
The programmable audio prompts provide a mechanism for higher-quality audio indications to replace standard tone
indications. A programmable audio prompt is assigned to any user event in place of a standard tone.
Programmable audio prompts contain either voice prompts to indicate that events have occurred or provide user-
defined higher quality ring tones/indications, e.g. custom power on/off tones.
The Headset Configurator tool can generate the content for the programmable audio prompts from standard WAV
audio files. The tool also enables the user to configure which prompts are assigned to which user events.
Section 6.5 describes the SPI flash interface and Section 7.4 describes the I²C interface to an external EEPROM.

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 SPI Flash
PS Keys
Configuration

Patches

CSR8640 SPI

G-TW-0007447.2.2
Programmable
Audio Prompts

Figure 16.1: Programmable Audio Prompts in External SPI Flash

EEPROM
PS Keys

CSR8640 BGA Data Sheet

Configuration

Patches

CSR8640 I2C

G-TW-0007448.1.1
Programmable
Audio Prompts

Figure 16.2: Programmable Audio Prompts in External I²C EEPROM

Note:

When using the SPI flash interface for programmable audio prompts, an EEPROM device is not required in the
CSR8640 stereo headset.

16.1.7 CSR’s Intelligent Power Management

IPM extends the available talk time of a CSR8640 BGA-based headset, by automatically reducing the audio
processing performed by CVC at a series of low battery capacity thresholds.
Configurable IPM features include:
■ IPM enable/disable
■ The battery capacity that engages IPM
■ A user-action to enable or disable the IPM
If engaged, CVC processing reduces automatically on reaching the preset battery capacity. Once the audio is
terminated, the DSP shuts down to achieve maximum power savings before the next call.
IPM resets when recharging the headset. The talk time extension depends on:
■ The battery size
■ The battery condition
■ The threshold capacity configured for the IPM to engage

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16.1.8 Proximity Pairing
Proximity pairing is headset-initiated pairing and it simplifies the out-of-box pairing process. Proximity pairing enables
the headset to find the closest discoverable phone. The headset then initiates the pairing activity and the user simply
has to accept the incoming pairing invitation on the phone.
This means that the phone-user does not have to hunt through phone menus to pair with the new headset.
Depending on the phone UI:
■ For a Bluetooth v2.0 phone the headset pairing is with a PIN code
■ For a Bluetooth v2.1 (or above) phone the headset pairing is without a PIN code
Proximity pairing is based on finding and pairing with the closest phone. To do this, the headset finds the loudest
phone by carrying out RSSI power threshold measurements. The loudest phone is the one with the largest RSSI
power threshold measurement, and it is defined as the closest device. The headset then attempts to pair with and
connect to this device.
Proximity pairing is configurable using the Headset Configurator tool available from www.csrsupport.com.

16.1.9 Proximity Connection

Proximity connection is an extension to proximity pairing, see Section 16.1.8. It enables the headset‑user to take
advantage of the proximity of devices each time the headset powers up and not just during a first time pairing event.

CSR8640 BGA Data Sheet

Proximity connection enables a user with multiple handsets to easily connect to the closest discoverable phone by
comparing the proximity of devices to the headset at power-on to the list of previously paired devices.
Proximity connection speeds up the headset connection process. It requires the headset to initiate a SLC connection
to the nearest device first and combines this with the headset's storage of the last 8 paired/connected devices. Using
proximity connection means functions like power on into an incoming call operate equally well for the most recently
paired or connected device, as well as the least recently paired or connected device.

16.2 6th Generation 2-mic CVC Audio Enhancements

2-mic CVC full-duplex voice processing software is a fully integrated and highly optimised set of DSP algorithms
developed to ensure easy design and build of echo and noise‑cancelling headset products.
CVC enables greater acoustic design flexibility by incorporating software to compensate for cost-optimised
microphone‑to‑speaker coupling and placement. CVC-enabled headsets operate in a wide variety of acoustic
environments. Sophisticated noise suppression technology reduces the impact of noise in the transmission channel.
Using intelligent volume control and intelligibility improvements, the receive channel is also enhanced based on the
acoustic noise in the listener's environment.
The 6th generation CVC provides 3 new major features:
■ A high performance Wind Noise Reduction module provides significant reduction of both front and side
wind noise. This uses a very low-power algorithm which automatically cuts in only on the detection of wind
noise.
■ A 16kHz sample rate for full compliance across the suite of DSP algorithms
■ Frequency enhanced speech intelligibility
2-mic CVC includes a tuning tool enabling the developer to easily adapt CVC with different audio configurations and
tuning parameters. The tool provides real-time system statistics with immediate feedback enabling designers to
quickly investigate the effect of changes.
Figure 16.3 shows the functional block diagram of CSR’s proprietary 2-mic CVC DSP solution for a dual-microphone
headset product.

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 Dual-microphone
Wind Noise Noise Acoustic Echo
Signal Comfort Noise Equaliser AGC
Reduction Suppression Canceller
Separation
Mic Gain

NDVC

Bluetooth Radio
Side
Tone

G-TW-0007444.2.2
Auxiliary Stream
Mix

Adaptive Noise Packet Loss

DAC Clipper AGC Equaliser
Equaliser Suppression Concealment

Figure 16.3: 2-mic CVC Block Diagram

Section 16.2.3 to Section 16.2.13 describe the audio processing functions provided within CVC.

16.2.1 Wind Noise Reduction

The wind noise algorithm achieves excellent wind noise reduction with very low power overhead, which has a

CSR8640 BGA Data Sheet

negligible impact on battery life. The wind noise capability operates in the noise suppression block in the transmit
path and dynamically detects and engages when wind noise is present. SNR improvements depend on wind
direction, speech and microphone placement. Improvements of up to 32dB are achievable using the DSP module.
CVC wind noise performance is further improved by suitable mechanical baffling of the microphone which is
optimised during the tuning process.

16.2.2 Dual-microphone Signal Separation

The dual-microphone signal separation is the major dynamic noise suppression block in 2-mic CVC. It separates
the speech from the competing noises. It achieves this by first applying a pre-stage algorithm using a blind source
separation processing technique. Blind source separation is a rules based filter which uses the 2 microphone's spatial
information, direction of arrival and power ratios assumptions etc.
Blind source separation results in speech (S1) and noise (S2) dominant outputs. These outputs are then processed
by a post stage adaptive noise canceller filter to further reduce the environmental noise, resulting in a single-channel
noise suppressed output. Depending on the acoustic arrangement of the microphone and the noise type, the dual-
microphone signal separation block provides up to 22dB SNR of dynamic noise suppression.

16.2.3 Noise Suppression

The noise suppression block is implemented in both signal paths. It is completely independent and is individually
tuned. Noise suppression is a sub-band stationary / quasi-stationary noise suppression algorithm that uses the
temporal characteristics of speech and noise to remove the noise from the composite signal while maximising speech
quality. The current implementation has the capability to improve the SNR by > 20dB.

16.2.4 Acoustic Echo Cancellation

The AEC includes:
■ A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point
to the microphone input
■ Non-linear echo cancellation. A non-linear processing function that adaptively applies additional attenuation
when excessive residual echo is detected after the linear filter

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16.2.5 Comfort Noise Generator
The CNG:
■ Creates a spectrally and temporally consistent noise floor for the far-end listener
■ Adaptively inserts noise modelled from the noise present at the microphone into gaps introduced when
attenuation is applied by the non-linear processing of the AEC

16.2.6 Equalisation
The equalisation filters:
■ Have independent equalisation modules provided in the send and receive signal paths:
■ Each module comprises of 5 bands of equalisation using cascaded 2nd order IIR filters
■ Are fully configurable using a graphical tuning tool
■ Provide static compensation for the frequency response of transducers in the system

16.2.7 Automatic Gain Control

The AGC block attempts to:
■ Normalise the amplitude of the incoming audio signal to a desired range to increase perceived loudness
■ Reduce distortion due to clipping
■ Reduce amplitude variance observed from different users, phones, and networks

CSR8640 BGA Data Sheet

Maintaining a consistent long-term loudness for the speech ensures it is more easily heard by the listener and it also
provides the subsequent processing block a larger amplitude signal to process. The behaviour of the AGC differs
from a dynamic range audio compressor. The convergence time for the AGC is much slower to reduce the non-
linear distortion.

16.2.8 Packet Loss Concealment

Bit errors and packet loss can occur in the Bluetooth transmission due to a variety of reasons, e.g. Wi-Fi interference
or RF signal degradation due to distance or physical objects. As a result of these errors, the user hears glitches
referred to as pops and clicks in the audio stream. The PLC block improves the receive path audio quality in the
presence of bit and packet errors within the Bluetooth link by using a variety of techniques such as pitch-based
waveform substitution.
The PLC significantly improves dealing with bit errors, using the BFI output from the firmware. The DSP calculates
an average BER and selectively applies the PLC to the incoming data. This optimises audio quality for a variety of
bit errors and packet loss conditions. The PLC is enabled in all modes.

16.2.9 Adaptive Equalisation

The adaptive equalisation block improves the intelligibility of the receive path voice signal in the presence of near‑end
noise by altering the spectral shape of the receive path signal while maintaining the overall power level. The adaptive
equaliser can also compensate for variations in voice transmission channels.

16.2.10 Auxiliary Stream Mix

The auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps and voice
prompts with the incoming SCO stream. This avoids any interruption to the SCO stream and as a result prevents
any speech from being lost.

16.2.11 Clipper
The clipper block intentionally limits the amplitude of the receive signal prior to the reference input of the AEC to
more accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier, and the
loudspeaker. This processing block can significantly improve the echo performance in cost-optimised loudspeakers.

Advance Information Page 98 of 110

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16.2.12 Noise Dependent Volume Control
The NDVC block improves the intelligibility of the receive path signal by increasing the analogue DAC gain value
based on the send noise estimate from the send path noise suppression block. As the send noise estimate increases,
the NDVC algorithm increases the analogue DAC gain value. The NDVC uses hysteresis to minimise the artefacts
generated by rapidly adjusting the DAC gain due to the fluctuation in the environmental noise.

16.2.13 Fixed Gains

There are fixed gain controls at all inputs and outputs to the system so that levels are set according to hardware
constraints and industry standards.

16.2.14 Frequency Enhanced Speech Intelligibility

Frequency enhanced speech intelligibility on the CSR8640 BGA works with the adaptive equalisation module, see
Section 16.2.9, and the NDVC module, see Section 16.2.12, to enhance intelligibility in the presence of noise. This
combination of functions creates higher frequency information, which in the presence of noise, makes it much easier
for the listener to differentiate between consonant pairs, therefore improving intelligibility. This also reduces listener
fatigue as it requires less concentration effort from the user. This can lead to improved dual-tasking performance.

16.3 Music Enhancements

CSR8640 BGA Data Sheet

16.3.1 Audio Decoders
CSR8640 BGA supports:
■ A wide range of standard decoders:
■ SBC
■ MP3
■ AAC
■ Faststream codec:
■ Low-latency
■ No video/lip-sync issues while watching a video or playing games
■ Jitter handling and high quality sample rate matching
■ Low power consumption

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16.3.2 Configurable EQ
The configurable equaliser on the CSR8640 BGA:
■ Each EQ filter contains up to 5 fully tuneable stages of cascaded 2nd order IIR filters per bank
■ Enables compensation for imperfections in loudspeaker performance and frequency adjustments to the
received audio to enhance music brightness
■ Contains tiering for multiple customer presets, e.g. rock, pop, classical, jazz, dance etc.
■ Contains an easy to use GUI, with drag points, see Figure 16.4

CSR8640 BGA Data Sheet

Figure 16.4: Configurable EQ GUI with Drag Points
■ Is configurable with up to 6 switchable bank presets. This enables the headset user to select between the
EQ bank presets through button presses.

16.3.3 Stereo Widening (S3D)

The stereo widening feature on CSR8640 BGA:
■ Simulates loudspeaker listening to provide 3D listening experience
■ Is highly optimised at <1MIPS of the Kalimba DSP
■ Reduces listener fatigue for headphone listening

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16.3.4 Volume Boost
The volume boost feature on the CSR8640 BGA is a dynamic range compander and provides:
■ Additional loudness without clipping
■ Multi-stage compression and expansion
■ Processing modules for dynamic bass boost
■ Easy to use GUI, with drag points, see Figure 16.5

CSR8640 BGA Data Sheet

Figure 16.5: Volume Boost GUI with Drag Points
■ Louder audio output without distortion

16.4 CSR8640 Stereo Headset Development Kit

CSR's audio development kit for the CSR8640 BGA, order code DK-8640-10061-1A, includes a CSR8640 stereo
headset demonstrator board and necessary interface adapters and cables are available. In conjunction with the
CSR8640 stereo headset Configurator tool and other supporting utilities the development kit provides the best
environment for designing audio solutions with the CSR8640 BGA.
Important Note:

The CSR8640 Stereo Headset audio development kit is subject to change and updates, for up-to-date
information see www.csrsupport.com.

Advance Information Page 101 of 110

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17 Ordering Information
Package
Device Order Number
Shipment
Type Size
Method

CSR8640 Stereo VFBGA 68‑ball 5.5 x 5.5 x 1mm

Tape and reel CSR8640A03‑IBBC‑R
Headset (Pb free) 0.5mm pitch

Note:

Until CSR8640A03 reaches Production status, engineering samples order number applies. This is
ES‑CSR8640A02‑IBBC, with no minimum order quantity.
CSR8640 BGA is a ROM-based device where the product code has the form CSR8640Axx. Axx is the specific
ROM-variant, A03 is the ROM-variant for CSR8640 Stereo Headset.
At Production status minimum order quantity is 2kpcs taped and reeled.
Your attention is drawn to Cambridge Silicon Radio Limited’s ("Seller"’s ) standard terms of supply which govern

CSR8640 BGA Data Sheet

the supply of Prototype Products or Engineering Samples and which state in clause 5:
5.1 "Prototype Products" or "Engineering Samples" means any products that have not passed all the stages of
full production acceptance as determined solely by the Seller. The Seller will usually identify which of the Goods
ordered are considered Prototype Products designating them "ES" on the Quotation and any Order for Prototype
Products shall be subject to the special terms contained in this clause 5.
5.2 The Seller has used reasonable efforts to design and build the Prototype Products in accordance with the
relevant specification, but because the testing carried out by the Seller in respect of the Prototype Products is
incomplete, the Seller does not give or enter into any warranties, conditions or other terms in relation to quality
or fitness for purpose of the Prototype Products and/or that the Prototype Products are free from bugs, errors
or omissions.
Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your
local sales account manager or representative.
To contact a CSR representative, email sales@csr.com or go to www.csr.com/contacts.

17.1 CSR8640 Stereo Headset Development Kit Ordering Information

Description Order Number

CSR8640 Stereo Headset Audio Development Kit DK-8640-10061-1A

Advance Information Page 102 of 110

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18 Tape and Reel Information
For tape and reel packing and labelling see IC Packing and Labelling Specification.

18.1 Tape Orientation

Figure 18.1 shows the general orientation of the CSR8640 BGA package in the carrier tape.

Circular Holes
Pin A1 Marker

A≥B

G-TW-0002434.3.2
B

CSR8640 BGA Data Sheet

User Direction of Feed

Figure 18.1: Tape Orientation

18.2 Tape Dimensions

Figure 18.2 shows the dimensions of the tape for the CSR8640 BGA.

Ø 1.5 +0.1/-0.0
8.00 MIN
2.00 ±0.10 SEE NOTE 3 Ø 1.50 MIN
4.00 SEE NOTE 1 1.75 ±0.10
0.30 ±0.05
A

R 0.3 MAX 4.48 B0

7.5 ±0.1
SEE NOTE 3

16.0 ±0.3

A
G-TW-0007442.1.1

K0 R 0.5 TYP

0.66
A0
4.48
SECTION A - A

Figure 18.2: Tape Dimensions

Advance Information Page 103 of 110

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 A0 B0 K0 Unit Notes

1. 10 sprocket hole pitch cumulative tolerance ±0.2.

2. Camber in compliance with EIA 481.
3. Pocket position relative to sprocket hole measured
6.00 6.00 1.50 mm
as true position of pocket, not pocket hole
4. Tolerances, unless noted, 1PL ± 0.2, 2PL ± 0.10
5. Material: PS + C

18.3 Reel Information

CSR8640 BGA Data Sheet

G-TW-0000386.3.2

Figure 18.3: Reel Dimensions

W3
Package Tape A W2
B C D Min N Min W1 Units
Type Width Max Max
Min Max

5.5 x 5.5 x
13.0 16.4
1mm 16 332 1.5 20.2 50 19.1 16.4 19.1 mm
(0.5/-0.2) (3.0/-0.2)
VFBGA

18.4 Moisture Sensitivity Level

CSR8640 BGA is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.

Advance Information Page 104 of 110

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19 Document References
Document Reference, Date

BlueTest User Guide CS-102736-UG

Bluetooth and USB Design Considerations CS-101412-AN

Bluetooth Specification Version 3.0 + HS Version 3.0 + HS [Vol 0 to Vol 5], 21 April 2009

CSR8640 BGA Performance Specification CS-213228-SP

Electrostatic Discharge (ESD) Sensitivity Testing

JESD22-A114F
Human Body Model (HBM)

Electrostatic Discharge (ESD) Sensitivity Testing,

JESD22-A115C
Machine Model (MM)

Field-Induced Charged-Device Model Test Method for

CSR8640 BGA Data Sheet

Electrostatic- Discharge-Withstand Thresholds of JESD22-C101E
Microelectronic Components

IC Packing and Labelling Specification CS-112584-SP

Kalimba Architecture 3 DSP User Guide CS-202067-UG

Lithium Polymer Battery Charger Calibration and

CS-204572-AN
Operation for CSR8670

Moisture / Reflow Sensitivity Classification for

IPC / JEDEC J-STD-020
Nonhermitic Solid State Surface Mount Devices

Optimising BlueCore5-Multimedia ADC Performance

CS-120059-AN
Application Note

Selection of I²C EEPROMS for Use with BlueCore bcore-an-008P

Typical Solder Reflow Profile for Lead-free Device CS-116434-AN

Universal Serial Bus Specification v2.0, 27 April 2000

USB Battery Charging Specification v1.1, 15 April 2009

Advance Information Page 105 of 110

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Terms and Definitions
Term Definition

µ-law Audio companding standard (G.711)

A-law Audio companding standard (G.711)

A2DP Advanced Audio Distribution Profile

AAC Advanced Audio Coding

AC Alternating Current

ACL Asynchronous Connection-oriented

ADC Analogue to Digital Converter

AEC Acoustic Echo Cancellation

AEQ Adaptive EQualiser

CSR8640 BGA Data Sheet

AFC Automatic Frequency Control

AFH Adaptive Frequency Hopping

AG Audio Gateway

AGC Automatic Gain Control

ALU Arithmetic logic unit

AVRCP Audio/Video Remote Control Profile

BCCMD BlueCore Command

BCSP BlueCore Serial Protocol

BEC Bit Error Concealment

BER Bit Error Rate

BFI Bad Frame Indicator

BIST Built-In Self-Test

BlueCore® Group term for CSR’s range of Bluetooth wireless technology ICs

Bluetooth® Set of technologies providing audio and data transfer over short-range radio connections

BMC Burst Mode Controller

CNG Comfort Noise Generation

codec Coder decoder

CRC Cyclic Redundancy Check

CSR Cambridge Silicon Radio

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Term Definition

CTS Clear to Send

CVC Clear Voice Capture

CVSD Continuous Variable Slope Delta Modulation

DAC Digital to Analogue Converter

DC Direct Current

DDS Direct Digital Synthesis

DFU Device Firmware Upgrade

DMA Direct Memory Access

DNL Differential Non Linearity (ADC accuracy parameter)

DSP Digital Signal Processor

DUT Device Under Test

CSR8640 BGA Data Sheet

e.g. exempli gratia, for example

EDR Enhanced Data Rate

EEPROM Electrically Erasable Programmable Read Only Memory

EIA Electronic Industries Alliance

EQ EQualiser

eSCO Extended SCO

ESD Electrostatic Discharge

ESR Equivalent Series Resistance

etc et cetera, and the rest, and so forth

FIR Finite Impulse Response (filter)

FSK Frequency Shift Keying

G.722 An ITU-T standard wideband speech codec operating at 48, 56 and 64 kbps

GCI General Circuit Interface

GSM Global System for Mobile communications

GUI Graphical User Interface

H4DS H4 Deep Sleep

HBM Human Body Model

HCI Host Controller Interface

HFP Hands-Free Profile

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Term Definition

HSP HeadSet Profile

I²C Inter-Integrated Circuit Interface

I²S Inter-Integrated Circuit Sound

i.e. Id est, that is

I/O Input/Output

IC Integrated Circuit

IEEE Institute of Electronic and Electrical Engineers

IF Intermediate Frequency

IIR Infinite Impulse Response (filter)

INL Integral Non Linearity (ADC accuracy parameter)

IPM Intelligent Power Management

CSR8640 BGA Data Sheet

IQ In-Phase and Quadrature

ISDN Integrated Services Digital Network

JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology
Association)

Kalimba An open platform DSP co-processor, enabling support of enhanced audio applications, such
as echo and noise suppression, and file compression / decompression

Kb Kilobit

LC An inductor (L) and capacitor (C) network

LDO Low (voltage) Drop-Out

LED Light-Emitting Diode

LM Link Manager

LNA Low Noise Amplifier

LSB Least Significant Bit (or Byte)

MAC Multiplier and ACcumulator

MAP Message Access Profile

Mb Megabit

MCU MicroController Unit

MEMS Micro Electro Mechanical System

MIPS Million Instructions Per Second

MISO Master In Slave Out

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Term Definition

MLC Multilayer Ceramic

MMU Memory Management Unit

MP3 MPEG-1 audio layer 3

mSBC modified Sub-Band Coding

N/A Not Applicable

NDVC Noise Dependent Volume Control

NSMD Non Solder Mask Defined

PA Power Amplifier

PBAP Phonebook Access Profile

PC Personal Computer

PCB Printed Circuit Board

CSR8640 BGA Data Sheet

PCM Pulse Code Modulation

PIN Personal Identification Number

PIO Parallel Input/Output

PIO Programmable Input/Output, also known as general purpose I/O

PLC Packet Loss Concealment

plc Public Limited Company

PS Key Persistent Store Key

PWM Pulse Width Modulation

RAM Random Access Memory

RC A Resistor and Capacitor network

RF Radio Frequency

RGB Red Green Blue

RISC Reduced Instruction Set Computer

RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive

(2002/95/EC)

ROM Read Only Memory

RSSI Received Signal Strength Indication

RTS Request To Send

RX Receive or Receiver

SBC Sub-Band Coding

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Term Definition

SCL Serial Clock Line

SCO Synchronous Connection-Oriented

SDA Serial Data (line)

SIG (Bluetooth) Special Interest Group

SLC Service Level Connection

SMPS Switch Mode Power Supply

SNR Signal-to-Noise Ratio

S/PDIF Sony/Philips Digital InterFace (also IEC 958 type II, part of IEC-60958). An interface designed
to transfer stereo digital audio signals between various devices and stereo components with
minimal loss.

SPI Serial Peripheral Interface

SPP Serial Port Profile

CSR8640 BGA Data Sheet

TBD To Be Defined

THD+N Total Harmonic Distortion and Noise

TX Transmit or Transmitter

UART Universal Asynchronous Receiver Transmitter

UI User Interface

USB Universal Serial Bus

VCO Voltage Controlled Oscillator

VFBGA Very thin, Fine pitch, Ball Grid Array

VM Virtual Machine

VoIP Voice over Internet Protocol

W-CDMA Wideband Code Division Multiple Access

Wi-Fi® Wireless Fidelity (IEEE 802.11 wireless networking)

WNR Wind Noise Reduction

Advance Information Page 110 of 110

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