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Logic Gates

The electronic circuits for performing logic functions are usually called gates.
Boolean functions can be realized by the logic gates. Corresponding to AND,
OR and NOT operations, we have AND gate, OR gate and NOT gate ( inverting
gate), respectively. These logic gates are called basic logic gates.
Logic gates NAND and NOR derived from the basic logic gates are called
universal logic gates. A universal gate is a gate that can implement any basic
Logic Gates gate or any Boolean function without the need to use any other gate type.
The other gates Exclusive OR (Ex-OR) and Exclusive NOR (Ex-NOR) derived
also from the basic logic gates are called special purpose logic gates.
The gates described so far are basic building blocks of digital circuits/digital
systems, having one or more inputs and single output.
These gates can be realized by various types of switching devices such as
electro-mechanical relays, vacuum tubes, semiconductor diodes, transistors
(bipolar and unipolar), tunnel diodes, etc. Now, logic gates based on electro-
mechanical relays are not used in high speed digital computer circuits
because of their slow speed and mechanical moving parts. In most of the
cases, high speed switching devices such as semiconductor diodes and
transistors (bipolar and unipolar) are used.

Logic Gates Logic Gates

Logic gate circuits can be classified in two ways. One way of classifying the The second criterion classify the logic gates based on logic families. A
gates depends upon the operation/logic function, the gate does on its inputs, group of compatible ICs with the same logic levels and supply voltages for
while the other way of classifying the gate circuits depends upon its performing various logic functions have been fabricated using a specific
electronic-circuits structure irrespective of the logic function it performs. circuit configuration which is referred to as a logic family. These are as
There are three types of logic gates based on the first criterion. These are: follows:
 Basic logic gates 1. Bipolar Logic Families
 Universal logic gates The main elements of a bipolar IC are resistors, diodes (which are also
 Special purpose logic gates capacitors) and transistors. Basically, there are two types of operations in
bipolar ICs:
Logic Gates
(a) Saturated, and
(b) Non-saturated.
In saturated logic, the transistors in the IC are driven into saturation,
Basic Logic Universal Logic Special purpose Whereas in the case of non-saturated logic, the transistors are not driven
Gates Gates Logic Gates into saturation.
The saturated bipolar logic families are:
AND OR NOT NAND NOR Ex-OR Ex-NOR (i) Diode Logic (DL),
gate gate gate gate gate gate gate

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Logic Gates Logic Gates

(ii) Direct-Coupled Transistor Logic (DCTL), While in PMOS only P-channel MOSFETs are used and in NMOS only n-
(iii) Resistor-Transistor Logic (RTL), channel MOSFETs are used, in complementary MOS (CMOS), both p- and n-
(iv) Diode-Transistor Logic (DTL), channel MOSFETs are employed and are fabricated on the same silicon chip.
(v) Integrated-Injection Logic (I2L),
(vi) High-Threshold Logic (HTL), and 3. BiCMOS Logic Family
(vii) Transistor-Transistor Logic (TTL).
BiCMOS logic circuits use CMOS devices for input and logic operations and
The non-saturated bipolar logic families are: bipolar devices for output.
(i) Schottky TTL and Characteristics of Digital ICs
(ii) Emitter-Coupled Logic (ECL).
Selection of a particular design out of the various logic families, which are
2. Unipolar Logic Families simply known as digital ICs , depends upon many factors. These factors are
MOS devices are unipolar devices and only MOSFETs are employed in called characteristics of digital ICs and are listed below:
MOS logic circuits.
 Speed of operation,  Power dissipation
The MOS logic families are:  Fan-in,  Current and voltage parameters,
(i) PMOS,  Fan-out,  Operating temperature range,
(ii) NMOS, and  Noise immunity,  Power supply requirements, and
(iii) CMOS  Figure of merit,  Flexibilities available.

Logic Gates Logic Gates

Speed of Operation making a transition from the LOW state to the HIGH state. The propagation
delay time of the logic gate is taken as the average of these two delay times.
The speed of a digital circuit is characterized by the rise time of the output
step when an input step is given. It is specified in terms of the propagation Fan-In
delay time. The input and output waveforms of a logic gate are shown in The fan-in is the number of identical inputs the logic circuits or gates can
Fig. 3.1. handle.
Fan-Out
50% The fan-out is the number of identical logic circuits or gates the output can
Input drive without affecting the performance of the gate seriously. Simply, this is
tpHL tpLH the number of similar gates which can be driven by a gate. High fan-output
Output is advantageous because it reduces the need for additional drivers to drive
50% more gates.

Noise Immunity
Fig. 3.1 Input and output voltage waveforms to define propagation delay Stray electric and magnetic fields can induce voltages on the connecting
wires between logic circuits. These unwanted, spurious signals are called
The delay times are measured between the 50% voltage levels of input and noise and can sometimes cause the voltage at the input to a logic circuit to
output waveforms. There are two delay times: tpHL, when the output goes drop below VIH(min) or rise above VIL(max), which could produce undesired
from the HIGH state to the LOW state and tpLH, corresponding to the output or unpredictable operation. The noise immunity of a logic circuit refers to

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Logic Gates Logic Gates

Noise Immunity Figure 3.2 (a) is a diagram showing the range of voltages that can occur at a
the circuit’s ability to tolerate noise without causing spurious changes in the logic circuit output.
output voltage. A quantitative measure of noise immunity is called noise  Any voltages greater than VOH(min) are considered a logic 1, and any
margin and is illustrated in Fig. 3.2. voltages lower than VOL(max) are considered a logic 0.
 Voltages in the indeterminate/disallowed/forbidden range should not
Logic
appear at a logic circuit output under normal conditions.
Logic
1 Figure 3.2 (b) shows the voltage requirements at a logic circuit input.
1
VOH(min)
VNH
VIH(min)  The logic circuit responds to any input voltage greater than VIH(min) as

Voltage
Disallowed or
Voltage

indeterminate Indeterminate a logic 1, and it responds to voltages lower than VIL(max) as a logic 0.
range range
VNL
VIL(max)  Voltages in the indeterminate/disallowed/forbidden range produce an
VOL(max) unpredictable response and should not be used.
Logic
Logic
0
0 The high-state noise margin VNH is defined as

Output voltage Input voltage VNH = VOH(min) – VIH(min)

ranges requirements That is, VNH is the difference between the lowest possible HIGH output and
(a) (b) the minimum input voltage required for a HIGH. When a HIGH logic output
is driving a logic-circuit input, any negative noise spike greater than VNH
Fig. 3.2 DC noise margins. appearing on the signal line can cause the voltage to drop the disallowed/

Logic Gates Logic Gates

indeterminate/forbidden range, where unpredictable operation can occur.  required to produce a change in the circuit output. This means that a
The low-state noise margin VNL is defined as logic circuit can effectively tolerate a large noise amplitude if the noise
is of a very short duration. This is referred to as ac noise margin and is
VNL = VIL(max) – VOL(max) substantially greater than the dc noise margin.
and it is the difference between the largest possible LOW output and the
Figure of Merit/Speed-Power Product
maximum input voltage required for a LOW. When a LOW logic output is
driving a logic input, any positive noise spikes greater than VNL can cause The figure of merit of a digital IC is defined as the product of speed and
the voltage to rise into the indeterminate/disallowed/forbidden range. power. The speed is specified in terms of propagation delay time expressed
in nanoseconds.
The noise margins discussed so far are referred to as d.c. noise margins.
Figure of merit = Propagation delay time (ns) x Power (mW)
Strictly speaking, the noise is generally thought of as an a.c. signal with
amplitude and pulse width. It is specified in pico joules (ns x mW). A low value of speed-power product
 For high speed ICs, a pulse width of a few microseconds is extremely is desirable.
long in comparison to the propagation delay time of the circuit and Power Dissipation
therefore, may be treated as d.c. as far as the response of the logic This is the amount of power dissipated in an IC. It is determined by the
circuit is concerned. current, Icc, that it draws from the Vcc supply, and is given by Vcc x Icc. Icc is
 As the noise pulse width decreases and approaches the propagation the average value of Icc(0) and Icc(1). This power is specified in milliwatts
delay time of the circuit, the pulse duration is too short for the circuit and is known as static power dissipation, i.e., the power consumed by the
to respond. Under this condition, a large pulse amplitude would be circuit when input signals are not changing.

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Logic Gates Logic Gates

Current and Voltage Parameters Low-Level Input Current, IIL: This is the current following into (taken as
The following currents and voltages are specified which are very useful in positive) or out of (taken as negative) an input, when a maximum Low-
the design of digital systems. Level Input Voltage, VIL(max) equal to the maximum Low-Level Output
Voltage, VOL(max) specified for the logic family is applied.
High-Level Input Voltage, VIH(min): The minimum voltage level required for
a logical 1 at an input. Any voltage below this level will not be accepted as High-Level Output Current, IOH: This is the current following out of an
a HIGH by the logic circuit. output when the input conditions are such that the output is in the logical
1 (High) state under specified load conditions. It informs us about the
Low-Level Input Voltage, VIL(max): The maximum voltage level required for current sourcing capability of the output. The magnitude of IOH determines
a logic 0 at an input. Any voltage above this level will not be accepted as a the number of inputs the logic function can drive when its output is in the
LOW by the logic circuit. logical 1 (High) state.
High-Level Output Voltage, VOH(min): The minimum voltage level at a logic
circuit output in the logical 1 state under defined load conditions. HIGH
Low-Level Output Voltage, VOL(max): The maximum voltage level at a logic IOH IIH
circuit output in the logical 0 state under defined load conditions.
+ +
VOH VIH
High-Level Input Current, IIH: This is the current following into (taken as - -
positive) or out of (taken as negative) an input, when a minimum High-
Level Input Voltage, VIH(min) equal to the minimum High-Level Output Logic ‘0’
Voltage, VOH(min) specified for the logic family is applied.
(a)

Logic Gates Logic Gates

Note:
+5 V (Logic ‘1’)
LOW  The actual current directions may be opposite to those shown in Fig. 3.3,
IOL IIL depending on the logic family.
 Conventional current flow is considered i.e., current flow from higher
+ +
VOL VIL potential to lower potential.
- -
 Current flowing into a node or device is considered positive, and current
flowing out of a node or device is considered negative

(b) Operating Temperature Range

Fig. 3.3 Currents and voltages in the two logic states. The temperature range in which an IC function properly must be known. The
accepted temperature ranges are: 0 to +70oC for consumer and industrial
Low-Level Output Current, IOL: This is the current following into an output applications and -55oC to +125oC for military purposes.
when the input conditions are such that the output is in the logical 0 (Low) Power Supply Requirements
state under specified load conditions. It informs us about the current
Every IC requires a certain amount of electrical power to operate. The amo-
sinking capability of the output. The magnitude of IOL determines the
unt of power that an IC requires is determined by the current, ICC (or IDD), that
number of inputs the logic function can drive when its output is in the
it draws from the VCC (or VDD) supply, and the actual power is the product ICC
logical 0 (Low) state.
x VCC. Here VCC stands for TTL and VDD stands for MOS devices.

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Logic Gates Logic Gates

Flexibility Available Logic

Various flexibilities are available in different IC logic families and these In the case of digital circuit/switching circuit, logic means that the circuit
must be considered while selecting a logic family for a particular job. Some works using only two voltage levels – high and low (or on and off or true
of the flexibilities available are: and false). This is immediately related to the binary number system by
 The breadth of the series: Type of different logic functions in the series. assigning generally high/on/true = 1 and low/off/false = 0. These voltage
levels are sometimes called logic levels and digital circuits/switching
 Popularity of the series: The cost of manufacturing depends upon the circuits use only these logic levels to represent information. There are
number of ICs manufactured. When a large number of ICs of one type are two types of logic systems: Positive Logic and Negative Logic.
manufactured, the cost per function will be very small and it will be easily
available because of multiple sources.  Positive Logic: In the positive logic, the high voltage level (or on/true)
is used to represent the logic 1 and the low voltage level (or off/false) is
 Wired-logic capability: The outputs can be connected together to perform
used to represent the logic 0.
additional logic without any extra hardware.
 Negative Logic: In the negative logic, the high voltage level (or on/true)
 Availability of complement output: This eliminates the need for additional represents the logic 0 and the low voltage level (or off/false) represents
inverters. the logic 1.
 Type of output: Passive pull-up, active pull-up, open-collector/drain, and
tristate. The convention is shown in table 3.1. Positive logic is more common and
will be used in all of my lectures on digital electronics.

Logic Gates Logic Gates

Table 3.1 Positive and Negative Logic Example-3.1 Implement the following Boolean function using diode logic
Positive Logic Negative Logic gates:
High level 1 0 𝒇 𝒙𝟏 , 𝒙𝟐 , 𝒙𝟑 , 𝒙𝟒 , 𝒙𝟓 = 𝒙𝟏 𝒙𝟐 𝒙𝟑 + 𝒙𝟒 𝒙𝟓
Low level 0 1

Diode Logic (DL) Gates Advantages of DL

 Simple, cheap, and robust.
𝒙𝟏 VS (+5V)
 Integration with other components is easy.

R Disadvantages of DL
𝒙𝟐 𝒇(𝒙𝟏 + 𝒙𝟐 )
 Loss of voltage level definiteness as more and more gates are cascaded.
𝒙𝟏 𝒇(𝒙𝟏, 𝒙𝟐)  Loading of the driving source.
R
 Low speed.
(a) 𝒙𝟐 (b)  Fan-out is restricted.

Fig. 3.4 Diode logic gates: (a) A two-input OR gate; (b) A two-input AND gate.

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Logic Gates Logic Gates

Direct Coupled Transistor Logic (DCTL) Gate If any of the input variable is at logical value 1, the
+VCC base current will be supplied to the transistor and
+VCC
collector current will flow through RC, bringing the
collector voltage to the saturation voltage VCE (Sat).
RC
RC
𝒇 = (𝒙𝟏 . 𝒙𝟐 . 𝒙𝟑 )′
𝒇 = (𝒙𝟏 + 𝒙𝟐 + 𝒙𝟑 )′
T1 T2 T3
𝒙𝟏 T1
𝒙𝟏 Fig. 3.6 shows a DCTL-NAND gate. In this circuit, all
transistors are connected in series and only when all
three transistors are conducting, current can flow th-
rough, RC. Since the emitter of the transistors are not
𝒙𝟐 T2 connected together, the base voltage required for co-
𝒙𝟐
nduction of each transistor is different. The output
𝒙𝟐 voltage, when all three inputs are high, is 3 times VCE
Fig. 3.5. A 3 input DCTL – NOR gate (Sat).
T3
𝒙𝟑
The DCTL logic circuits are very simple and require fewer components. In
the DCTL- NOR gate circuit shown in Fig. 3.5, three transistors share a
common load resistor.
Fig. 3.6. A 3 input DCTL- NAND gate

Logic Gates Logic Gates

The DCTL is simple but it has two serious drawbacks namely, (1) Base-current
hogging and (2) Low voltage-noise-margin. The first trouble exists due to the
variation in input characteristics of different transistors as illustrated in Fig.3.7
for a 3 input NOR gate of Fig. 3.5. The non-linearity of the input characteristic
causes imbalance in the distribution of the available drive current. When two
or more transistors are fed from the
output, the transistor with lowest input IB
impedance tends to take more current T1 T2 T3
at the expense of others. This phenom-
enon known as base current hogging
prevents the other transistors from tur-
ning on properly. The DCTL logic circu- IB1
its, therefore, have low fan-out capabil-
ity. IB2

IB3

VBE Preceding A 3 input DCTL-NOR gate Next stage

stage
Fig. 3.7. Base current hogging. Fig. 3.8. DCTL - NOR gate with fan-in of 3 and fan-out of 2.

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Logic Gates Logic Gates

To understand voltage-noise-margin for the DCTL circuits, consider a DCTL- Direct Coupled Transistor Logic (DCTL) circuits are also called as Integrated-
NOR gate of Fig. 3.8 with a fan-in of 3 and fan-out of 2. Injection Logic (I2L) circuits. It uses no biasing and loading resisters at all!
 Assume that the input 𝒙𝟏 to the gate is in the ‘0’ state. This low voltage Resistors require lot of power and space on an IC chip. Hence, their elimina-
comes from a preceding stage with a saturated transistor, 𝒙𝟏 = 𝑽𝑪𝑬 (sat) ≃ tion results in higher density circuits operating at much reduced power.
𝟎. 𝟐 V. Since cut in base voltage of a transistor is 𝑽𝜸 ≃ 𝟎. 𝟓 V, transistor T1 Because of its high speed and less power dissipation, it is used in large
will conduct very little. The noise margin in this case is only (0.5 - 0.2) = computers. Such circuits are also used where high packing density is of
prime consideration as in digital wrist watches. I2L chips are capable of
0.3 V. This noise margin further reduces with temperature and transistor
can be switched on by noise only. microwatt power dissipation yet can provide high currents when necessary
to drive LED displays. Another feature of I2L is that it is easy to fabricate.
 Now if 𝒙𝟐 and 𝒙𝟑 are also in ‘0’ state, the output of the gate will be high
and the transistors T4 and T5 will be saturated. The output 𝒇 of the NOR Advantages of DCTL Disadvantages of DCTL
gate will be clamped at 𝑽𝑩𝑬 (sat) ≃ 0.8 V which corresponds to ‘1’ state.
• It is a simple circuit and requires • Base-current hogging
Therefore in a DCTL gate, the low state is about 0.2 V and the high state is fewer components. • Low voltage-noise-margin
only about 0.8 V. • Power dissipation is low.
• It is easy to fabricate onto integ-
rated circuits.
• Switching speed is fast.
• It is more economical.

Logic Gates Logic Gates

Resistor-Transistor Logic (RTL) Gate Some of the shortcomings of DCTL circuits can be reduced by connecting a
series resistor in each base leg of the transistor and the resulting circuits are
+VCC called Resistor-Transistor Logic (RTL) circuits. The use of series resistances
minimizes the variations in the input impedances of different transistors and
problem of current hogging is reduced.
RC
A three-input RTL NOR gate is shown in Fig. 3.9. If any input is high, then the
𝑓 = (𝑥 + 𝑥 + 𝑥 )′ corresponding transistor is driven into saturation and the output is low, 𝒇 =
Rb T1 T2 T3
𝑽𝑪𝑬 (sat) ≃ 𝟎.2 V. When all inputs are law, then all transistors are cut off by
𝒙𝟏 𝑽𝜸 − 𝑽𝑪𝑬 (sat) = 𝟎. 𝟓 − 𝟎. 𝟐 = 𝟎. 𝟑 V and the output is high. In this case, the
noise margin is still low (≃ 𝟎. 𝟑 𝑽). The circuit therefore work as a NOR gate.
The output of the gate in 1 state depends upon the fan-out. The expression
Rb
that relates the 1 sate output with the fan-out is
𝒙𝟐
𝑹𝒃
Rb 𝒏 𝑹𝑪
𝑽 𝟏 = 𝑽𝑪𝑪 + 𝑽𝑩𝑬 𝒔𝒂𝒕 ⋯ ⋯ ⋯ ⋯ (𝟑. 𝟏)
𝒙𝟑 𝑹𝒃 𝑹𝒃
𝒏 + 𝑹𝑪 𝒏 + 𝑹𝑪
Fig. 3.9 A three-input RTL – NOR gate 𝑽𝑪𝑪 𝒏
𝑽 𝟏 = + 𝑽𝑩𝑬 (𝒔𝒂𝒕) 𝒊𝒇 𝑹𝒃 = 𝑹𝑪 ⋯ ⋯ ⋯ (𝟑. 𝟐)
𝟏+𝒏 𝟏+𝒏

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Logic Gates Logic Gates

The base current for each transistor of the driven circuits i.e. load transistor
is
𝑽𝑪𝑪 − 𝑽𝑩𝑬 (𝒔𝒂𝒕) 𝟏
𝑰𝑩 = ⋯ ⋯ ⋯ (𝟑. 𝟑)
𝑹 𝒏
𝑹𝑪 + 𝒃
𝒏
The collector current for the transistor of the driven circuits i.e. load transis-
tor is
𝑽𝑪𝑪 − 𝑽𝑪𝑬 (𝒔𝒂𝒕)
𝑰𝑪 𝒔𝒂𝒕 = ⋯ ⋯ ⋯ (𝟑. 𝟒)
𝑹𝑪

𝑽𝑪𝑪

𝑹𝑪
V(1) V(1)
𝟏 𝟓
For a fan-out of 5, from (3.2), V(1) is obtained as 𝑽𝑪𝑪 + 𝑽𝑩𝑬 (sat). With 𝑽𝑪𝑪 = 𝑹𝒃 𝑹𝒃 𝑹𝒃 𝑹𝒃
𝟔 𝟔
5 volts and 𝑽𝑩𝑬 (sat) = 0.8 volt, V(1) = (0.833 + 0.666) ≈ 1.50 V. If this voltage is 𝒏 ...……
lowered by some undesired dc noise of 0.2 V, it becomes 1.30 V. This voltage 𝑽𝑩𝑬 (𝒔𝒂𝒕) 𝑽𝑩𝑬 (𝒔𝒂𝒕) 𝑽𝑩𝑬 (𝒔𝒂𝒕) 𝑽𝑩𝑬 (𝒔𝒂𝒕)
does not guarantee reliable operation, because it can not supply enough
current to saturate the transistors of the driven circuits.

Logic Gates Logic Gates

The value of fan-out, 𝒏 must satisfy the following relation,

Therefore, the RTL circuits should be used with care after determining its
𝒉𝑭𝑬 𝑰𝑩 ≥ 𝑰𝑪 (𝒔𝒂𝒕) fan-out and also they have low noise margins of about 0.3V.

For 𝒏 = 𝟓, 𝑽𝑪𝑪 = 𝟓𝑽, 𝑽𝑪𝑬(𝒔𝒂𝒕) = 𝟎. 𝟐𝑽, 𝑹𝑪 = 𝟔𝟒𝟎 Ω, 𝑹𝒃 = 𝟒𝟓𝟎 Ω, and 𝑽𝑩𝑬(𝒔𝒂𝒕) =

𝟎. 𝟖𝑽, 𝑰𝑩 and 𝑰𝑪 𝒔𝒂𝒕 currents will be 1.15 mA and 7.5 mA, respectively. Advantages of RTL Disadvantages of RTL
Therefore, 𝒉𝑭𝑬 must be greater than 7. Now, using eqn. (3.1), the voltage • It is a simple digital circuit and • Switching speed is low due
V(1) is found 𝟏. 𝟑𝟐𝑽. requires fewer transistors to build to base resistors, 𝑹𝒃.
For 𝒉𝑭𝑬 = 𝟏𝟎, the total base current required for load transistors to be driven logic circuit than other logic famil- • Power dissipation is high
into saturation will be ies. due to the base resistors, 𝑹𝒃
𝟕. 𝟓 • Operation of this circuit is very and collector resistors, 𝑹𝑪.
𝟓× 𝒎𝑨 = 𝟑. 𝟕𝟓 𝒎𝑨
𝟏𝟎 simple • Low voltage-noise-margin
and the corresponding V(1) must be • It is also more economical.
𝑩𝒂𝒔𝒆 𝒄𝒖𝒓𝒓𝒆𝒏𝒕 𝒊𝒏 𝒆𝒂𝒄𝒉 𝒍𝒐𝒂𝒅 𝒕𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 × Resistor-Capacitor-Transistor Logic (RCTL) Gate
𝑹𝒆𝒔𝒊𝒔𝒕𝒐𝒓 𝒊𝒏 𝒆𝒂𝒄𝒉 𝒃𝒂𝒔𝒆 𝒍𝒆𝒈 𝒐𝒇 𝒍𝒐𝒂𝒅 𝒕𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 + 𝑽𝑩𝑬 (𝒔𝒂𝒕).
The switching time of a transistor depends on the rate at which the source
𝟕. 𝟓 𝟑. 𝟕𝟓 can supply sufficient current to charge the input capacitance of the
𝒐𝒓 𝒎𝑨 × 𝑹𝒃 + 𝟎. 𝟖𝑽 = 𝟎. 𝟕𝟓 𝒎𝑨 × 𝟒𝟓𝟎𝜴 + 𝟎. 𝟖𝑽 = 𝟏. 𝟏𝟒𝑽. transistor. To improve the switching speed, a capacitor in shunt with 𝑹𝒃 is
𝟏𝟎 𝟓
used as indicated in Fig. 3.10 resulting RCTL-NOR logic gate. The operation
Therefore , the noise margin for logic 1 level is 𝟏. 𝟑𝟐 − 𝟏. 𝟏𝟒 𝑽 = 𝟎. 𝟏𝟖𝑽. is same as RTL-NOR gate.

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Resistor-Capacitor-Transistor Logic (RCTL) Gate Diode-Transistor Logic (DTL) Gate

+VCC
DTL is the combination of Diode Logic (DL) and Resistor-Capacitor-Transistor
Logic (RCTL). Diode logic has some disadvantages, specially (i) loss of volta-
RC ge level definiteness as more and more gates are cascaded and (ii) loading of
C1 𝒇 = (𝒙𝟏 + 𝒙𝟐 + 𝒙𝟑 )′ the driving source. A transistor inverter (NOT) gate is, therefore, placed at the
T1 T2 T3 output of the diode gate, which provides isolation and increased driving capa-
𝒙𝟏 bilities.
Rb Fig. 3.11 (a) and (b) show the circuits of DTL-NOR and DTL-NAND gates, resp-
C1 ectively. Fan-in of DTL gates are similar to those of diode logic, while fan-out is
limited by transistor current.
The operation of the inverter can be understood by assuming that the input 𝒗𝟏
𝒙𝟐 to the inverter takes on either of two values − low voltage corresponding to 0
Rb Addition of capacitance C1 permits rapid
charging during the turn on of the tran- level 𝑽(𝟎) and high voltage corresponding to 1 level 𝑽(𝟏). When the input is
C1 sistor. The rise time of the pulse is impro- 𝑽(𝟎), then the circuit parameters are such that the transistor T1 is off and
ved due to cancellation of the dominant hence the output 𝒇 = VCC= 𝑽(𝟏). If 𝒗𝟏 = 𝑽(𝟏), the circuit parameters are chosen
pole of the transistor input impedance by such that the transistor is saturated due to the base current and hence 𝒇 =
𝒙𝟑 𝑽𝑪𝑬 (𝒔𝒂𝒕) = 𝑽(𝟎).
Rb the zero introduced by RbC1.
Fig. 3.10 A three-input RCTL-NOR gate

Logic Gates Logic Gates

DTL-NOR Gate DTL-NAND Gate

+VCC +VCC
+V
D D
𝒙𝟏 RC 𝒙𝟏 RC
C 𝒇 = (𝒙𝟏 + 𝒙𝟐 + 𝒙𝟑 )′ R1 C 𝒇 = (𝒙𝟏 𝒙𝟐 𝒙𝟑 )′
D D
𝒗𝟏 𝒗𝒃 𝒗𝒃
𝒙𝟐 𝒙𝟐
R 𝒗𝟏 R
D D
𝒙𝟑 R1 Rb Rb
𝒙𝟑

-VBB - VBB
OR Gate NOT (Inverter) Gate AND Gate NOT (Inverter) Gate

Fig. 3.11 (a) A three-input DTL-NOR gate Fig. 3.11 (b) A three-input DTL-NAND gate

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Logic Gates Logic Gates

Design of Inverter Circuit If 𝑽𝑪𝑪 = 𝟏𝟐𝑽, −𝑽𝑩𝑩 = −𝟏𝟐𝑽, 𝑽𝑪𝑬(𝒔𝒂𝒕) = 𝟎. 𝟐𝑽, 𝑰𝑪 = 𝟓 𝒎𝑨, (𝒉𝑭𝑬)min = 𝟑𝟎, and
The inverter circuit in Fig. 3.11 can be designed easily by following method. 𝑽𝑩𝑬(𝒔𝒂𝒕) = 𝟎. 𝟖𝑽, then component values will be
Assuming a collector current of 𝑰𝑪 (𝒎𝑨), value of 𝑹𝑪 is given by 𝑹𝑪 = 𝟐. 𝟐 𝑲Ω, 𝑹 = 𝟏𝟓 𝑲Ω, and 𝑹𝒃 = 𝟏𝟎𝟎 𝑲Ω.
𝑽𝑪𝑪 − 𝑽𝑪𝑬 (𝒔𝒂𝒕) The capacitor C across R has been added to improve the transient response
𝑹𝑪 = 𝑲𝛀 ⋯ ⋯ ⋯ ⋯ (𝟑. 𝟑)
𝑰𝑪 (𝒎𝑨) of the gate. It helps to remove the charge carriers stored in the base when
the signal changes the logical state abruptly. The value of C depends upon
For 𝒗𝟏 = 𝑽(𝟎) ≃ 𝟎 volt, 𝒗𝒃 should be negative so that transistor T1 is cut off. the transistor used, the order of magnitude being about 100 pF.
Or
𝑽𝑩𝑩
𝑹 > 𝟎 ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ (𝟑. 𝟒) For the integrated circuit implementation of DTL gates some modification is
𝑹 + 𝑹𝒃 necessary because the fabrication of capacitance and large value of resista-
For 𝒗𝟏 = 𝑽 𝟏 = 𝟏𝟐 volts, the transistor T1 should be saturated. nces are uneconomical. The transistors and diode can be constructed inexp-
𝑰𝑪 ensively. The circuit of DTL-NAND gate using only one power supply of 5
𝑰𝑩 > ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ ⋯ (𝟑. 𝟓) volts suitable for IC construction is shown in Fig. 3.12.
𝒉𝑭𝑬 𝒎𝒊𝒏
If at least one of the inputs is low, the diode D connected to that input cond-
𝒉𝑭𝑬 𝒎𝒊𝒏 is the minimum value of the 𝒉𝑭𝑬 for the transistor and 𝑰𝑩 is given by
ucts and the voltage 𝒗𝟏 is low and hence the diodes D1 and D2 are non-
𝑽 𝟏 − 𝑽𝑩𝑬 (𝒔𝒂𝒕) 𝑽𝑩𝑬 𝒔𝒂𝒕 + 𝑽𝑩𝑩 conducting. As a result, the base current to the transistor, T1 is zero and
𝑰𝑩 = − ⋯ ⋯ (𝟑. 𝟔)
𝑹 𝑹𝒃 hence the T1 is off. Therefore, the output 𝒇 = 𝑽(𝟏).

Logic Gates Logic Gates

If all the inputs are high, then all the diodes are reverse biased and hence Two diodes D1 and D2 are used to increase the noise-margin of the gate. This
𝒗𝟏 = 𝑽(𝟏). Thus the base current flows into the transistor T1 which turns can be explained as follows:
the transistor into saturation. As a result, the output 𝒇 = 𝑽(𝟎). The circuit, If at least one input is at V(0), then 𝒗𝟏 = 𝑽𝑪𝑬(𝒔𝒂𝒕) + 𝟎. 𝟕𝑽 = 𝟎. 𝟐𝑽 + 𝟎. 𝟕𝑽 = 𝟎. 𝟗𝑽,
therefore, works as a NAND gate. where 0.7V is the drop across the conducting diode. Now, if only one diode, D1
is used, then 𝑽𝑩𝑬 = 𝟎. 𝟗𝑽 − 𝟎. 𝟔 𝑽 = 𝟎. 𝟑𝑽, where 𝟎. 𝟔 𝑽 represents the cutin
+VCC voltage of the diode, D1. Since the cutin base voltage of the transistor is 0.5V,
the transistor is cut off and the noise margin is only (𝟎. 𝟓 − 𝟎. 𝟑)𝑽 = 𝟎. 𝟐𝑽.
D However, if two diodes D1 and D2 are used, a voltage is of (𝟎. 𝟓 + 𝟐 × 𝟎. 𝟕) =
𝟏. 𝟗𝑽 is required for the diodes and since 𝑽𝟏 is 𝟎. 𝟗𝑽, the transistor is well cut
𝒙𝟏 RC
R1 off.
𝒇 = (𝒙𝟏 𝒙𝟐 𝒙𝟑 )′ +VCC +VCC
D D1 D2
𝒗𝒃
𝒙𝟐 𝒗𝟏
D RC D RC
R1 R1 𝒇
Rb 𝒙𝟏
D D1 D2 D1 D2 𝒗
𝒗𝒃 𝒃
𝒙𝟑 VCE 𝒗𝟏 VCE
D 𝒗𝟏 D
𝒙𝟐 VBE Rb VBE
Rb

Fig. 3.12 DTL-NAND gate for IC construction. Previous Stage Next Stage

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Logic Gates Logic Gates

Advantages of DTL Transistor-Transistor Logic

• The switching speed of DTL is faster as compared to RTL because the
signal/current passes through the low forward resistance of the diodes
to the transistor.
• The use of diodes within DTL circuits makes them cheaper because the +V1
fabrication of diodes and transistor on ICs is simpler as compared to
resistors and capacitors. IB R1
• Power loss within DTL circuits is very low. +VCC
• DTL circuits have faster switching speed.
• It has greater fan-out and improved noise margins as compared to RTL. T1 T2 T3 RC
𝒇 𝒙𝟏 , 𝒙𝟐 , 𝒙𝟑 ′
Disadvantages of DTL T4
• DTL is somewhat more complex than RTL. 𝒙𝟏
• It has low operating speed as compared to TTL. 𝒙𝟐
• It has a very large gate propagation delay. 𝒙𝟑
• It’s noise margin is still poor as compared to TTL.

Logic Gates Logic Gates

Multiple Emitter Transistor Logic +VCC

R2 R3
R1

+V +VCC
+V +VCC T3
T1
R1 RC
R1 𝒙𝟏 T2 D
RC 𝒇
T1 𝒙𝟐 𝒇 = (𝒙𝟏 .𝒙𝟐 .𝒙𝟑 )′
𝒙𝟑
T2
𝒙𝟏 T2
𝒙𝟐 T4
𝒙𝟑
R4
T1

Fig. 14 A practical METL circuit.

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Logic Gates Logic Gates

VCC = +5V VCC = +5V

R1 R2 R4 R1 R2 R4

T3 T3

OFF ON

OFF T2 OFF D4 T2
D4
𝒙𝟏 = +𝟓𝑽 D 𝒙𝟏 = +𝟓𝑽 D
ON OFF
D1 D1
ON OFF
T4 + T4 +
OFF OFF
ON OFF
𝒙𝟐 = +𝟓𝑽 + 𝑽𝑶𝑳 ≤ 𝟎. 𝟒𝑽 𝒙𝟐 = +𝟓𝑽 𝑽𝑶𝑯 ≥ 𝟐. 𝟒𝑽
D2 R3 0.7 V D2 R3
-
- -
OFF ON
𝒙𝟑 = +𝟓𝑽 𝒙𝟑
D3 D3
𝑰𝑰𝑯 = 𝟏𝟎𝝁𝑨 (typical) 𝑰𝑰𝑳 = 𝟏. 𝟏𝒎𝑨 (typical)

Logic Gates Logic Gates

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+VCC
Rb

RC Rb +VCC
V(1)
Rb T1 T2 T3 ⁞
⁞ RC
⁞
Rb
Rb

Rb

T4
T1 T2 T3
𝒙𝟏

𝒙𝟐

T5

𝒙𝟑

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