Digital System Design
Lecture # 6
Introduction to Verilog
ENGR. DR. MUHAMMAD AQEEL ASLAM
ASSISTANT PROFESSOR
SCHOOL OF ENGINEERING AND APPLIED SCIENCES
ELECTRICAL ENGINEERING DEPARTMENT
GIFT UNIVERSITY
GUJRANWALA
2
Operators in Verilog
Shift Replication
Logical Concatenation
Conditional Equality
Negation Unary Reduction
Relational Bit-wise
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Shift Operator
The left shift operator (<<)
shifts the left operand left by module shift;
the number of bit positions
initial begin
specified by left by the right
operand. $display (8’b00011000 << 2); // 01100000
The right shift operator (>>) $display (8’b00011000 >> 3); // 00000011
shifts the left operand right end
by the number of bit
endmodule
positions specified by the
right operand
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Logical Operator
module logical_block;
Logical operators (&&,
initial begin
||) produce a scalar
$display (2’b00 && 2’b10); // 0
value (0 1 or X) (0, 1, or $display (2’b01 && 2’b10); // 1
X). $display (2’b00 || 2’b00); // 0
$display (2’b01 || 2’b00); // 1 71
$display (2 b01 || 2 b00); // 1
$display (2’b00 && 2’b1x); // x
$display (2’b1z && 2’b10); // x
end
endmodule
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Conditional Operator
The conditional operator (?)
Also called ternary operator
Must have 3 operands.
It selects from two operands, based on a third
Syntax:
<conditional_expression> ? <conditional_expression> : <false_expression>
It can be thought of as if-else statement.
“if (conditional_expression) LHS = true_expression; else LHS = false expression;”
An unknown conditional expression can still produce a
known value if all possible selections are identical.
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Conditional operator
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Ternary Operator
Objective: Write a module for a 8 to 1 mux.
Specification:
module 8to1(in0,in1,in2,in3,in4,in5,in6,in7,select, out) ;
input [2:0] select;
input in0,in1,in2,in3,in4,in5,in6,in7;
output out;
endmodule
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Other Operators
Negation operator:
(!) logical
(~) bitwise
Reduces an operand to its logical inverse.
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Other Operators
Relational Operators
Less than (<),
Less than or equal to (<=),
Greater than or equal to (>=),
Greater than (>).
Example: if (A >= 2’b11) then B = 1’b1;
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Operators: Replication
Replication operator
Replicates an expression a fixed number of times
to form a new vector quantity.
({n{}})
Example
regA = 2’b11;
bus = {4{regA}}; // bus = 11111111
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Operators: Concatenation
Concatenation operator
Allows you to select bits from different vectors to
join then into a new vector.
{} concatenation
Example
new_vector[8:0] = {regA[4:2],regB[2:1],1’b0,regC[2:0]};
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Other operators
Logical equality(==) operator
Evaluates to be true if LHS is equal to the RHS.
Logical equality(==) operator evaluates to be unknown (X) if
either LHS or RHS have an ”x”
Operation is inverse for the inequality (!=) operator.
$display ( 4’b0011 == 4’b1010 ) ; // 0 $
display ( 4’b0011 != 4’b1x10 ) ; // x
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Other operators
Case equality (===)
Case inequality (!==)
operators are the same as the logical equality except that
they perform definitive match of bit positions that are Z or X
Example
valid = (A == 2’b11) ?1: 0;
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Bit-Wise Operators
Bit-wise operators perform bit-
wise manipulations on two
operands (vectors)
They compare each bit in one
operand with its corresponding
bit in the other operand to
calculate each bit of the result
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Bit-Wise Operators
Example:
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Unary Reduction Operator
Unary reduction operators
operate on all bits of a
single operand(vector) to
produce a single a single
operand(vector) to
produce a single-bit result
(scalar)
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Operator precedence
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Expressions with Operands Containing x or z
Arithmetic
If any bit is x or z, result is all x’s.
Divide by 0 produces all x’s.
Relational
If any bit is x or z, result is x.
Logical
== and != If any bit is x or z, result is x.
=== and !== All bits including x and z values must match for
equality
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Expressions with Operands Containing x or z
Bitwise
Defined by tables for 0, 1, x, z operands.
Reduction
Defined by tables as for bitwise operators.
Shifts
z changed to x. Vacated positions zero filled.
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Expressions with Operands Containing x or z
Conditional
Ifconditional expression is ambiguous (e.g., x
or z), both expressions are evaluated and
bitwise combined as follows: f(1,1) = 1, f(0,0) =
0, otherwise x.
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Blocking Assignments
Identified by =
Sequence of blocking
assignments executes
sequentially
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Non-Blocking Assignments
Identified by <=
Sequence of non-blocking
assignments executes
concurrently
/*Calculates b = 2a, c = b + a, d
<= c + a. All values used on RHS
are those at posedge clock. Note
that there are two assignments to
b and c. Only the last one is
effective. */
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Blocking Assignments – Inter
Assignment Delay
Delays evaluation of RHS
and assignment to LHS
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Blocking Assignment – Intra
Assignment Delay
Delays assignment to
LHS and subsequent
statements, not
evaluation of RHS
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Non-Blocking Assignment
Inter-Assignment Delay
Delays evaluation of
RHS and assignment to
LHS
Delays subsequent
statements
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Non-Blocking Assignment
Intra-Assignment Delay
Delays only assignment to LHS
